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daq2: xcvr pll changes

main
Rejeesh Kutty 2016-11-22 12:53:29 -05:00
parent 750b23621b
commit b1a9bd96f1
1 changed files with 17 additions and 0 deletions
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17
projects/daq2/common/daq2_bd.tcl
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@ -68,6 +68,23 @@ set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $util_daq2_xcvr
ad_connect sys_cpu_resetn util_daq2_xcvr/up_rstn
ad_connect sys_cpu_clk util_daq2_xcvr/up_clk
# reference clocks & resets
create_bd_port -dir I tx_ref_clk_0
create_bd_port -dir I rx_ref_clk_0
ad_connect tx_ref_clk_0 util_daq2_xcvr/qpll_ref_clk_0
ad_connect axi_ad9144_xcvr/up_pll_rst util_daq2_xcvr/up_qpll_rst_0
ad_connect rx_ref_clk_0 util_daq2_xcvr/cpll_ref_clk_0
ad_connect rx_ref_clk_0 util_daq2_xcvr/cpll_ref_clk_1
ad_connect rx_ref_clk_0 util_daq2_xcvr/cpll_ref_clk_2
ad_connect rx_ref_clk_0 util_daq2_xcvr/cpll_ref_clk_3
ad_connect axi_ad9680_xcvr/up_pll_rst util_daq2_xcvr/up_cpll_rst_0
ad_connect axi_ad9680_xcvr/up_pll_rst util_daq2_xcvr/up_cpll_rst_1
ad_connect axi_ad9680_xcvr/up_pll_rst util_daq2_xcvr/up_cpll_rst_2
ad_connect axi_ad9680_xcvr/up_pll_rst util_daq2_xcvr/up_cpll_rst_3
# connections (dac)
ad_xcvrcon util_daq2_xcvr axi_ad9144_xcvr axi_ad9144_jesd