diff --git a/library/axi_ad9783/axi_ad9783.v b/library/axi_ad9783/axi_ad9783.v
index ea42deac7..1ecd85e86 100755
--- a/library/axi_ad9783/axi_ad9783.v
+++ b/library/axi_ad9783/axi_ad9783.v
@@ -42,13 +42,10 @@ module axi_ad9783 #(
   parameter   FPGA_FAMILY = 0,
   parameter   SPEED_GRADE = 0,
   parameter   DEV_PACKAGE = 0,
-  parameter   SERDES_OR_DDR_N = 1,
-  parameter   MMCM_OR_BUFIO_N = 1,
   parameter   DAC_DDS_TYPE = 2,
   parameter   DAC_DDS_CORDIC_DW = 16,
   parameter   DAC_DDS_CORDIC_PHASE_DW = 16,
-  parameter   DAC_DATAPATH_DISABLE = 0,
-  parameter   IO_DELAY_GROUP = "dev_if_delay_group") (
+  parameter   DAC_DATAPATH_DISABLE = 0) (
 
   // dac interface
   // from dco1_p
@@ -126,7 +123,7 @@ module axi_ad9783 #(
 
   // signal name changes
 
-  assign up_clk = s_axi_aclk;
+  assign up_clk  = s_axi_aclk;
   assign up_rstn = s_axi_aresetn;
   assign dac_rst = dac_rst_s;
 
diff --git a/library/axi_ad9783/axi_ad9783_channel.v b/library/axi_ad9783/axi_ad9783_channel.v
index be5840cba..e89c465ae 100755
--- a/library/axi_ad9783/axi_ad9783_channel.v
+++ b/library/axi_ad9783/axi_ad9783_channel.v
@@ -86,8 +86,8 @@ module axi_ad9783_channel #(
   wire    [15:0]   dac_pat_data_2_s;
   wire    [ 3:0]   dac_data_sel_s;
 
-  reg     [23:0]  dac_prbs_data = 'd0;
-  reg     [15:0]  dac_prbs_counter = 'd0;
+  reg     [23:0]   dac_prbs_data = 'd0;
+  reg     [15:0]   dac_prbs_counter = 'd0;
 
 
   // pn23 function
@@ -171,7 +171,9 @@ module axi_ad9783_channel #(
 
   // single channel processor
 
-  up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
+  up_dac_channel #(
+    .CHANNEL_ID(CHANNEL_ID))
+  i_up_dac_channel (
     .dac_clk (dac_div_clk),
     .dac_rst (dac_rst),
     .dac_dds_scale_1 (dac_dds_scale_1_s),
diff --git a/library/axi_ad9783/axi_ad9783_core.v b/library/axi_ad9783/axi_ad9783_core.v
index 7e1add4c3..9b26714c4 100755
--- a/library/axi_ad9783/axi_ad9783_core.v
+++ b/library/axi_ad9783/axi_ad9783_core.v
@@ -113,12 +113,12 @@ module axi_ad9783_core #(
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 0) begin
       up_rdata <= 'd0;
-      up_rack <= 'd0;
-      up_wack <= 'd0;
+      up_rack  <= 'd0;
+      up_wack  <= 'd0;
     end else begin
       up_rdata <= up_rdata_s | up_rdata_0_s | up_rdata_1_s;
-      up_rack <= up_rack_s | up_rack_0_s | up_rack_1_s;
-      up_wack <= up_wack_s | up_wack_0_s | up_wack_1_s;
+      up_rack  <= up_rack_s | up_rack_0_s | up_rack_1_s;
+      up_wack  <= up_wack_s | up_wack_0_s | up_wack_1_s;
     end
   end
 
@@ -187,8 +187,8 @@ module axi_ad9783_core #(
     .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
     .FPGA_FAMILY (FPGA_FAMILY),
     .SPEED_GRADE (SPEED_GRADE),
-    .DEV_PACKAGE (DEV_PACKAGE)
-  ) i_up_dac_common (
+    .DEV_PACKAGE (DEV_PACKAGE))
+  i_up_dac_common (
     .mmcm_rst (),
     .dac_clk (dac_div_clk),
     .dac_rst (dac_rst),
diff --git a/library/axi_ad9783/axi_ad9783_if.v b/library/axi_ad9783/axi_ad9783_if.v
index f63e038b3..cb6bd94a1 100755
--- a/library/axi_ad9783/axi_ad9783_if.v
+++ b/library/axi_ad9783/axi_ad9783_if.v
@@ -147,8 +147,8 @@ module axi_ad9783_if #(
     .BUFGCE_DIVIDE (4),
     .IS_CE_INVERTED (1'b0),
     .IS_CLR_INVERTED (1'b0),
-    .IS_I_INVERTED (1'b0)
-  ) i_dac_div_clk_rbuf (
+    .IS_I_INVERTED (1'b0))
+  i_dac_div_clk_rbuf (
     .O (dac_div_clk_s),
     .CE (1'b1),
     .CLR (1'b0),