From b27f3ac18f8f97cb9e5672ca5d5e8f4bf0b93263 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Tue, 2 Jun 2020 17:56:17 +0100 Subject: [PATCH] adrv9001:zcu102: Initial version Generic project that supports CMOS or LVDS interface for the ADRV9001 transceiver. --- projects/adrv9001/Makefile | 6 + projects/adrv9001/common/adrv9001_bd.tcl | 262 +++++++++++++++++++ projects/adrv9001/zcu102/Makefile | 22 ++ projects/adrv9001/zcu102/cmos_constr.xdc | 54 ++++ projects/adrv9001/zcu102/lvds_constr.xdc | 55 ++++ projects/adrv9001/zcu102/system_bd.tcl | 13 + projects/adrv9001/zcu102/system_constr.xdc | 44 ++++ projects/adrv9001/zcu102/system_project.tcl | 45 ++++ projects/adrv9001/zcu102/system_top.v | 265 ++++++++++++++++++++ 9 files changed, 766 insertions(+) create mode 100644 projects/adrv9001/Makefile create mode 100644 projects/adrv9001/common/adrv9001_bd.tcl create mode 100644 projects/adrv9001/zcu102/Makefile create mode 100644 projects/adrv9001/zcu102/cmos_constr.xdc create mode 100644 projects/adrv9001/zcu102/lvds_constr.xdc create mode 100644 projects/adrv9001/zcu102/system_bd.tcl create mode 100644 projects/adrv9001/zcu102/system_constr.xdc create mode 100644 projects/adrv9001/zcu102/system_project.tcl create mode 100644 projects/adrv9001/zcu102/system_top.v diff --git a/projects/adrv9001/Makefile b/projects/adrv9001/Makefile new file mode 100644 index 000000000..4af18d6e7 --- /dev/null +++ b/projects/adrv9001/Makefile @@ -0,0 +1,6 @@ +#################################################################################### +## Copyright 2018(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### + +include ../scripts/project-toplevel.mk diff --git a/projects/adrv9001/common/adrv9001_bd.tcl b/projects/adrv9001/common/adrv9001_bd.tcl new file mode 100644 index 000000000..535c5ade3 --- /dev/null +++ b/projects/adrv9001/common/adrv9001_bd.tcl @@ -0,0 +1,262 @@ +create_bd_port -dir I ref_clk + +create_bd_port -dir I tx_output_enable + +create_bd_port -dir I mssi_sync + +# adrv9001 interface +create_bd_port -dir I rx1_dclk_in_n +create_bd_port -dir I rx1_dclk_in_p +create_bd_port -dir I rx1_idata_in_n +create_bd_port -dir I rx1_idata_in_p +create_bd_port -dir I rx1_qdata_in_n +create_bd_port -dir I rx1_qdata_in_p +create_bd_port -dir I rx1_strobe_in_n +create_bd_port -dir I rx1_strobe_in_p + +create_bd_port -dir I rx2_dclk_in_n +create_bd_port -dir I rx2_dclk_in_p +create_bd_port -dir I rx2_idata_in_n +create_bd_port -dir I rx2_idata_in_p +create_bd_port -dir I rx2_qdata_in_n +create_bd_port -dir I rx2_qdata_in_p +create_bd_port -dir I rx2_strobe_in_n +create_bd_port -dir I rx2_strobe_in_p + +create_bd_port -dir O tx1_dclk_out_n +create_bd_port -dir O tx1_dclk_out_p +create_bd_port -dir I tx1_dclk_in_n +create_bd_port -dir I tx1_dclk_in_p +create_bd_port -dir O tx1_idata_out_n +create_bd_port -dir O tx1_idata_out_p +create_bd_port -dir O tx1_qdata_out_n +create_bd_port -dir O tx1_qdata_out_p +create_bd_port -dir O tx1_strobe_out_n +create_bd_port -dir O tx1_strobe_out_p + +create_bd_port -dir O tx2_dclk_out_n +create_bd_port -dir O tx2_dclk_out_p +create_bd_port -dir I tx2_dclk_in_n +create_bd_port -dir I tx2_dclk_in_p +create_bd_port -dir O tx2_idata_out_n +create_bd_port -dir O tx2_idata_out_p +create_bd_port -dir O tx2_qdata_out_n +create_bd_port -dir O tx2_qdata_out_p +create_bd_port -dir O tx2_strobe_out_n +create_bd_port -dir O tx2_strobe_out_p + +# adrv9001 + +ad_ip_instance axi_adrv9001 axi_adrv9001 +ad_ip_parameter axi_adrv9001 CONFIG.CMOS_LVDS_N $ad_project_params(CMOS_LVDS_N) + +# dma for rx1 + +ad_ip_instance axi_dmac axi_adrv9001_rx1_dma +ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.DMA_TYPE_SRC 2 +ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.DMA_TYPE_DEST 0 +ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.CYCLIC 0 +ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.SYNC_TRANSFER_START 0 +ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.AXI_SLICE_DEST 0 +ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.DMA_DATA_WIDTH_SRC 64 + +ad_ip_instance util_cpack2 util_adc_1_pack { \ + NUM_OF_CHANNELS 4 \ + SAMPLE_DATA_WIDTH 16 \ +} + +# dma for rx2 + +ad_ip_instance axi_dmac axi_adrv9001_rx2_dma +ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.DMA_TYPE_SRC 2 +ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.DMA_TYPE_DEST 0 +ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.CYCLIC 0 +ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.SYNC_TRANSFER_START 0 +ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.AXI_SLICE_DEST 0 +ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.DMA_DATA_WIDTH_SRC 32 + +ad_ip_instance util_cpack2 util_adc_2_pack { \ + NUM_OF_CHANNELS 2 \ + SAMPLE_DATA_WIDTH 16 \ +} + +# dma for tx1 + +ad_ip_instance axi_dmac axi_adrv9001_tx1_dma +ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.DMA_TYPE_SRC 0 +ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.DMA_TYPE_DEST 1 +ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.CYCLIC 1 +ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.SYNC_TRANSFER_START 0 +ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.AXI_SLICE_DEST 0 +ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.DMA_DATA_WIDTH_DEST 64 + +ad_ip_instance util_upack2 util_dac_1_upack { \ + NUM_OF_CHANNELS 4 \ + SAMPLE_DATA_WIDTH 16 \ +} + +# dma for tx1 + +ad_ip_instance axi_dmac axi_adrv9001_tx2_dma +ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.DMA_TYPE_SRC 0 +ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.DMA_TYPE_DEST 1 +ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.CYCLIC 1 +ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.SYNC_TRANSFER_START 0 +ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.AXI_SLICE_DEST 0 +ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.DMA_DATA_WIDTH_DEST 32 + +ad_ip_instance util_upack2 util_dac_2_upack { \ + NUM_OF_CHANNELS 2 \ + SAMPLE_DATA_WIDTH 16 \ +} + +# ad9001 connections + +ad_connect $sys_iodelay_clk axi_adrv9001/delay_clk +ad_connect axi_adrv9001/adc_1_clk axi_adrv9001_rx1_dma/fifo_wr_clk +ad_connect axi_adrv9001/adc_1_clk util_adc_1_pack/clk + +ad_connect axi_adrv9001/adc_2_clk axi_adrv9001_rx2_dma/fifo_wr_clk +ad_connect axi_adrv9001/adc_2_clk util_adc_2_pack/clk + +ad_connect axi_adrv9001/dac_1_clk axi_adrv9001_tx1_dma/m_axis_aclk +ad_connect axi_adrv9001/dac_1_clk util_dac_1_upack/clk + +ad_connect axi_adrv9001/dac_2_clk axi_adrv9001_tx2_dma/m_axis_aclk +ad_connect axi_adrv9001/dac_2_clk util_dac_2_upack/clk + +ad_connect ref_clk axi_adrv9001/ref_clk + +ad_connect tx_output_enable axi_adrv9001/tx_output_enable + +ad_connect mssi_sync axi_adrv9001/mssi_sync + +ad_connect rx1_dclk_in_n axi_adrv9001/rx1_dclk_in_n_NC +ad_connect rx1_dclk_in_p axi_adrv9001/rx1_dclk_in_p_dclk_in +ad_connect rx1_idata_in_n axi_adrv9001/rx1_idata_in_n_idata0 +ad_connect rx1_idata_in_p axi_adrv9001/rx1_idata_in_p_idata1 +ad_connect rx1_qdata_in_n axi_adrv9001/rx1_qdata_in_n_qdata2 +ad_connect rx1_qdata_in_p axi_adrv9001/rx1_qdata_in_p_qdata3 +ad_connect rx1_strobe_in_n axi_adrv9001/rx1_strobe_in_n_NC +ad_connect rx1_strobe_in_p axi_adrv9001/rx1_strobe_in_p_strobe_in + +ad_connect rx2_dclk_in_n axi_adrv9001/rx2_dclk_in_n_NC +ad_connect rx2_dclk_in_p axi_adrv9001/rx2_dclk_in_p_dclk_in +ad_connect rx2_idata_in_n axi_adrv9001/rx2_idata_in_n_idata0 +ad_connect rx2_idata_in_p axi_adrv9001/rx2_idata_in_p_idata1 +ad_connect rx2_qdata_in_n axi_adrv9001/rx2_qdata_in_n_qdata2 +ad_connect rx2_qdata_in_p axi_adrv9001/rx2_qdata_in_p_qdata3 +ad_connect rx2_strobe_in_n axi_adrv9001/rx2_strobe_in_n_NC +ad_connect rx2_strobe_in_p axi_adrv9001/rx2_strobe_in_p_strobe_in + +ad_connect tx1_dclk_out_n axi_adrv9001/tx1_dclk_out_n_NC +ad_connect tx1_dclk_out_p axi_adrv9001/tx1_dclk_out_p_dclk_out +ad_connect tx1_dclk_in_n axi_adrv9001/tx1_dclk_in_n_NC +ad_connect tx1_dclk_in_p axi_adrv9001/tx1_dclk_in_p_dclk_in +ad_connect tx1_idata_out_n axi_adrv9001/tx1_idata_out_n_idata0 +ad_connect tx1_idata_out_p axi_adrv9001/tx1_idata_out_p_idata1 +ad_connect tx1_qdata_out_n axi_adrv9001/tx1_qdata_out_n_qdata2 +ad_connect tx1_qdata_out_p axi_adrv9001/tx1_qdata_out_p_qdata3 +ad_connect tx1_strobe_out_n axi_adrv9001/tx1_strobe_out_n_NC +ad_connect tx1_strobe_out_p axi_adrv9001/tx1_strobe_out_p_strobe_out + +ad_connect tx2_dclk_out_n axi_adrv9001/tx2_dclk_out_n_NC +ad_connect tx2_dclk_out_p axi_adrv9001/tx2_dclk_out_p_dclk_out +ad_connect tx2_dclk_in_n axi_adrv9001/tx2_dclk_in_n_NC +ad_connect tx2_dclk_in_p axi_adrv9001/tx2_dclk_in_p_dclk_in +ad_connect tx2_idata_out_n axi_adrv9001/tx2_idata_out_n_idata0 +ad_connect tx2_idata_out_p axi_adrv9001/tx2_idata_out_p_idata1 +ad_connect tx2_qdata_out_n axi_adrv9001/tx2_qdata_out_n_qdata2 +ad_connect tx2_qdata_out_p axi_adrv9001/tx2_qdata_out_p_qdata3 +ad_connect tx2_strobe_out_n axi_adrv9001/tx2_strobe_out_n_NC +ad_connect tx2_strobe_out_p axi_adrv9001/tx2_strobe_out_p_strobe_out + +# RX1_RX2 - CPACK - RX_DMA1 +ad_connect axi_adrv9001/adc_1_rst util_adc_1_pack/reset +ad_connect axi_adrv9001/adc_1_valid_i0 util_adc_1_pack/fifo_wr_en +ad_connect axi_adrv9001/adc_1_enable_i0 util_adc_1_pack/enable_0 +ad_connect axi_adrv9001/adc_1_data_i0 util_adc_1_pack/fifo_wr_data_0 +ad_connect axi_adrv9001/adc_1_enable_q0 util_adc_1_pack/enable_1 +ad_connect axi_adrv9001/adc_1_data_q0 util_adc_1_pack/fifo_wr_data_1 +ad_connect axi_adrv9001/adc_1_enable_i1 util_adc_1_pack/enable_2 +ad_connect axi_adrv9001/adc_1_data_i1 util_adc_1_pack/fifo_wr_data_2 +ad_connect axi_adrv9001/adc_1_enable_q1 util_adc_1_pack/enable_3 +ad_connect axi_adrv9001/adc_1_data_q1 util_adc_1_pack/fifo_wr_data_3 + +ad_connect axi_adrv9001/adc_1_dovf util_adc_1_pack/fifo_wr_overflow + +ad_connect util_adc_1_pack/packed_fifo_wr axi_adrv9001_rx1_dma/fifo_wr + +# RX2 - CPACK - RX_DMA2 +ad_connect axi_adrv9001/adc_2_rst util_adc_2_pack/reset +ad_connect axi_adrv9001/adc_2_valid_i0 util_adc_2_pack/fifo_wr_en +ad_connect axi_adrv9001/adc_2_enable_i0 util_adc_2_pack/enable_0 +ad_connect axi_adrv9001/adc_2_data_i0 util_adc_2_pack/fifo_wr_data_0 +ad_connect axi_adrv9001/adc_2_enable_q0 util_adc_2_pack/enable_1 +ad_connect axi_adrv9001/adc_2_data_q0 util_adc_2_pack/fifo_wr_data_1 + +ad_connect axi_adrv9001/adc_2_dovf util_adc_2_pack/fifo_wr_overflow + +ad_connect util_adc_2_pack/packed_fifo_wr axi_adrv9001_rx2_dma/fifo_wr + +# TX_DMA1 - UPACK - TX1 +ad_connect axi_adrv9001/dac_1_rst util_dac_1_upack/reset +ad_connect axi_adrv9001/dac_1_valid_i0 util_dac_1_upack/fifo_rd_en +ad_connect axi_adrv9001/dac_1_enable_i0 util_dac_1_upack/enable_0 +ad_connect axi_adrv9001/dac_1_data_i0 util_dac_1_upack/fifo_rd_data_0 +ad_connect axi_adrv9001/dac_1_enable_q0 util_dac_1_upack/enable_1 +ad_connect axi_adrv9001/dac_1_data_q0 util_dac_1_upack/fifo_rd_data_1 +ad_connect axi_adrv9001/dac_1_enable_i1 util_dac_1_upack/enable_2 +ad_connect axi_adrv9001/dac_1_data_i1 util_dac_1_upack/fifo_rd_data_2 +ad_connect axi_adrv9001/dac_1_enable_q1 util_dac_1_upack/enable_3 +ad_connect axi_adrv9001/dac_1_data_q1 util_dac_1_upack/fifo_rd_data_3 + +ad_connect axi_adrv9001_tx1_dma/m_axis util_dac_1_upack/s_axis +ad_connect axi_adrv9001/dac_1_dunf util_dac_1_upack/fifo_rd_underflow + +# TX_DMA2 - UPACK - TX2 +ad_connect axi_adrv9001/dac_2_rst util_dac_2_upack/reset +ad_connect axi_adrv9001/dac_2_valid_i0 util_dac_2_upack/fifo_rd_en +ad_connect axi_adrv9001/dac_2_enable_i0 util_dac_2_upack/enable_0 +ad_connect axi_adrv9001/dac_2_data_i0 util_dac_2_upack/fifo_rd_data_0 +ad_connect axi_adrv9001/dac_2_enable_q0 util_dac_2_upack/enable_1 +ad_connect axi_adrv9001/dac_2_data_q0 util_dac_2_upack/fifo_rd_data_1 + +ad_connect axi_adrv9001_tx2_dma/m_axis util_dac_2_upack/s_axis +ad_connect axi_adrv9001/dac_2_dunf util_dac_2_upack/fifo_rd_underflow + +# interconnect + +ad_cpu_interconnect 0x44A00000 axi_adrv9001 +ad_cpu_interconnect 0x44A30000 axi_adrv9001_rx1_dma +ad_cpu_interconnect 0x44A40000 axi_adrv9001_rx2_dma +ad_cpu_interconnect 0x44A50000 axi_adrv9001_tx1_dma +ad_cpu_interconnect 0x44A60000 axi_adrv9001_tx2_dma + +# memory inteconnect + +ad_mem_hp1_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1 +ad_mem_hp1_interconnect $sys_dma_clk axi_adrv9001_rx1_dma/m_dest_axi +ad_mem_hp1_interconnect $sys_dma_clk axi_adrv9001_rx2_dma/m_dest_axi +ad_mem_hp1_interconnect $sys_dma_clk axi_adrv9001_tx1_dma/m_src_axi +ad_mem_hp1_interconnect $sys_dma_clk axi_adrv9001_tx2_dma/m_src_axi + +ad_connect $sys_dma_resetn axi_adrv9001_rx1_dma/m_dest_axi_aresetn +ad_connect $sys_dma_resetn axi_adrv9001_rx2_dma/m_dest_axi_aresetn +ad_connect $sys_dma_resetn axi_adrv9001_tx1_dma/m_src_axi_aresetn +ad_connect $sys_dma_resetn axi_adrv9001_tx2_dma/m_src_axi_aresetn +# interrupts + +ad_cpu_interrupt ps-13 mb-12 axi_adrv9001_rx1_dma/irq +ad_cpu_interrupt ps-12 mb-11 axi_adrv9001_rx2_dma/irq +ad_cpu_interrupt ps-11 mb-6 axi_adrv9001_tx1_dma/irq +ad_cpu_interrupt ps-10 mb-5 axi_adrv9001_tx2_dma/irq + diff --git a/projects/adrv9001/zcu102/Makefile b/projects/adrv9001/zcu102/Makefile new file mode 100644 index 000000000..32cbf51be --- /dev/null +++ b/projects/adrv9001/zcu102/Makefile @@ -0,0 +1,22 @@ +#################################################################################### +## Copyright 2018(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := adrv9001_zcu102 + +M_DEPS += lvds_constr.xdc +M_DEPS += cmos_constr.xdc +M_DEPS += ../common/adrv9001_bd.tcl +M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc +M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v + +LIB_DEPS += axi_adrv9001 +LIB_DEPS += axi_dmac +LIB_DEPS += axi_sysid +LIB_DEPS += sysid_rom +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 + +include ../../scripts/project-xilinx.mk diff --git a/projects/adrv9001/zcu102/cmos_constr.xdc b/projects/adrv9001/zcu102/cmos_constr.xdc new file mode 100644 index 000000000..ccc86d427 --- /dev/null +++ b/projects/adrv9001/zcu102/cmos_constr.xdc @@ -0,0 +1,54 @@ +set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVCMOS18 } [get_ports rx1_dclk_out_n] ;## FMC_HPC0_LA00_CC_N IO_L13N_T2L_N1_GC_QBC_66 +set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS18 } [get_ports rx1_dclk_out_p] ;## FMC_HPC0_LA00_CC_P IO_L13P_T2L_N0_GC_QBC_66 +set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS18 } [get_ports rx1_idata_out_n] ;## FMC_HPC0_LA03_N IO_L22N_T3U_N7_DBC_AD0N_66 +set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS18 } [get_ports rx1_idata_out_p] ;## FMC_HPC0_LA03_P IO_L22P_T3U_N6_DBC_AD0P_66 +set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVCMOS18 } [get_ports rx1_qdata_out_n] ;## FMC_HPC0_LA04_N IO_L21N_T3L_N5_AD8N_66 +set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVCMOS18 } [get_ports rx1_qdata_out_p] ;## FMC_HPC0_LA04_P IO_L21P_T3L_N4_AD8P_66 +set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVCMOS18 } [get_ports rx1_strobe_out_n] ;## FMC_HPC0_LA02_N IO_L23N_T3U_N9_66 +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS18 } [get_ports rx1_strobe_out_p] ;## FMC_HPC0_LA02_P IO_L23P_T3U_N8_66 + +set_property -dict {PACKAGE_PIN N11 IOSTANDARD LVCMOS18 } [get_ports rx2_dclk_out_n] ;## FMC_HPC0_LA17_CC_N IO_L13N_T2L_N1_GC_QBC_67 +set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVCMOS18 } [get_ports rx2_dclk_out_p] ;## FMC_HPC0_LA17_CC_P IO_L13P_T2L_N0_GC_QBC_67 +set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS18 } [get_ports rx2_idata_out_n] ;## FMC_HPC0_LA20_N IO_L22N_T3U_N7_DBC_AD0N_67 +set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS18 } [get_ports rx2_idata_out_p] ;## FMC_HPC0_LA20_P IO_L22P_T3U_N6_DBC_AD0P_67 +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18 } [get_ports rx2_qdata_out_n] ;## FMC_HPC0_LA19_N IO_L23N_T3U_N9_67 +set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18 } [get_ports rx2_qdata_out_p] ;## FMC_HPC0_LA19_P IO_L23P_T3U_N8_67 +set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVCMOS18 } [get_ports rx2_strobe_out_n] ;## FMC_HPC0_LA21_N IO_L21N_T3L_N5_AD8N_67 +set_property -dict {PACKAGE_PIN P12 IOSTANDARD LVCMOS18 } [get_ports rx2_strobe_out_p] ;## FMC_HPC0_LA21_P IO_L21P_T3L_N4_AD8P_67 + +set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS18 } [get_ports tx1_dclk_in_n] ;## FMC_HPC0_LA07_N IO_L18N_T2U_N11_AD2N_66 +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS18 } [get_ports tx1_dclk_in_p] ;## FMC_HPC0_LA07_P IO_L18P_T2U_N10_AD2P_66 +set_property -dict {PACKAGE_PIN AC4 IOSTANDARD LVCMOS18 } [get_ports tx1_dclk_out_n] ;## FMC_HPC0_LA01_CC_N IO_L16N_T2U_N7_QBC_AD3N_66 +set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVCMOS18 } [get_ports tx1_dclk_out_p] ;## FMC_HPC0_LA01_CC_P IO_L16P_T2U_N6_QBC_AD3P_66 +set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVCMOS18 } [get_ports tx1_idata_in_n] ;## FMC_HPC0_LA08_N IO_L17N_T2U_N9_AD10N_66 +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS18 } [get_ports tx1_idata_in_p] ;## FMC_HPC0_LA08_P IO_L17P_T2U_N8_AD10P_66 +set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVCMOS18 } [get_ports tx1_qdata_in_n] ;## FMC_HPC0_LA05_N IO_L20N_T3L_N3_AD1N_66 +set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS18 } [get_ports tx1_qdata_in_p] ;## FMC_HPC0_LA05_P IO_L20P_T3L_N2_AD1P_66 +set_property -dict {PACKAGE_PIN AC1 IOSTANDARD LVCMOS18 } [get_ports tx1_strobe_in_n] ;## FMC_HPC0_LA06_N IO_L19N_T3L_N1_DBC_AD9N_66 +set_property -dict {PACKAGE_PIN AC2 IOSTANDARD LVCMOS18 } [get_ports tx1_strobe_in_p] ;## FMC_HPC0_LA06_P IO_L19P_T3L_N0_DBC_AD9P_66 + +set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS18 } [get_ports tx2_dclk_in_n] ;## FMC_HPC0_LA22_N IO_L20N_T3L_N3_AD1N_67 +set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS18 } [get_ports tx2_dclk_in_p] ;## FMC_HPC0_LA22_P IO_L20P_T3L_N2_AD1P_67 +set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18 } [get_ports tx2_dclk_out_n] ;## FMC_HPC0_LA18_CC_N IO_L16N_T2U_N7_QBC_AD3N_67 +set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS18 } [get_ports tx2_dclk_out_p] ;## FMC_HPC0_LA18_CC_P IO_L16P_T2U_N6_QBC_AD3P_67 +set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS18 } [get_ports tx2_idata_in_n] ;## FMC_HPC0_LA23_N IO_L19N_T3L_N1_DBC_AD9N_67 +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS18 } [get_ports tx2_idata_in_p] ;## FMC_HPC0_LA23_P IO_L19P_T3L_N0_DBC_AD9P_67 +set_property -dict {PACKAGE_PIN L11 IOSTANDARD LVCMOS18 } [get_ports tx2_qdata_in_n] ;## FMC_HPC0_LA25_N IO_L17N_T2U_N9_AD10N_67 +set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVCMOS18 } [get_ports tx2_qdata_in_p] ;## FMC_HPC0_LA25_P IO_L17P_T2U_N8_AD10P_67 +set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18 } [get_ports tx2_strobe_in_n] ;## FMC_HPC0_LA24_N IO_L18N_T2U_N11_AD2N_67 +set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18 } [get_ports tx2_strobe_in_p] ;## FMC_HPC0_LA24_P IO_L18P_T2U_N10_AD2P_67 + +# clocks + +create_clock -name ref_clk -period 25.00 [get_ports fpga_ref_clk_p] + +create_clock -name rx1_dclk_out -period 12.5 [get_ports rx1_dclk_out_p] +create_clock -name rx2_dclk_out -period 12.5 [get_ports rx2_dclk_out_p] +create_clock -name tx1_dclk_out -period 12.5 [get_ports tx1_dclk_out_p] +create_clock -name tx2_dclk_out -period 12.5 [get_ports tx2_dclk_out_p] + +set_clock_latency -source -early 2 [get_clocks rx1_dclk_out] +set_clock_latency -source -early 2 [get_clocks rx2_dclk_out] + +set_clock_latency -source -late 5 [get_clocks rx1_dclk_out] +set_clock_latency -source -late 5 [get_clocks rx2_dclk_out] diff --git a/projects/adrv9001/zcu102/lvds_constr.xdc b/projects/adrv9001/zcu102/lvds_constr.xdc new file mode 100644 index 000000000..5539736fc --- /dev/null +++ b/projects/adrv9001/zcu102/lvds_constr.xdc @@ -0,0 +1,55 @@ +set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_dclk_out_n] ;## FMC_HPC0_LA00_CC_N IO_L13N_T2L_N1_GC_QBC_66 +set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_dclk_out_p] ;## FMC_HPC0_LA00_CC_P IO_L13P_T2L_N0_GC_QBC_66 +set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_idata_out_n] ;## FMC_HPC0_LA03_N IO_L22N_T3U_N7_DBC_AD0N_66 +set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_idata_out_p] ;## FMC_HPC0_LA03_P IO_L22P_T3U_N6_DBC_AD0P_66 +set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_qdata_out_n] ;## FMC_HPC0_LA04_N IO_L21N_T3L_N5_AD8N_66 +set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_qdata_out_p] ;## FMC_HPC0_LA04_P IO_L21P_T3L_N4_AD8P_66 +set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_strobe_out_n] ;## FMC_HPC0_LA02_N IO_L23N_T3U_N9_66 +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_strobe_out_p] ;## FMC_HPC0_LA02_P IO_L23P_T3U_N8_66 + +set_property -dict {PACKAGE_PIN N11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_dclk_out_n] ;## FMC_HPC0_LA17_CC_N IO_L13N_T2L_N1_GC_QBC_67 +set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_dclk_out_p] ;## FMC_HPC0_LA17_CC_P IO_L13P_T2L_N0_GC_QBC_67 +set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_idata_out_n] ;## FMC_HPC0_LA20_N IO_L22N_T3U_N7_DBC_AD0N_67 +set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_idata_out_p] ;## FMC_HPC0_LA20_P IO_L22P_T3U_N6_DBC_AD0P_67 +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_qdata_out_n] ;## FMC_HPC0_LA19_N IO_L23N_T3U_N9_67 +set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_qdata_out_p] ;## FMC_HPC0_LA19_P IO_L23P_T3U_N8_67 +set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_strobe_out_n] ;## FMC_HPC0_LA21_N IO_L21N_T3L_N5_AD8N_67 +set_property -dict {PACKAGE_PIN P12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_strobe_out_p] ;## FMC_HPC0_LA21_P IO_L21P_T3L_N4_AD8P_67 + +set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVDS} [get_ports tx1_dclk_in_n] ;## FMC_HPC0_LA07_N IO_L18N_T2U_N11_AD2N_66 +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVDS} [get_ports tx1_dclk_in_p] ;## FMC_HPC0_LA07_P IO_L18P_T2U_N10_AD2P_66 +set_property -dict {PACKAGE_PIN AC4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx1_dclk_out_n] ;## FMC_HPC0_LA01_CC_N IO_L16N_T2U_N7_QBC_AD3N_66 +set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx1_dclk_out_p] ;## FMC_HPC0_LA01_CC_P IO_L16P_T2U_N6_QBC_AD3P_66 +set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVDS} [get_ports tx1_idata_in_n] ;## FMC_HPC0_LA08_N IO_L17N_T2U_N9_AD10N_66 +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVDS} [get_ports tx1_idata_in_p] ;## FMC_HPC0_LA08_P IO_L17P_T2U_N8_AD10P_66 +set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVDS} [get_ports tx1_qdata_in_n] ;## FMC_HPC0_LA05_N IO_L20N_T3L_N3_AD1N_66 +set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVDS} [get_ports tx1_qdata_in_p] ;## FMC_HPC0_LA05_P IO_L20P_T3L_N2_AD1P_66 +set_property -dict {PACKAGE_PIN AC1 IOSTANDARD LVDS} [get_ports tx1_strobe_in_n] ;## FMC_HPC0_LA06_N IO_L19N_T3L_N1_DBC_AD9N_66 +set_property -dict {PACKAGE_PIN AC2 IOSTANDARD LVDS} [get_ports tx1_strobe_in_p] ;## FMC_HPC0_LA06_P IO_L19P_T3L_N0_DBC_AD9P_66 + +set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVDS} [get_ports tx2_dclk_in_n] ;## FMC_HPC0_LA22_N IO_L20N_T3L_N3_AD1N_67 +set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVDS} [get_ports tx2_dclk_in_p] ;## FMC_HPC0_LA22_P IO_L20P_T3L_N2_AD1P_67 +set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx2_dclk_out_n] ;## FMC_HPC0_LA18_CC_N IO_L16N_T2U_N7_QBC_AD3N_67 +set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx2_dclk_out_p] ;## FMC_HPC0_LA18_CC_P IO_L16P_T2U_N6_QBC_AD3P_67 +set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVDS} [get_ports tx2_idata_in_n] ;## FMC_HPC0_LA23_N IO_L19N_T3L_N1_DBC_AD9N_67 +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVDS} [get_ports tx2_idata_in_p] ;## FMC_HPC0_LA23_P IO_L19P_T3L_N0_DBC_AD9P_67 +set_property -dict {PACKAGE_PIN L11 IOSTANDARD LVDS} [get_ports tx2_qdata_in_n] ;## FMC_HPC0_LA25_N IO_L17N_T2U_N9_AD10N_67 +set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVDS} [get_ports tx2_qdata_in_p] ;## FMC_HPC0_LA25_P IO_L17P_T2U_N8_AD10P_67 +set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVDS} [get_ports tx2_strobe_in_n] ;## FMC_HPC0_LA24_N IO_L18N_T2U_N11_AD2N_67 +set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVDS} [get_ports tx2_strobe_in_p] ;## FMC_HPC0_LA24_P IO_L18P_T2U_N10_AD2P_67 + +# clocks + +create_clock -name ref_clk -period 8.00 [get_ports fpga_ref_clk_p] + +create_clock -name rx1_dclk_out -period 2.034 [get_ports rx1_dclk_out_p] +create_clock -name rx2_dclk_out -period 2.034 [get_ports rx2_dclk_out_p] +create_clock -name tx1_dclk_out -period 2.034 [get_ports tx1_dclk_out_p] +create_clock -name tx2_dclk_out -period 2.034 [get_ports tx2_dclk_out_p] + +# Allow max skew of 0.5 ns between input clocks +set_clock_latency -source -early -0.25 [get_clocks rx1_dclk_out] +set_clock_latency -source -early -0.25 [get_clocks rx2_dclk_out] + +set_clock_latency -source -late 0.25 [get_clocks rx1_dclk_out] +set_clock_latency -source -late 0.25 [get_clocks rx2_dclk_out] diff --git a/projects/adrv9001/zcu102/system_bd.tcl b/projects/adrv9001/zcu102/system_bd.tcl new file mode 100644 index 000000000..f573b5d1e --- /dev/null +++ b/projects/adrv9001/zcu102/system_bd.tcl @@ -0,0 +1,13 @@ + +source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl +source ../common/adrv9001_bd.tcl + +ad_ip_parameter axi_adrv9001 CONFIG.USE_RX_CLK_FOR_TX 1 + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 +set sys_cstring "CMOS_LVDS_N=${ad_project_params(CMOS_LVDS_N)}" +sysid_gen_sys_init_file $sys_cstring + diff --git a/projects/adrv9001/zcu102/system_constr.xdc b/projects/adrv9001/zcu102/system_constr.xdc new file mode 100644 index 000000000..3a68aa4f3 --- /dev/null +++ b/projects/adrv9001/zcu102/system_constr.xdc @@ -0,0 +1,44 @@ +set_property -dict {PACKAGE_PIN AA7 IOSTANDARD LVCMOS18} [get_ports dev_clk_out] ; #FMC_HPC0_CLK0_M2C_P IO_L12P_T1U_N10_GC_66 +set_property -dict {PACKAGE_PIN AC6 IOSTANDARD LVDS} [get_ports dev_mcs_fpga_in_n] ; #FMC_HPC0_LA14_N IO_L7N_T1L_N1_QBC_AD13N_66 +set_property -dict {PACKAGE_PIN AC7 IOSTANDARD LVDS} [get_ports dev_mcs_fpga_in_p] ; #FMC_HPC0_LA14_P IO_L7P_T1L_N0_QBC_AD13P_66 + +set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS18} [get_ports dgpio_0] ; #FMC_HPC0_LA16_P IO_L5P_T0U_N8_AD14P_66 +set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS18} [get_ports dgpio_1] ; #FMC_HPC0_LA16_N IO_L5N_T0U_N9_AD14N_66 +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS18} [get_ports dgpio_2] ; #FMC_HPC0_LA15_N IO_L6N_T0U_N11_AD6N_66 +set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS18} [get_ports dgpio_3] ; #FMC_HPC0_LA11_N IO_L10N_T1U_N7_QBC_AD4N_66 +set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVCMOS18} [get_ports dgpio_4] ; #FMC_HPC0_LA09_N IO_L24N_T3U_N11_66 +set_property -dict {PACKAGE_PIN W4 IOSTANDARD LVCMOS18} [get_ports dgpio_5] ; #FMC_HPC0_LA10_N IO_L15N_T2L_N5_AD11N_66 +set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS18} [get_ports dgpio_6] ; #FMC_HPC0_LA27_P IO_L15P_T2L_N4_AD11P_67 +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports dgpio_7] ; #FMC_HPC0_LA26_P IO_L24P_T3U_N10_67 +set_property -dict {PACKAGE_PIN T7 IOSTANDARD LVCMOS18} [get_ports dgpio_8] ; #FMC_HPC0_LA28_P IO_L10P_T1U_N6_QBC_AD4P_67 +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS18} [get_ports dgpio_9] ; #FMC_HPC0_LA28_N IO_L10N_T1U_N7_QBC_AD4N_67 +set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS18} [get_ports dgpio_10] ; #FMC_HPC0_LA11_P IO_L10P_T1U_N6_QBC_AD4P_66 +set_property -dict {PACKAGE_PIN L10 IOSTANDARD LVCMOS18} [get_ports dgpio_11] ; #FMC_HPC0_LA27_N IO_L15N_T2L_N5_AD11N_67 + +set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports fpga_mcs_in_n] ; #FMC_HPC0_LA32_N IO_L6N_T0U_N11_AD6N_67 +set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports fpga_mcs_in_p] ; #FMC_HPC0_LA32_P IO_L6P_T0U_N10_AD6P_67 +set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports fpga_ref_clk_n] ; #FMC_HPC0_CLK1_M2C_N IO_L12N_T1U_N11_GC_67 +set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports fpga_ref_clk_p] ; #FMC_HPC0_CLK1_M2C_P IO_L12P_T1U_N10_GC_67 +set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS18} [get_ports gp_int] ; #FMC_HPC0_LA30_P IO_L8P_T1L_N2_AD5P_67 +set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVCMOS18} [get_ports mode] ; #FMC_HPC0_LA13_P IO_L8P_T1L_N2_AD5P_66 +set_property -dict {PACKAGE_PIN AC8 IOSTANDARD LVCMOS18} [get_ports reset_trx] ; #FMC_HPC0_LA13_N IO_L8N_T1L_N3_AD5N_66 + +set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS18} [get_ports rx1_enable] ; #FMC_HPC0_LA10_P IO_L15P_T2L_N4_AD11P_66 +set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports rx2_enable] ; #FMC_HPC0_LA26_N IO_L24N_T3U_N11_67 + +set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVCMOS18} [get_ports sm_fan_tach] ; #FMC_HPC0_CLK0_M2C_N IO_L12N_T1U_N11_GC_66 + +set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; #FMC_HPC0_LA12_P IO_L9P_T1L_N4_AD12P_66 +set_property -dict {PACKAGE_PIN U8 IOSTANDARD LVCMOS18} [get_ports spi_dio] ; #FMC_HPC0_LA29_N IO_L9N_T1L_N5_AD12N_67 +set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS18} [get_ports spi_do] ; #FMC_HPC0_LA12_N IO_L9N_T1L_N5_AD12N_66 +set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS18} [get_ports spi_en] ; #FMC_HPC0_LA15_P IO_L6P_T0U_N10_AD6P_66 + +set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVCMOS18} [get_ports tx1_enable] ; #FMC_HPC0_LA09_P IO_L24P_T3U_N10_66 +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS18} [get_ports tx2_enable] ; #FMC_HPC0_LA29_P IO_L9P_T1L_N4_AD12P_67 + +set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS18} [get_ports vadj_test_1] ; #FMC_HPC0_LA31_P IO_L7P_T1L_N0_QBC_AD13P_67 +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS18} [get_ports vadj_test_2] ; #FMC_HPC0_LA31_N IO_L7N_T1L_N1_QBC_AD13N_67 + +set_property UNAVAILABLE_DURING_CALIBRATION TRUE [get_ports tx1_strobe_in_p] +set_property UNAVAILABLE_DURING_CALIBRATION TRUE [get_ports tx2_idata_in_p] + diff --git a/projects/adrv9001/zcu102/system_project.tcl b/projects/adrv9001/zcu102/system_project.tcl new file mode 100644 index 000000000..ad3418c6e --- /dev/null +++ b/projects/adrv9001/zcu102/system_project.tcl @@ -0,0 +1,45 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +# The get_env_param procedure retrieves parameter value from the environment if exists, +# other case returns the default value specified in its second parameter field. +# +# How to use over-writable parameters from the environment: +# +# e.g. +# make CMOS_LVDS_N=0 +# or +# make CMOS_LVDS_N=1 +# +# +# Parameter description: +# CMOS_LVDS_N - type of interface +# 0 - LVDS +# 1 - CMOS + +set CMOS_LVDS_N [get_env_param CMOS_LVDS_N 1] + +adi_project adrv9001_zcu102 0 [list \ + CMOS_LVDS_N $CMOS_LVDS_N \ +] + +adi_project_files {} [list \ + "system_top.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ] + +if {$CMOS_LVDS_N == 0} { + adi_project_files {} [list \ + "lvds_constr.xdc" \ + ] +} else { + adi_project_files {} [list \ + "cmos_constr.xdc" \ + ] +} + +adi_project_run adrv9001_zcu102 + diff --git a/projects/adrv9001/zcu102/system_top.v b/projects/adrv9001/zcu102/system_top.v new file mode 100644 index 000000000..b7f10fa00 --- /dev/null +++ b/projects/adrv9001/zcu102/system_top.v @@ -0,0 +1,265 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + input [12:0] gpio_bd_i, + output [ 7:0] gpio_bd_o, + + inout iic_scl, + inout iic_sda, + + output spi_clk, + output spi_dio, + input spi_do, + output spi_en, + + // Device clock + input fpga_ref_clk_n, + input fpga_ref_clk_p, + // Device clock passed through 9001 + input dev_clk_out, + + input fpga_mcs_in_n, + input fpga_mcs_in_p, + output dev_mcs_fpga_in_n, + output dev_mcs_fpga_in_p, + + inout dgpio_0, + inout dgpio_1, + inout dgpio_2, + inout dgpio_3, + inout dgpio_4, + inout dgpio_5, + inout dgpio_6, + inout dgpio_7, + inout dgpio_8, + inout dgpio_9, + inout dgpio_10, + inout dgpio_11, + + inout gp_int, + inout mode, + inout reset_trx, + + input rx1_dclk_out_n, + input rx1_dclk_out_p, + inout rx1_enable, + input rx1_idata_out_n, + input rx1_idata_out_p, + input rx1_qdata_out_n, + input rx1_qdata_out_p, + input rx1_strobe_out_n, + input rx1_strobe_out_p, + + input rx2_dclk_out_n, + input rx2_dclk_out_p, + inout rx2_enable, + input rx2_idata_out_n, + input rx2_idata_out_p, + input rx2_qdata_out_n, + input rx2_qdata_out_p, + input rx2_strobe_out_n, + input rx2_strobe_out_p, + + output tx1_dclk_in_n, + output tx1_dclk_in_p, + input tx1_dclk_out_n, + input tx1_dclk_out_p, + inout tx1_enable, + output tx1_idata_in_n, + output tx1_idata_in_p, + output tx1_qdata_in_n, + output tx1_qdata_in_p, + output tx1_strobe_in_n, + output tx1_strobe_in_p, + + output tx2_dclk_in_n, + output tx2_dclk_in_p, + input tx2_dclk_out_n, + input tx2_dclk_out_p, + inout tx2_enable, + output tx2_idata_in_n, + output tx2_idata_in_p, + output tx2_qdata_in_n, + output tx2_qdata_in_p, + output tx2_strobe_in_n, + output tx2_strobe_in_p, + + inout sm_fan_tach, + output vadj_test_1, + output vadj_test_2 +); + // internal registers + reg [ 2:0] mcs_sync_m = 'd0; + reg dev_mcs_fpga_in = 1'b0; + + // internal signals + wire [94:0] gpio_i; + wire [94:0] gpio_o; + wire [94:0] gpio_t; + wire [ 2:0] spi_csn; + + wire fpga_ref_clk; + wire fpga_mcs_in; + + // instantiations + + IBUFDS i_ibufgs_fpga_ref_clk ( + .I (fpga_ref_clk_p), + .IB (fpga_ref_clk_n), + .O (fpga_ref_clk)); + + IBUFDS i_ibufgs_fpga_mcs_in ( + .I (fpga_mcs_in_p), + .IB (fpga_mcs_in_n), + .O (fpga_mcs_in)); + + OBUFDS i_obufds_dev_mcs_fpga_in ( + .I (dev_mcs_fpga_in), + .O (dev_mcs_fpga_in_p), + .OB (dev_mcs_fpga_in_n)); + + // multi-chip synchronization + // + always @(posedge fpga_ref_clk) begin + mcs_sync_m <= {mcs_sync_m[1:0], gpio_o[53]}; + dev_mcs_fpga_in <= mcs_sync_m[2] & ~mcs_sync_m[1]; + end + + // multi-ssi synchronization + // + assign mssi_sync = gpio_o[54]; + + assign {vadj_test_2,vadj_test_1} = 2'b11; + + ad_iobuf #(.DATA_WIDTH(20)) i_iobuf ( + .dio_t ({gpio_t[51:32]}), + .dio_i ({gpio_o[51:32]}), + .dio_o ({gpio_i[51:32]}), + .dio_p ({tx2_enable, + tx1_enable, + rx2_enable, + rx1_enable, + sm_fan_tach, + reset_trx, + mode, + gp_int, + dgpio_11, + dgpio_10, + dgpio_9, + dgpio_8, + dgpio_7, + dgpio_6, + dgpio_5, + dgpio_4, + dgpio_3, + dgpio_2, + dgpio_1, + dgpio_0 })); // 32 + + assign gpio_i[ 7: 0] = gpio_o[ 7: 0]; + assign gpio_i[20: 8] = gpio_bd_i; + assign gpio_bd_o = gpio_o[ 7: 0]; + + assign gpio_i[94:52] = gpio_o[94:52]; + assign gpio_i[31:21] = gpio_o[31:21]; + + assign spi_en = spi_csn[0]; + + system_wrapper i_system_wrapper ( + .ref_clk (fpga_ref_clk), + .mssi_sync (mssi_sync), + + .tx_output_enable (1'b1), + + .rx1_dclk_in_n (rx1_dclk_out_n), + .rx1_dclk_in_p (rx1_dclk_out_p), + .rx1_idata_in_n (rx1_idata_out_n), + .rx1_idata_in_p (rx1_idata_out_p), + .rx1_qdata_in_n (rx1_qdata_out_n), + .rx1_qdata_in_p (rx1_qdata_out_p), + .rx1_strobe_in_n (rx1_strobe_out_n), + .rx1_strobe_in_p (rx1_strobe_out_p), + + .rx2_dclk_in_n (rx2_dclk_out_n), + .rx2_dclk_in_p (rx2_dclk_out_p), + .rx2_idata_in_n (rx2_idata_out_n), + .rx2_idata_in_p (rx2_idata_out_p), + .rx2_qdata_in_n (rx2_qdata_out_n), + .rx2_qdata_in_p (rx2_qdata_out_p), + .rx2_strobe_in_n (rx2_strobe_out_n), + .rx2_strobe_in_p (rx2_strobe_out_p), + + .tx1_dclk_out_n (tx1_dclk_in_n), + .tx1_dclk_out_p (tx1_dclk_in_p), + .tx1_dclk_in_n (tx1_dclk_out_n), + .tx1_dclk_in_p (tx1_dclk_out_p), + .tx1_idata_out_n (tx1_idata_in_n), + .tx1_idata_out_p (tx1_idata_in_p), + .tx1_qdata_out_n (tx1_qdata_in_n), + .tx1_qdata_out_p (tx1_qdata_in_p), + .tx1_strobe_out_n (tx1_strobe_in_n), + .tx1_strobe_out_p (tx1_strobe_in_p), + + .tx2_dclk_out_n (tx2_dclk_in_n), + .tx2_dclk_out_p (tx2_dclk_in_p), + .tx2_dclk_in_n (tx2_dclk_out_n), + .tx2_dclk_in_p (tx2_dclk_out_p), + .tx2_idata_out_n (tx2_idata_in_n), + .tx2_idata_out_p (tx2_idata_in_p), + .tx2_qdata_out_n (tx2_qdata_in_n), + .tx2_qdata_out_p (tx2_qdata_in_p), + .tx2_strobe_out_n (tx2_strobe_in_n), + .tx2_strobe_out_p (tx2_strobe_in_p), + + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .spi0_sclk (spi_clk), + .spi0_csn (spi_csn), + .spi0_miso (spi_do), + .spi0_mosi (spi_dio), + .spi1_sclk (), + .spi1_csn (), + .spi1_miso (1'b0), + .spi1_mosi () + ); +endmodule + +// *************************************************************************** +// ***************************************************************************