From b2dc91b30dae891b6319d88e083f26e726f43ba0 Mon Sep 17 00:00:00 2001 From: PIoandan <128376819+PIoandan@users.noreply.github.com> Date: Wed, 24 Apr 2024 15:43:57 +0300 Subject: [PATCH] pulsar_adc_pmdz: Port to ZedBoard Added support for AD40xx family in the PulSAR ADC project. --------- Signed-off-by: Ioan-daniel Pop --- .github/CODEOWNERS | 3 - projects/ad40xx_fmc/Readme.md | 25 ---- projects/ad40xx_fmc/common/ad40xx_bd.tcl | 126 ------------------ projects/ad40xx_fmc/zed/system_bd.tcl | 34 ----- projects/{ad40xx_fmc => pulsar_adc}/Makefile | 2 +- projects/pulsar_adc/Readme.md | 68 ++++++++++ projects/pulsar_adc/common/ad40xx_fmc.txt | 9 ++ projects/pulsar_adc/common/adaq400x_pmod.txt | 8 ++ .../common/pulsar_adc_bd.tcl} | 1 + .../common/pulsar_adc_pmod.txt} | 0 .../coraz7s/Makefile | 4 +- .../coraz7s/system_bd.tcl | 4 +- .../coraz7s/system_constr.xdc | 2 +- .../coraz7s/system_project.tcl | 2 +- .../coraz7s/system_top.v | 2 +- .../{ad40xx_fmc => pulsar_adc}/zed/Makefile | 9 +- projects/pulsar_adc/zed/system_bd.tcl | 21 +++ .../zed/system_constr_ad40xx.xdc | 25 ++-- .../zed/system_constr_adaq400x.xdc | 15 ++- .../zed/system_project.tcl | 28 ++-- .../zed/system_top_ad40xx.v | 15 ++- .../zed/system_top_adaq400x.v | 15 ++- projects/pulsar_adc_pmdz/Makefile | 7 - projects/pulsar_adc_pmdz/Readme.md | 38 ------ 24 files changed, 172 insertions(+), 291 deletions(-) delete mode 100644 projects/ad40xx_fmc/Readme.md delete mode 100644 projects/ad40xx_fmc/common/ad40xx_bd.tcl delete mode 100644 projects/ad40xx_fmc/zed/system_bd.tcl rename projects/{ad40xx_fmc => pulsar_adc}/Makefile (85%) create mode 100755 projects/pulsar_adc/Readme.md create mode 100644 projects/pulsar_adc/common/ad40xx_fmc.txt create mode 100644 projects/pulsar_adc/common/adaq400x_pmod.txt rename projects/{pulsar_adc_pmdz/common/pulsar_adc_pmdz_bd.tcl => pulsar_adc/common/pulsar_adc_bd.tcl} (97%) rename projects/{pulsar_adc_pmdz/common/pulsar_adc_pmdz_pmod.txt => pulsar_adc/common/pulsar_adc_pmod.txt} (100%) rename projects/{pulsar_adc_pmdz => pulsar_adc}/coraz7s/Makefile (90%) rename projects/{pulsar_adc_pmdz => pulsar_adc}/coraz7s/system_bd.tcl (85%) rename projects/{pulsar_adc_pmdz => pulsar_adc}/coraz7s/system_constr.xdc (96%) rename projects/{pulsar_adc_pmdz => pulsar_adc}/coraz7s/system_project.tcl (90%) rename projects/{pulsar_adc_pmdz => pulsar_adc}/coraz7s/system_top.v (98%) rename projects/{ad40xx_fmc => pulsar_adc}/zed/Makefile (81%) create mode 100644 projects/pulsar_adc/zed/system_bd.tcl rename projects/{ad40xx_fmc => pulsar_adc}/zed/system_constr_ad40xx.xdc (50%) rename projects/{ad40xx_fmc => pulsar_adc}/zed/system_constr_adaq400x.xdc (64%) rename projects/{ad40xx_fmc => pulsar_adc}/zed/system_project.tcl (79%) rename projects/{ad40xx_fmc => pulsar_adc}/zed/system_top_ad40xx.v (94%) rename projects/{ad40xx_fmc => pulsar_adc}/zed/system_top_adaq400x.v (94%) delete mode 100644 projects/pulsar_adc_pmdz/Makefile delete mode 100755 projects/pulsar_adc_pmdz/Readme.md diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS index 9ddc93b55..92909d334 100644 --- a/.github/CODEOWNERS +++ b/.github/CODEOWNERS @@ -17,9 +17,6 @@ # Code owners for ad3552r_evb folder /projects/ad3552r_evb/ paul.pop@analog.com adrian.costina@analog.com -# Code owners for ad40xx_fmc folder -/projects/ad40xx_fmc/ pop.ioan-daniel@analog.com paul.pop@analog.com - # Code owners for ad4110 folder /projects/ad4110/ sergiu.arpadi@analog.com adrian.costina@analog.com diff --git a/projects/ad40xx_fmc/Readme.md b/projects/ad40xx_fmc/Readme.md deleted file mode 100644 index 534c3de64..000000000 --- a/projects/ad40xx_fmc/Readme.md +++ /dev/null @@ -1,25 +0,0 @@ -# AD40XX-FMCZ HDL Project - -Here are some pointers to help you: - * [Board Product Page](https://www.analog.com/eval-ad400x-fmcz) - * Parts : [18-Bit, 2 MSPS/1 MSPS/500 kSPS, Easy Drive, Differential SAR ADCs](https://www.analog.com/ad4003) - * Parts : [18-Bit, 2 MSPS/1 MSPS/500 kSPS, Easy Drive, Differential SAR ADCs](https://www.analog.com/ad4007) - * Parts : [18-Bit, 500 kSPS, Easy Drive, Differential SAR ADCs](https://www.analog.com/ad4011) - * Parts : [20-Bit, 1.8 MSPS/1 MSPS/500 kSPS, Easy Drive, Differential SAR ADCs](https://www.analog.com/ad4020) - * Project Doc: https://wiki.analog.com/resources/eval/user-guides/ad400x - * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad400x - * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/ad400x - -## Supported parts - * AD4000 - * AD4001 - * AD4002 - * AD4003 - * AD4004 - * AD4005 - * AD4006 - * AD4007 - * AD4008 - * AD4010 - * AD4011 - * AD4020 diff --git a/projects/ad40xx_fmc/common/ad40xx_bd.tcl b/projects/ad40xx_fmc/common/ad40xx_bd.tcl deleted file mode 100644 index 1fa1ad7e6..000000000 --- a/projects/ad40xx_fmc/common/ad40xx_bd.tcl +++ /dev/null @@ -1,126 +0,0 @@ -############################################################################### -## Copyright (C) 2019-2024 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 ad40xx_spi - - -## To support the 1.8MSPS (SCLK == 100 MHz), set the spi clock to 200 MHz -set_property -dict [list \ - CONFIG.PCW_EN_CLK2_PORT {1} \ - CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ $spi_clk_ref_frequency] [get_bd_cells sys_ps7] - -# create a SPI Engine architecture - -create_bd_cell -type hier spi_ad40xx -current_bd_instance /spi_ad40xx - - create_bd_pin -dir I -type clk clk - create_bd_pin -dir I -type rst resetn - create_bd_pin -dir I -type clk spi_clk - create_bd_pin -dir O irq - create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 m_spi - create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SAMPLE - - if {$ADC_RESOLUTION <= 16} { - set data_width 16 - } else { - set data_width 32 - }; - - ad_ip_instance spi_engine_execution execution - ad_ip_parameter execution CONFIG.DATA_WIDTH $data_width - ad_ip_parameter execution CONFIG.NUM_OF_CS 1 - ad_ip_parameter execution CONFIG.NUM_OF_SDI 1 - ad_ip_parameter execution CONFIG.SDO_DEFAULT 1 - ad_ip_parameter execution CONFIG.SDI_DELAY 1 - - ad_ip_instance axi_spi_engine axi_regmap - ad_ip_parameter axi_regmap CONFIG.DATA_WIDTH $data_width - ad_ip_parameter axi_regmap CONFIG.NUM_OFFLOAD 1 - ad_ip_parameter axi_regmap CONFIG.ASYNC_SPI_CLK 1 - - ad_ip_instance spi_engine_offload offload - ad_ip_parameter offload CONFIG.DATA_WIDTH $data_width - ad_ip_parameter offload CONFIG.ASYNC_SPI_CLK 1 - - ad_ip_instance spi_engine_interconnect interconnect - ad_ip_parameter interconnect CONFIG.DATA_WIDTH $data_width - - ad_ip_instance util_pulse_gen trigger_gen - - ## to setup the sample rate of the system change the PULSE_PERIOD value - ## the acutal sample rate will be PULSE_PERIOD * (1/sys_cpu_clk) - set sampling_cycle [expr int(ceil(double($spi_clk_ref_frequency * 1000000) / $ADC_SAMPLING_RATE))] - ad_ip_parameter trigger_gen CONFIG.PULSE_PERIOD $sampling_cycle - ad_ip_parameter trigger_gen CONFIG.PULSE_WIDTH 1 - - ad_connect axi_regmap/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl - ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl - ad_connect axi_regmap/spi_engine_ctrl interconnect/s1_ctrl - ad_connect interconnect/m_ctrl execution/ctrl - ad_connect offload/offload_sdi M_AXIS_SAMPLE - - ad_connect execution/spi m_spi - - ad_connect spi_clk offload/spi_clk - ad_connect spi_clk offload/ctrl_clk - ad_connect spi_clk execution/clk - ad_connect clk axi_regmap/s_axi_aclk - ad_connect spi_clk axi_regmap/spi_clk - ad_connect spi_clk interconnect/clk - ad_connect spi_clk trigger_gen/clk - - ad_connect axi_regmap/spi_resetn offload/spi_resetn - ad_connect axi_regmap/spi_resetn execution/resetn - ad_connect axi_regmap/spi_resetn interconnect/resetn - ad_connect axi_regmap/spi_resetn trigger_gen/rstn - ad_connect trigger_gen/load_config GND - ad_connect trigger_gen/pulse_width GND - ad_connect trigger_gen/pulse_period GND - - ad_connect trigger_gen/pulse offload/trigger - - ad_connect resetn axi_regmap/s_axi_aresetn - ad_connect irq axi_regmap/irq - -current_bd_instance / - -# asynchronous SPI clock, to support higher SCLK -ad_connect spi_clk sys_ps7/FCLK_CLK2 - -# dma to receive data stream - -ad_ip_instance axi_dmac axi_ad40xx_dma -ad_ip_parameter axi_ad40xx_dma CONFIG.DMA_TYPE_SRC 1 -ad_ip_parameter axi_ad40xx_dma CONFIG.DMA_TYPE_DEST 0 -ad_ip_parameter axi_ad40xx_dma CONFIG.CYCLIC 0 -ad_ip_parameter axi_ad40xx_dma CONFIG.SYNC_TRANSFER_START 0 -ad_ip_parameter axi_ad40xx_dma CONFIG.AXI_SLICE_SRC 1 -ad_ip_parameter axi_ad40xx_dma CONFIG.AXI_SLICE_DEST 1 -ad_ip_parameter axi_ad40xx_dma CONFIG.DMA_2D_TRANSFER 0 - - -ad_ip_parameter axi_ad40xx_dma CONFIG.DMA_DATA_WIDTH_SRC $data_width -ad_ip_parameter axi_ad40xx_dma CONFIG.DMA_DATA_WIDTH_DEST 64 - -ad_connect sys_cpu_clk spi_ad40xx/clk -ad_connect spi_clk axi_ad40xx_dma/s_axis_aclk -ad_connect sys_cpu_resetn spi_ad40xx/resetn -ad_connect sys_cpu_resetn axi_ad40xx_dma/m_dest_axi_aresetn - -ad_connect spi_clk spi_ad40xx/spi_clk - -ad_connect spi_ad40xx/m_spi ad40xx_spi - -ad_connect axi_ad40xx_dma/s_axis spi_ad40xx/M_AXIS_SAMPLE - -ad_cpu_interconnect 0x44a00000 spi_ad40xx/axi_regmap -ad_cpu_interconnect 0x44a30000 axi_ad40xx_dma - -ad_cpu_interrupt "ps-13" "mb-13" axi_ad40xx_dma/irq -ad_cpu_interrupt "ps-12" "mb-12" /spi_ad40xx/irq - -ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2 -ad_mem_hp2_interconnect sys_cpu_clk axi_ad40xx_dma/m_dest_axi diff --git a/projects/ad40xx_fmc/zed/system_bd.tcl b/projects/ad40xx_fmc/zed/system_bd.tcl deleted file mode 100644 index 46952e1c9..000000000 --- a/projects/ad40xx_fmc/zed/system_bd.tcl +++ /dev/null @@ -1,34 +0,0 @@ -############################################################################### -## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl -source $ad_hdl_dir/projects/scripts/adi_pd.tcl - -# specify the spi reference clock frequency in MHz -set spi_clk_ref_frequency 166 - -# specify ADC resolution -- supported resolutions 16/18/20 bits -set ADC_RESOLUTION [get_env_param ADC_RESOLUTION 20] - -# specify ADC sampling rate in samples/seconds - -# NOTE: This rate can be set just in turbo mode -- if turbo mode is not used -# the max rate should be 1.6 MSPS -# supported sampling rates: 2/1.8/1/0.5 MSPS depending on the board -set ADC_SAMPLING_RATE [get_env_param ADC_SAMPLING_RATE 1800000] - -source ../common/ad40xx_bd.tcl - -set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt; - -#system ID -ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 -ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path" -ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 - -set AD40XX_ADAQ400X_N [get_env_param AD40XX_ADAQ400X_N 1] -set sys_cstring "ad40xx: $AD40XX_ADAQ400X_N - adc_sampling_rate: $ADC_SAMPLING_RATE - adc_resolution: $ADC_RESOLUTION" -sysid_gen_sys_init_file $sys_cstring - diff --git a/projects/ad40xx_fmc/Makefile b/projects/pulsar_adc/Makefile similarity index 85% rename from projects/ad40xx_fmc/Makefile rename to projects/pulsar_adc/Makefile index 1402069e1..6667c4f44 100644 --- a/projects/ad40xx_fmc/Makefile +++ b/projects/pulsar_adc/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. +## Copyright (c) 2018 - 2024 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### diff --git a/projects/pulsar_adc/Readme.md b/projects/pulsar_adc/Readme.md new file mode 100755 index 000000000..4abfe5c59 --- /dev/null +++ b/projects/pulsar_adc/Readme.md @@ -0,0 +1,68 @@ +# PULSAR_ADC HDL Project + +Here are some pointers to help you: + * [Board Product Page](https://www.analog.com/eval-ad400x-fmcz) + * Parts : [AD7942: 14-Bit, 250 kSPS PulSAR, Pseudo Differential ADC in MSOP/LFCSP](https://www.analog.com/ad7942) + * Parts : [AD7946: 14-Bit, 500 kSPS PulSAR ADC in MSOP](https://www.analog.com/ad7946) + * Parts : [AD7988-1: 16-Bit Lower Power PulSAR ADCs in MSOP/LFCSP](https://www.analog.com/ad7988-1) + * Parts : [AD7685: 16-Bit, 250 kSPS PulSAR ADC in MSOP/QFN](https://www.analog.com/ad7685) + * Parts : [AD7687: 16-Bit, 1.5 LSB INL, 250 kSPS PulSAR Differential ADC in MSOP/QFN](https://www.analog.com/ad7687) + * Parts : [AD7691: 18-Bit, 1.5 LSB INL, 250 kSPS PulSAR Differential ADC in MSOP/QFN](https://www.analog.com/ad7691) + * Parts : [AD7686: 500 kSPS 16-BIT PulSAR A/D Converter in MSOP/QFN](https://www.analog.com/ad7686) + * Parts : [AD7688: 500 kSPS 16- BIT Differential PulSAR A/D Converter in µSOIC/QFN](https://www.analog.com/ad7688) + * Parts : [AD7693: 16-Bit, ±0.5 LSB, 500 kSPS PulSAR Differential A/D Converter in MSOP/QFN](https://www.analog.com/ad7693) + * Parts : [AD7988-5: 16-Bit Lower Power PulSAR ADCs in MSOP/LFCSP](https://www.analog.com/ad7988-5) + * Parts : [AD7980: 16-Bit, 1 MSPS, PulSAR ADC in MSOP/LFCSP](https://www.analog.com/ad7980) + * Parts : [AD7983: 16-Bit, 1.33 MSPS PulSAR ADC in MSOP/LFCSP](https://www.analog.com/ad7983) + * Parts : [AD7690: 18-Bit, 1.5 LSB INL, 400 kSPS PulSAR Differential ADC in MSOP/QFN](https://www.analog.com/ad7690) + * Parts : [AD7689: 16-Bit, 8-Channel, 250 kSPS PulSAR ADC](https://www.analog.com/ad7689) + * Parts : [AD4000: 16-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs](https://www.analog.com/ad4000) + * Parts : [AD4001: 16-Bit, 2 MSPS/1 MSPS, Precision, Differential SAR ADCs](https://www.analog.com/ad4001) + * Parts : [AD4002: 18-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs](https://www.analog.com/ad4002) + * Parts : [AD4003: 18-Bit, 2 MSPS/1 MSPS/500 kSPS, Easy Drive, Differential SAR ADCs](https://www.analog.com/ad4003) + * Parts : [AD4004: 16-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs](https://www.analog.com/ad4004) + * Parts : [AD4005: 16-Bit, 2 MSPS/1 MSPS, Precision, Differential SAR ADCs](https://www.analog.com/ad4005) + * Parts : [AD4006: 18-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs](https://www.analog.com/ad4006) + * Parts : [AD4007: 18-Bit, 2 MSPS/1 MSPS/500 kSPS, Easy Drive, Differential SAR ADCs](https://www.analog.com/ad4007) + * Parts : [AD4008: 16-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs](https://www.analog.com/ad4008) + * Parts : [AD4010: 18-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs](https://www.analog.com/ad4010) + * Parts : [AD4011: 18-Bit, 2 MSPS/1 MSPS/500 kSPS, Easy Drive, Differential SAR ADCs](https://www.analog.com/ad4011) + * Parts : [ADAQ4003: 18-Bit, 2 MSPS, Precision DAQ, Differential SAR ADCs](https://www.analog.com/adaq4003) + * Parts : [AD4020: 20-Bit, 1.8 MSPS/1 MSPS/500 kSPS, Easy Drive, Differential SAR ADCs](https://www.analog.com/ad4020) + + * Project Doc: https://wiki.analog.com/resources/eval/10-lead-pulsar-adc-evaluation-board + * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/pulsar_adc_pmods_hdl + * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/ad7476a + +## Supported parts + + * AD7942 + * AD7946 + * AD7988-1 + * AD7685 + * AD7687 + * AD7691 + * AD7686 + * AD7688 + * AD7693 + * AD7988-5 + * AD7980 + * AD7983 + * AD7690 + * AD7982 + * AD7984 + * AD7682 + * AD7689 + * AD4000 + * AD4001 + * AD4002 + * AD4003 + * AD4004 + * AD4005 + * AD4006 + * AD4007 + * AD4008 + * AD4010 + * AD4011 + * ADAQ4003 + * AD4020 \ No newline at end of file diff --git a/projects/pulsar_adc/common/ad40xx_fmc.txt b/projects/pulsar_adc/common/ad40xx_fmc.txt new file mode 100644 index 000000000..4ae0f6af8 --- /dev/null +++ b/projects/pulsar_adc/common/ad40xx_fmc.txt @@ -0,0 +1,9 @@ +FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination + +# ad40xx + +H7 FMC_LA02_P SDI_FMC ad40xx_spi_sdo LVCMOS25 IOB TRUE +D8 FMC_LA01_CC_P SDO_FMC ad40xx_spi_sdi LVCMOS25 IOB TRUE +G6 FMC_LA00_CC_P SCK_FMC ad40xx_spi_sclk LVCMOS25 IOB TRUE +G7 FMC_LA00_CC_N CNV_FMC ad40xx_spi_cs LVCMOS25 IOB TRUE +G10 FMC_LA03_N AMP_PD ad40xx_amp_pd LVCMOS25 IOB TRUE \ No newline at end of file diff --git a/projects/pulsar_adc/common/adaq400x_pmod.txt b/projects/pulsar_adc/common/adaq400x_pmod.txt new file mode 100644 index 000000000..e47ff4d7b --- /dev/null +++ b/projects/pulsar_adc/common/adaq400x_pmod.txt @@ -0,0 +1,8 @@ +Pin Port Schematic_name System_top_name IOSTANDARD Termination + +# adaq400x + +2 PMOD_2 SDI adaq400x_spi_sdo LVCMOS33 #N/A +3 PMOD_3 SDO adaq400x_spi_sdi LVCMOS33 #N/A +4 PMOD_4 SCK adaq400x_spi_sclk LVCMOS33 #N/A +1 PMOD_1 CNV adaq400x_spi_cs LVCMOS33 #N/A diff --git a/projects/pulsar_adc_pmdz/common/pulsar_adc_pmdz_bd.tcl b/projects/pulsar_adc/common/pulsar_adc_bd.tcl similarity index 97% rename from projects/pulsar_adc_pmdz/common/pulsar_adc_pmdz_bd.tcl rename to projects/pulsar_adc/common/pulsar_adc_bd.tcl index fad10f924..eec33060a 100644 --- a/projects/pulsar_adc_pmdz/common/pulsar_adc_pmdz_bd.tcl +++ b/projects/pulsar_adc/common/pulsar_adc_bd.tcl @@ -6,6 +6,7 @@ create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 pulsar_adc_spi source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl +# If the ADC resolution <= 16, data_width is set 16 else 32 set data_width 32 set async_spi_clk 1 set num_cs 1 diff --git a/projects/pulsar_adc_pmdz/common/pulsar_adc_pmdz_pmod.txt b/projects/pulsar_adc/common/pulsar_adc_pmod.txt similarity index 100% rename from projects/pulsar_adc_pmdz/common/pulsar_adc_pmdz_pmod.txt rename to projects/pulsar_adc/common/pulsar_adc_pmod.txt diff --git a/projects/pulsar_adc_pmdz/coraz7s/Makefile b/projects/pulsar_adc/coraz7s/Makefile similarity index 90% rename from projects/pulsar_adc_pmdz/coraz7s/Makefile rename to projects/pulsar_adc/coraz7s/Makefile index a714bb027..9ac32d0b9 100644 --- a/projects/pulsar_adc_pmdz/coraz7s/Makefile +++ b/projects/pulsar_adc/coraz7s/Makefile @@ -1,12 +1,12 @@ #################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. +## Copyright (c) 2018 - 2024 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### PROJECT_NAME := pulsar_adc_pmdz_coraz7s -M_DEPS += ../common/pulsar_adc_pmdz_bd.tcl +M_DEPS += ../common/pulsar_adc_bd.tcl M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc diff --git a/projects/pulsar_adc_pmdz/coraz7s/system_bd.tcl b/projects/pulsar_adc/coraz7s/system_bd.tcl similarity index 85% rename from projects/pulsar_adc_pmdz/coraz7s/system_bd.tcl rename to projects/pulsar_adc/coraz7s/system_bd.tcl index be70162f0..6fd2e2e36 100644 --- a/projects/pulsar_adc_pmdz/coraz7s/system_bd.tcl +++ b/projects/pulsar_adc/coraz7s/system_bd.tcl @@ -1,11 +1,11 @@ ############################################################################### -## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### source $ad_hdl_dir/projects/common/coraz7s/coraz7s_system_bd.tcl source $ad_hdl_dir/projects/scripts/adi_pd.tcl -source ../common/pulsar_adc_pmdz_bd.tcl +source ../common/pulsar_adc_bd.tcl set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt; diff --git a/projects/pulsar_adc_pmdz/coraz7s/system_constr.xdc b/projects/pulsar_adc/coraz7s/system_constr.xdc similarity index 96% rename from projects/pulsar_adc_pmdz/coraz7s/system_constr.xdc rename to projects/pulsar_adc/coraz7s/system_constr.xdc index 0edac4ec5..83c763388 100644 --- a/projects/pulsar_adc_pmdz/coraz7s/system_constr.xdc +++ b/projects/pulsar_adc/coraz7s/system_constr.xdc @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### diff --git a/projects/pulsar_adc_pmdz/coraz7s/system_project.tcl b/projects/pulsar_adc/coraz7s/system_project.tcl similarity index 90% rename from projects/pulsar_adc_pmdz/coraz7s/system_project.tcl rename to projects/pulsar_adc/coraz7s/system_project.tcl index 47a981297..d09991112 100755 --- a/projects/pulsar_adc_pmdz/coraz7s/system_project.tcl +++ b/projects/pulsar_adc/coraz7s/system_project.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2016-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### diff --git a/projects/pulsar_adc_pmdz/coraz7s/system_top.v b/projects/pulsar_adc/coraz7s/system_top.v similarity index 98% rename from projects/pulsar_adc_pmdz/coraz7s/system_top.v rename to projects/pulsar_adc/coraz7s/system_top.v index 9acb09c63..7c2653782 100644 --- a/projects/pulsar_adc_pmdz/coraz7s/system_top.v +++ b/projects/pulsar_adc/coraz7s/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad40xx_fmc/zed/Makefile b/projects/pulsar_adc/zed/Makefile similarity index 81% rename from projects/ad40xx_fmc/zed/Makefile rename to projects/pulsar_adc/zed/Makefile index 20d1fe7d4..864469367 100644 --- a/projects/ad40xx_fmc/zed/Makefile +++ b/projects/pulsar_adc/zed/Makefile @@ -1,23 +1,25 @@ #################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. +## Copyright (c) 2018 - 2024 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### -PROJECT_NAME := ad40xx_fmc_zed +PROJECT_NAME := pulsar_adc_pmdz_zed M_DEPS += system_constr_adaq400x.xdc M_DEPS += system_constr_ad40xx.xdc -M_DEPS += ../common/ad40xx_bd.tcl +M_DEPS += ../common/pulsar_adc_bd.tcl M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/zed/zed_system_constr.xdc M_DEPS += ../../common/zed/zed_system_bd.tcl +M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl M_DEPS += ../../../library/common/ad_iobuf.v LIB_DEPS += axi_clkgen LIB_DEPS += axi_dmac LIB_DEPS += axi_hdmi_tx LIB_DEPS += axi_i2s_adi +LIB_DEPS += axi_pwm_gen LIB_DEPS += axi_spdif_tx LIB_DEPS += axi_sysid LIB_DEPS += spi_engine/axi_spi_engine @@ -26,6 +28,5 @@ LIB_DEPS += spi_engine/spi_engine_interconnect LIB_DEPS += spi_engine/spi_engine_offload LIB_DEPS += sysid_rom LIB_DEPS += util_i2c_mixer -LIB_DEPS += util_pulse_gen include ../../scripts/project-xilinx.mk diff --git a/projects/pulsar_adc/zed/system_bd.tcl b/projects/pulsar_adc/zed/system_bd.tcl new file mode 100644 index 000000000..f51d37ad8 --- /dev/null +++ b/projects/pulsar_adc/zed/system_bd.tcl @@ -0,0 +1,21 @@ +############################################################################### +## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl + +source ../common/pulsar_adc_bd.tcl + +#system ID + +set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt; + +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 + +set AD40XX_ADAQ400X_N [get_env_param AD40XX_ADAQ400X_N 1] +set sys_cstring "ad40xx: $AD40XX_ADAQ400X_N" +sysid_gen_sys_init_file $sys_cstring diff --git a/projects/ad40xx_fmc/zed/system_constr_ad40xx.xdc b/projects/pulsar_adc/zed/system_constr_ad40xx.xdc similarity index 50% rename from projects/ad40xx_fmc/zed/system_constr_ad40xx.xdc rename to projects/pulsar_adc/zed/system_constr_ad40xx.xdc index e33ac3d1b..e3464b2a4 100644 --- a/projects/ad40xx_fmc/zed/system_constr_ad40xx.xdc +++ b/projects/pulsar_adc/zed/system_constr_ad40xx.xdc @@ -1,25 +1,28 @@ ############################################################################### -## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### # ad40xx_fmc SPI interface -set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad40xx_spi_sdo] ; ## H07 FMC_LPC_LA02_P -set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad40xx_spi_sdi] ; ## D08 FMC_LPC_LA01_CC_P -set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad40xx_spi_sclk] ; ## G06 FMC_LPC_LA00_CC_P -set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad40xx_spi_cs] ; ## G07 FMC_LPC_LA00_CC_N +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad40xx_spi_sdo] ; ## H7 FMC_LA02_P IO_L20P_T3_34 +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad40xx_spi_sdi] ; ## D8 FMC_LA01_CC_P IO_L14P_T2_SRCC_34 +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad40xx_spi_sclk] ; ## G6 FMC_LA00_CC_P IO_L13P_T2_MRCC_34 +set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad40xx_spi_cs] ; ## G7 FMC_LA00_CC_N IO_L13N_T2_MRCC_34 -set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports ad40xx_amp_pd] ; ## G10 FMC_LPC_LA03_N +set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports ad40xx_amp_pd] ; ## G10 FMC_LA03_N IO_L16N_T2_34 + +# NOTE: clk_fpga_0 is the first PL fabric clock, also called $sys_cpu_clk + +create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] -master_clock clk_fpga_0 [get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] ## There is a multi-cycle path between the axi_spi_engine's SDO_FIFO and the # execution's shift register, because we load new data into the shift register # in every DATA_WIDTH's x 8 cycle. (worst case scenario) # Set a multi-cycle delay of 8 spi_clk cycle, slightly over constraining the path. -set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks clk_fpga_2] -set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks clk_fpga_2] - -set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/execution/inst/left_aligned_reg*}] -from [get_clocks clk_fpga_2] -set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/execution/inst/left_aligned_reg*}] -from [get_clocks clk_fpga_2] +set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk] +set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk] +set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/spi_pulsar_adc_execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk] +set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/spi_pulsar_adc_execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk] diff --git a/projects/ad40xx_fmc/zed/system_constr_adaq400x.xdc b/projects/pulsar_adc/zed/system_constr_adaq400x.xdc similarity index 64% rename from projects/ad40xx_fmc/zed/system_constr_adaq400x.xdc rename to projects/pulsar_adc/zed/system_constr_adaq400x.xdc index 62481d5d9..341222667 100644 --- a/projects/ad40xx_fmc/zed/system_constr_adaq400x.xdc +++ b/projects/pulsar_adc/zed/system_constr_adaq400x.xdc @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -10,14 +10,17 @@ set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS33} [get_ports adaq400x_sp set_property -dict {PACKAGE_PIN AA9 IOSTANDARD LVCMOS33} [get_ports adaq400x_spi_sclk] ; ## JA4 set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_ports adaq400x_spi_cs] ; ## JA1 +# NOTE: clk_fpga_0 is the first PL fabric clock, also called $sys_cpu_clk + +create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] -master_clock clk_fpga_0 [get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] + ## There is a multi-cycle path between the axi_spi_engine's SDO_FIFO and the # execution's shift register, because we load new data into the shift register # in every DATA_WIDTH's x 8 cycle. (worst case scenario) # Set a multi-cycle delay of 8 spi_clk cycle, slightly over constraining the path. -set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks clk_fpga_2] -set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks clk_fpga_2] - -set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/execution/inst/left_aligned_reg*}] -from [get_clocks clk_fpga_2] -set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/execution/inst/left_aligned_reg*}] -from [get_clocks clk_fpga_2] +set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk] +set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk] +set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/spi_pulsar_adc_execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk] +set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/spi_pulsar_adc_execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk] diff --git a/projects/ad40xx_fmc/zed/system_project.tcl b/projects/pulsar_adc/zed/system_project.tcl similarity index 79% rename from projects/ad40xx_fmc/zed/system_project.tcl rename to projects/pulsar_adc/zed/system_project.tcl index 4490beff5..ecd12d6c3 100644 --- a/projects/ad40xx_fmc/zed/system_project.tcl +++ b/projects/pulsar_adc/zed/system_project.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -15,8 +15,8 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl ## ## ADAQ4003 ## -## NOTE: Make sure that you set up your required ADC resolution and sampling rate -## in system_bd.tcl +## NOTE: Make sure that you set up your required ADC resolution in pulsar_adc_bd.tcl +## ## Please select which eval board do you want to use ## @@ -25,24 +25,22 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl ## set AD40XX_ADAQ400X_N [get_env_param AD40XX_ADAQ400X_N 1] -adi_project ad40xx_fmc_zed +adi_project pulsar_adc_pmdz_zed -if {$AD40XX_ADAQ400X_N == 1} { - adi_project_files ad40xx_fmc_zed [list \ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ - "system_top_ad40xx.v" \ - "system_constr_ad40xx.xdc" \ - "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"] -} elseif {$AD40XX_ADAQ400X_N == 0} { - adi_project_files ad40xx_fmc_zed [list \ +if {$AD40XX_ADAQ400X_N == 0} { + adi_project_files pulsar_adc_pmdz_zed [list \ "$ad_hdl_dir/library/common/ad_iobuf.v" \ "system_top_adaq400x.v" \ "system_constr_adaq400x.xdc" \ "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"] - +} elseif {$AD40XX_ADAQ400X_N == 1} { + adi_project_files pulsar_adc_pmdz_zed [list \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "system_top_ad40xx.v" \ + "system_constr_ad40xx.xdc" \ + "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"] } else { return -code error [format "ERROR: Invalid eval board type! ..."] } -adi_project_run ad40xx_fmc_zed - +adi_project_run pulsar_adc_pmdz_zed diff --git a/projects/ad40xx_fmc/zed/system_top_ad40xx.v b/projects/pulsar_adc/zed/system_top_ad40xx.v similarity index 94% rename from projects/ad40xx_fmc/zed/system_top_ad40xx.v rename to projects/pulsar_adc/zed/system_top_ad40xx.v index 1dc5aaaa1..1720bb359 100644 --- a/projects/ad40xx_fmc/zed/system_top_ad40xx.v +++ b/projects/pulsar_adc/zed/system_top_ad40xx.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -107,7 +107,7 @@ module system_top ( // instantiations - assign gpio_i[63:33] = 31'b0; + assign gpio_i[63:33] = gpio_o[63:33]; ad_iobuf #( .DATA_WIDTH(1) @@ -202,11 +202,12 @@ module system_top ( .spi1_sdi_i (1'b0), .spi1_sdo_i (1'b0), .spi1_sdo_o (), - .ad40xx_spi_sdo (ad40xx_spi_sdo), - .ad40xx_spi_sdo_t (), - .ad40xx_spi_sdi (ad40xx_spi_sdi), - .ad40xx_spi_cs (ad40xx_spi_cs), - .ad40xx_spi_sclk (ad40xx_spi_sclk), + .pulsar_adc_spi_cs(ad40xx_spi_cs), + .pulsar_adc_spi_sclk(ad40xx_spi_sclk), + .pulsar_adc_spi_sdi(ad40xx_spi_sdi), + .pulsar_adc_spi_sdo(ad40xx_spi_sdo), + .pulsar_adc_spi_sdo_t(), + .pulsar_adc_spi_three_wire(), .otg_vbusoc (otg_vbusoc), .spdif (spdif)); diff --git a/projects/ad40xx_fmc/zed/system_top_adaq400x.v b/projects/pulsar_adc/zed/system_top_adaq400x.v similarity index 94% rename from projects/ad40xx_fmc/zed/system_top_adaq400x.v rename to projects/pulsar_adc/zed/system_top_adaq400x.v index 3de3efb31..b3e69a2c2 100644 --- a/projects/ad40xx_fmc/zed/system_top_adaq400x.v +++ b/projects/pulsar_adc/zed/system_top_adaq400x.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -105,7 +105,7 @@ module system_top ( // instantiations - assign gpio_i[63:32] = 31'b0; + assign gpio_i[63:32] = gpio_o[63:32]; ad_iobuf #( .DATA_WIDTH(32) @@ -192,11 +192,12 @@ module system_top ( .spi1_sdi_i (1'b0), .spi1_sdo_i (1'b0), .spi1_sdo_o (), - .ad40xx_spi_sdo (adaq400x_spi_sdo), - .ad40xx_spi_sdo_t (), - .ad40xx_spi_sdi (adaq400x_spi_sdi), - .ad40xx_spi_cs (adaq400x_spi_cs), - .ad40xx_spi_sclk (adaq400x_spi_sclk), + .pulsar_adc_spi_cs (adaq400x_spi_cs), + .pulsar_adc_spi_sclk (adaq400x_spi_sclk), + .pulsar_adc_spi_sdi (adaq400x_spi_sdi), + .pulsar_adc_spi_sdo (adaq400x_spi_sdo), + .pulsar_adc_spi_sdo_t (), + .pulsar_adc_spi_three_wire (), .otg_vbusoc (otg_vbusoc), .spdif (spdif)); diff --git a/projects/pulsar_adc_pmdz/Makefile b/projects/pulsar_adc_pmdz/Makefile deleted file mode 100644 index 1402069e1..000000000 --- a/projects/pulsar_adc_pmdz/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -#################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. -### SPDX short identifier: BSD-1-Clause -## Auto-generated, do not modify! -#################################################################################### - -include ../scripts/project-toplevel.mk diff --git a/projects/pulsar_adc_pmdz/Readme.md b/projects/pulsar_adc_pmdz/Readme.md deleted file mode 100755 index 659d1bba7..000000000 --- a/projects/pulsar_adc_pmdz/Readme.md +++ /dev/null @@ -1,38 +0,0 @@ -# PULSAR_ADC_PMDZ HDL Project - -Here are some pointers to help you: - * [Board Product Page](https://www.analog.com/eval-ad400x-fmcz) - * Parts : [AD7942: 14-Bit, 250 kSPS PulSAR, Pseudo Differential ADC in MSOP/LFCSP](https://www.analog.com/ad7942) - * Parts : [AD7946: 14-Bit, 500 kSPS PulSAR ADC in MSOP](https://www.analog.com/ad7946) - * Parts : [AD7988-1: 16-Bit Lower Power PulSAR ADCs in MSOP/LFCSP](https://www.analog.com/ad7988-1) - * Parts : [AD7685: 16-Bit, 250 kSPS PulSAR ADC in MSOP/QFN](https://www.analog.com/ad7685) - * Parts : [AD7687: 16-Bit, 1.5 LSB INL, 250 kSPS PulSAR Differential ADC in MSOP/QFN](https://www.analog.com/ad7687) - * Parts : [AD7691: 18-Bit, 1.5 LSB INL, 250 kSPS PulSAR Differential ADC in MSOP/QFN](https://www.analog.com/ad7691) - * Parts : [AD7686: 500 kSPS 16-BIT PulSAR A/D Converter in MSOP/QFN](https://www.analog.com/ad7686) - * Parts : [AD7688: 500 kSPS 16- BIT Differential PulSAR A/D Converter in µSOIC/QFN](https://www.analog.com/ad7688) - * Parts : [AD7693: 16-Bit, ±0.5 LSB, 500 kSPS PulSAR Differential A/D Converter in MSOP/QFN](https://www.analog.com/ad7693) - * Parts : [AD7988-5: 16-Bit Lower Power PulSAR ADCs in MSOP/LFCSP](https://www.analog.com/ad7988-5) - * Parts : [AD7980: 16-Bit, 1 MSPS, PulSAR ADC in MSOP/LFCSP](https://www.analog.com/ad7980) - * Parts : [AD7983: 16-Bit, 1.33 MSPS PulSAR ADC in MSOP/LFCSP](https://www.analog.com/ad7983) - * Parts : [AD7690: 18-Bit, 1.5 LSB INL, 400 kSPS PulSAR Differential ADC in MSOP/QFN](https://www.analog.com/ad7690) - * Project Doc: https://wiki.analog.com/resources/eval/10-lead-pulsar-adc-evaluation-board - * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/pulsar_adc_pmods_hdl - * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/ad7476a - -## Supported parts - - * AD7942 - * AD7946 - * AD7988-1 - * AD7685 - * AD7687 - * AD7691 - * AD7686 - * AD7688 - * AD7693 - * AD7988-5 - * AD7980 - * AD7983 - * AD7690 - * AD7982 - * AD7984