pulsar_adc_pmdz: Port to ZedBoard
Added support for AD40xx family in the PulSAR ADC project. --------- Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>main
PIoandan
GitHub
parent
03043f732a
commit
b2dc91b30d
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@ -17,9 +17,6 @@
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# Code owners for ad3552r_evb folder
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/projects/ad3552r_evb/ paul.pop@analog.com adrian.costina@analog.com
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# Code owners for ad40xx_fmc folder
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/projects/ad40xx_fmc/ pop.ioan-daniel@analog.com paul.pop@analog.com
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# Code owners for ad4110 folder
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/projects/ad4110/ sergiu.arpadi@analog.com adrian.costina@analog.com
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@ -1,25 +0,0 @@
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# AD40XX-FMCZ HDL Project
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Here are some pointers to help you:
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* [Board Product Page](https://www.analog.com/eval-ad400x-fmcz)
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* Parts : [18-Bit, 2 MSPS/1 MSPS/500 kSPS, Easy Drive, Differential SAR ADCs](https://www.analog.com/ad4003)
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* Parts : [18-Bit, 2 MSPS/1 MSPS/500 kSPS, Easy Drive, Differential SAR ADCs](https://www.analog.com/ad4007)
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* Parts : [18-Bit, 500 kSPS, Easy Drive, Differential SAR ADCs](https://www.analog.com/ad4011)
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* Parts : [20-Bit, 1.8 MSPS/1 MSPS/500 kSPS, Easy Drive, Differential SAR ADCs](https://www.analog.com/ad4020)
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* Project Doc: https://wiki.analog.com/resources/eval/user-guides/ad400x
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* HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad400x
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* Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/ad400x
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## Supported parts
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* AD4000
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* AD4001
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* AD4002
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* AD4003
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* AD4004
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* AD4005
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* AD4006
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* AD4007
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* AD4008
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* AD4010
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* AD4011
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* AD4020
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@ -1,126 +0,0 @@
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###############################################################################
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## Copyright (C) 2019-2024 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 ad40xx_spi
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## To support the 1.8MSPS (SCLK == 100 MHz), set the spi clock to 200 MHz
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set_property -dict [list \
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CONFIG.PCW_EN_CLK2_PORT {1} \
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CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ $spi_clk_ref_frequency] [get_bd_cells sys_ps7]
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# create a SPI Engine architecture
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create_bd_cell -type hier spi_ad40xx
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current_bd_instance /spi_ad40xx
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create_bd_pin -dir I -type clk clk
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create_bd_pin -dir I -type rst resetn
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create_bd_pin -dir I -type clk spi_clk
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create_bd_pin -dir O irq
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create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 m_spi
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create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SAMPLE
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if {$ADC_RESOLUTION <= 16} {
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set data_width 16
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} else {
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set data_width 32
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};
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ad_ip_instance spi_engine_execution execution
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ad_ip_parameter execution CONFIG.DATA_WIDTH $data_width
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ad_ip_parameter execution CONFIG.NUM_OF_CS 1
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ad_ip_parameter execution CONFIG.NUM_OF_SDI 1
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ad_ip_parameter execution CONFIG.SDO_DEFAULT 1
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ad_ip_parameter execution CONFIG.SDI_DELAY 1
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ad_ip_instance axi_spi_engine axi_regmap
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ad_ip_parameter axi_regmap CONFIG.DATA_WIDTH $data_width
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ad_ip_parameter axi_regmap CONFIG.NUM_OFFLOAD 1
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ad_ip_parameter axi_regmap CONFIG.ASYNC_SPI_CLK 1
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ad_ip_instance spi_engine_offload offload
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ad_ip_parameter offload CONFIG.DATA_WIDTH $data_width
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ad_ip_parameter offload CONFIG.ASYNC_SPI_CLK 1
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ad_ip_instance spi_engine_interconnect interconnect
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ad_ip_parameter interconnect CONFIG.DATA_WIDTH $data_width
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ad_ip_instance util_pulse_gen trigger_gen
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## to setup the sample rate of the system change the PULSE_PERIOD value
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## the acutal sample rate will be PULSE_PERIOD * (1/sys_cpu_clk)
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set sampling_cycle [expr int(ceil(double($spi_clk_ref_frequency * 1000000) / $ADC_SAMPLING_RATE))]
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ad_ip_parameter trigger_gen CONFIG.PULSE_PERIOD $sampling_cycle
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ad_ip_parameter trigger_gen CONFIG.PULSE_WIDTH 1
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ad_connect axi_regmap/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl
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ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl
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ad_connect axi_regmap/spi_engine_ctrl interconnect/s1_ctrl
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ad_connect interconnect/m_ctrl execution/ctrl
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ad_connect offload/offload_sdi M_AXIS_SAMPLE
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ad_connect execution/spi m_spi
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ad_connect spi_clk offload/spi_clk
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ad_connect spi_clk offload/ctrl_clk
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ad_connect spi_clk execution/clk
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ad_connect clk axi_regmap/s_axi_aclk
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ad_connect spi_clk axi_regmap/spi_clk
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ad_connect spi_clk interconnect/clk
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ad_connect spi_clk trigger_gen/clk
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ad_connect axi_regmap/spi_resetn offload/spi_resetn
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ad_connect axi_regmap/spi_resetn execution/resetn
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ad_connect axi_regmap/spi_resetn interconnect/resetn
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ad_connect axi_regmap/spi_resetn trigger_gen/rstn
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ad_connect trigger_gen/load_config GND
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ad_connect trigger_gen/pulse_width GND
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ad_connect trigger_gen/pulse_period GND
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ad_connect trigger_gen/pulse offload/trigger
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ad_connect resetn axi_regmap/s_axi_aresetn
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ad_connect irq axi_regmap/irq
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current_bd_instance /
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# asynchronous SPI clock, to support higher SCLK
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ad_connect spi_clk sys_ps7/FCLK_CLK2
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# dma to receive data stream
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ad_ip_instance axi_dmac axi_ad40xx_dma
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ad_ip_parameter axi_ad40xx_dma CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter axi_ad40xx_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_ad40xx_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_ad40xx_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_ad40xx_dma CONFIG.AXI_SLICE_SRC 1
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ad_ip_parameter axi_ad40xx_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_ad40xx_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_ad40xx_dma CONFIG.DMA_DATA_WIDTH_SRC $data_width
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ad_ip_parameter axi_ad40xx_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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ad_connect sys_cpu_clk spi_ad40xx/clk
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ad_connect spi_clk axi_ad40xx_dma/s_axis_aclk
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ad_connect sys_cpu_resetn spi_ad40xx/resetn
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ad_connect sys_cpu_resetn axi_ad40xx_dma/m_dest_axi_aresetn
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ad_connect spi_clk spi_ad40xx/spi_clk
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ad_connect spi_ad40xx/m_spi ad40xx_spi
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ad_connect axi_ad40xx_dma/s_axis spi_ad40xx/M_AXIS_SAMPLE
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ad_cpu_interconnect 0x44a00000 spi_ad40xx/axi_regmap
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ad_cpu_interconnect 0x44a30000 axi_ad40xx_dma
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ad_cpu_interrupt "ps-13" "mb-13" axi_ad40xx_dma/irq
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ad_cpu_interrupt "ps-12" "mb-12" /spi_ad40xx/irq
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ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect sys_cpu_clk axi_ad40xx_dma/m_dest_axi
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@ -1,34 +0,0 @@
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###############################################################################
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## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
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source $ad_hdl_dir/projects/scripts/adi_pd.tcl
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# specify the spi reference clock frequency in MHz
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set spi_clk_ref_frequency 166
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# specify ADC resolution -- supported resolutions 16/18/20 bits
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set ADC_RESOLUTION [get_env_param ADC_RESOLUTION 20]
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# specify ADC sampling rate in samples/seconds
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# NOTE: This rate can be set just in turbo mode -- if turbo mode is not used
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# the max rate should be 1.6 MSPS
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# supported sampling rates: 2/1.8/1/0.5 MSPS depending on the board
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set ADC_SAMPLING_RATE [get_env_param ADC_SAMPLING_RATE 1800000]
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source ../common/ad40xx_bd.tcl
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set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt;
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#system ID
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ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
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ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path"
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ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
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set AD40XX_ADAQ400X_N [get_env_param AD40XX_ADAQ400X_N 1]
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set sys_cstring "ad40xx: $AD40XX_ADAQ400X_N - adc_sampling_rate: $ADC_SAMPLING_RATE - adc_resolution: $ADC_RESOLUTION"
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sysid_gen_sys_init_file $sys_cstring
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@ -1,5 +1,5 @@
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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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## Copyright (c) 2018 - 2024 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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@ -0,0 +1,68 @@
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# PULSAR_ADC HDL Project
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Here are some pointers to help you:
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* [Board Product Page](https://www.analog.com/eval-ad400x-fmcz)
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* Parts : [AD7942: 14-Bit, 250 kSPS PulSAR, Pseudo Differential ADC in MSOP/LFCSP](https://www.analog.com/ad7942)
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* Parts : [AD7946: 14-Bit, 500 kSPS PulSAR ADC in MSOP](https://www.analog.com/ad7946)
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* Parts : [AD7988-1: 16-Bit Lower Power PulSAR ADCs in MSOP/LFCSP](https://www.analog.com/ad7988-1)
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* Parts : [AD7685: 16-Bit, 250 kSPS PulSAR ADC in MSOP/QFN](https://www.analog.com/ad7685)
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* Parts : [AD7687: 16-Bit, 1.5 LSB INL, 250 kSPS PulSAR Differential ADC in MSOP/QFN](https://www.analog.com/ad7687)
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* Parts : [AD7691: 18-Bit, 1.5 LSB INL, 250 kSPS PulSAR Differential ADC in MSOP/QFN](https://www.analog.com/ad7691)
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* Parts : [AD7686: 500 kSPS 16-BIT PulSAR A/D Converter in MSOP/QFN](https://www.analog.com/ad7686)
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* Parts : [AD7688: 500 kSPS 16- BIT Differential PulSAR A/D Converter in µSOIC/QFN](https://www.analog.com/ad7688)
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* Parts : [AD7693: 16-Bit, ±0.5 LSB, 500 kSPS PulSAR Differential A/D Converter in MSOP/QFN](https://www.analog.com/ad7693)
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* Parts : [AD7988-5: 16-Bit Lower Power PulSAR ADCs in MSOP/LFCSP](https://www.analog.com/ad7988-5)
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* Parts : [AD7980: 16-Bit, 1 MSPS, PulSAR ADC in MSOP/LFCSP](https://www.analog.com/ad7980)
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* Parts : [AD7983: 16-Bit, 1.33 MSPS PulSAR ADC in MSOP/LFCSP](https://www.analog.com/ad7983)
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* Parts : [AD7690: 18-Bit, 1.5 LSB INL, 400 kSPS PulSAR Differential ADC in MSOP/QFN](https://www.analog.com/ad7690)
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* Parts : [AD7689: 16-Bit, 8-Channel, 250 kSPS PulSAR ADC](https://www.analog.com/ad7689)
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* Parts : [AD4000: 16-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs](https://www.analog.com/ad4000)
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* Parts : [AD4001: 16-Bit, 2 MSPS/1 MSPS, Precision, Differential SAR ADCs](https://www.analog.com/ad4001)
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* Parts : [AD4002: 18-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs](https://www.analog.com/ad4002)
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* Parts : [AD4003: 18-Bit, 2 MSPS/1 MSPS/500 kSPS, Easy Drive, Differential SAR ADCs](https://www.analog.com/ad4003)
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* Parts : [AD4004: 16-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs](https://www.analog.com/ad4004)
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* Parts : [AD4005: 16-Bit, 2 MSPS/1 MSPS, Precision, Differential SAR ADCs](https://www.analog.com/ad4005)
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* Parts : [AD4006: 18-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs](https://www.analog.com/ad4006)
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* Parts : [AD4007: 18-Bit, 2 MSPS/1 MSPS/500 kSPS, Easy Drive, Differential SAR ADCs](https://www.analog.com/ad4007)
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* Parts : [AD4008: 16-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs](https://www.analog.com/ad4008)
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* Parts : [AD4010: 18-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs](https://www.analog.com/ad4010)
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* Parts : [AD4011: 18-Bit, 2 MSPS/1 MSPS/500 kSPS, Easy Drive, Differential SAR ADCs](https://www.analog.com/ad4011)
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* Parts : [ADAQ4003: 18-Bit, 2 MSPS, Precision DAQ, Differential SAR ADCs](https://www.analog.com/adaq4003)
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* Parts : [AD4020: 20-Bit, 1.8 MSPS/1 MSPS/500 kSPS, Easy Drive, Differential SAR ADCs](https://www.analog.com/ad4020)
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* Project Doc: https://wiki.analog.com/resources/eval/10-lead-pulsar-adc-evaluation-board
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* HDL Doc: https://wiki.analog.com/resources/eval/user-guides/pulsar_adc_pmods_hdl
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* Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/ad7476a
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## Supported parts
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* AD7942
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* AD7946
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* AD7988-1
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* AD7685
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* AD7687
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* AD7691
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* AD7686
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* AD7688
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* AD7693
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* AD7988-5
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* AD7980
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* AD7983
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* AD7690
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* AD7982
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* AD7984
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* AD7682
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* AD7689
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* AD4000
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* AD4001
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* AD4002
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* AD4003
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* AD4004
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* AD4005
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* AD4006
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* AD4007
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* AD4008
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* AD4010
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* AD4011
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* ADAQ4003
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* AD4020
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FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination
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# ad40xx
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H7 FMC_LA02_P SDI_FMC ad40xx_spi_sdo LVCMOS25 IOB TRUE
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D8 FMC_LA01_CC_P SDO_FMC ad40xx_spi_sdi LVCMOS25 IOB TRUE
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G6 FMC_LA00_CC_P SCK_FMC ad40xx_spi_sclk LVCMOS25 IOB TRUE
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G7 FMC_LA00_CC_N CNV_FMC ad40xx_spi_cs LVCMOS25 IOB TRUE
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G10 FMC_LA03_N AMP_PD ad40xx_amp_pd LVCMOS25 IOB TRUE
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Pin Port Schematic_name System_top_name IOSTANDARD Termination
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# adaq400x
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2 PMOD_2 SDI adaq400x_spi_sdo LVCMOS33 #N/A
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3 PMOD_3 SDO adaq400x_spi_sdi LVCMOS33 #N/A
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4 PMOD_4 SCK adaq400x_spi_sclk LVCMOS33 #N/A
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1 PMOD_1 CNV adaq400x_spi_cs LVCMOS33 #N/A
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@ -6,6 +6,7 @@
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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 pulsar_adc_spi
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source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
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# If the ADC resolution <= 16, data_width is set 16 else 32
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set data_width 32
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set async_spi_clk 1
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set num_cs 1
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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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## Copyright (c) 2018 - 2024 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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PROJECT_NAME := pulsar_adc_pmdz_coraz7s
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M_DEPS += ../common/pulsar_adc_pmdz_bd.tcl
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M_DEPS += ../common/pulsar_adc_bd.tcl
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M_DEPS += ../../scripts/adi_pd.tcl
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M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl
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M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc
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###############################################################################
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## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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## Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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source $ad_hdl_dir/projects/common/coraz7s/coraz7s_system_bd.tcl
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source $ad_hdl_dir/projects/scripts/adi_pd.tcl
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source ../common/pulsar_adc_pmdz_bd.tcl
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source ../common/pulsar_adc_bd.tcl
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set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt;
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###############################################################################
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## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
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## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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@ -1,5 +1,5 @@
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###############################################################################
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## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
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## Copyright (C) 2016-2024 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
|
||||
// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
|
|
@ -1,23 +1,25 @@
|
|||
####################################################################################
|
||||
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
|
||||
## Copyright (c) 2018 - 2024 Analog Devices, Inc.
|
||||
### SPDX short identifier: BSD-1-Clause
|
||||
## Auto-generated, do not modify!
|
||||
####################################################################################
|
||||
|
||||
PROJECT_NAME := ad40xx_fmc_zed
|
||||
PROJECT_NAME := pulsar_adc_pmdz_zed
|
||||
|
||||
M_DEPS += system_constr_adaq400x.xdc
|
||||
M_DEPS += system_constr_ad40xx.xdc
|
||||
M_DEPS += ../common/ad40xx_bd.tcl
|
||||
M_DEPS += ../common/pulsar_adc_bd.tcl
|
||||
M_DEPS += ../../scripts/adi_pd.tcl
|
||||
M_DEPS += ../../common/zed/zed_system_constr.xdc
|
||||
M_DEPS += ../../common/zed/zed_system_bd.tcl
|
||||
M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl
|
||||
M_DEPS += ../../../library/common/ad_iobuf.v
|
||||
|
||||
LIB_DEPS += axi_clkgen
|
||||
LIB_DEPS += axi_dmac
|
||||
LIB_DEPS += axi_hdmi_tx
|
||||
LIB_DEPS += axi_i2s_adi
|
||||
LIB_DEPS += axi_pwm_gen
|
||||
LIB_DEPS += axi_spdif_tx
|
||||
LIB_DEPS += axi_sysid
|
||||
LIB_DEPS += spi_engine/axi_spi_engine
|
||||
|
|
@ -26,6 +28,5 @@ LIB_DEPS += spi_engine/spi_engine_interconnect
|
|||
LIB_DEPS += spi_engine/spi_engine_offload
|
||||
LIB_DEPS += sysid_rom
|
||||
LIB_DEPS += util_i2c_mixer
|
||||
LIB_DEPS += util_pulse_gen
|
||||
|
||||
include ../../scripts/project-xilinx.mk
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
###############################################################################
|
||||
## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
|
||||
|
||||
source ../common/pulsar_adc_bd.tcl
|
||||
|
||||
#system ID
|
||||
|
||||
set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt;
|
||||
|
||||
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
|
||||
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path"
|
||||
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
|
||||
|
||||
set AD40XX_ADAQ400X_N [get_env_param AD40XX_ADAQ400X_N 1]
|
||||
set sys_cstring "ad40xx: $AD40XX_ADAQ400X_N"
|
||||
sysid_gen_sys_init_file $sys_cstring
|
||||
|
|
@ -1,25 +1,28 @@
|
|||
###############################################################################
|
||||
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
|
||||
## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
# ad40xx_fmc SPI interface
|
||||
|
||||
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad40xx_spi_sdo] ; ## H07 FMC_LPC_LA02_P
|
||||
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad40xx_spi_sdi] ; ## D08 FMC_LPC_LA01_CC_P
|
||||
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad40xx_spi_sclk] ; ## G06 FMC_LPC_LA00_CC_P
|
||||
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad40xx_spi_cs] ; ## G07 FMC_LPC_LA00_CC_N
|
||||
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad40xx_spi_sdo] ; ## H7 FMC_LA02_P IO_L20P_T3_34
|
||||
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad40xx_spi_sdi] ; ## D8 FMC_LA01_CC_P IO_L14P_T2_SRCC_34
|
||||
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad40xx_spi_sclk] ; ## G6 FMC_LA00_CC_P IO_L13P_T2_MRCC_34
|
||||
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad40xx_spi_cs] ; ## G7 FMC_LA00_CC_N IO_L13N_T2_MRCC_34
|
||||
|
||||
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports ad40xx_amp_pd] ; ## G10 FMC_LPC_LA03_N
|
||||
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports ad40xx_amp_pd] ; ## G10 FMC_LA03_N IO_L16N_T2_34
|
||||
|
||||
# NOTE: clk_fpga_0 is the first PL fabric clock, also called $sys_cpu_clk
|
||||
|
||||
create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] -master_clock clk_fpga_0 [get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]]
|
||||
|
||||
## There is a multi-cycle path between the axi_spi_engine's SDO_FIFO and the
|
||||
# execution's shift register, because we load new data into the shift register
|
||||
# in every DATA_WIDTH's x 8 cycle. (worst case scenario)
|
||||
# Set a multi-cycle delay of 8 spi_clk cycle, slightly over constraining the path.
|
||||
|
||||
set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks clk_fpga_2]
|
||||
set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks clk_fpga_2]
|
||||
|
||||
set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/execution/inst/left_aligned_reg*}] -from [get_clocks clk_fpga_2]
|
||||
set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/execution/inst/left_aligned_reg*}] -from [get_clocks clk_fpga_2]
|
||||
set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk]
|
||||
set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk]
|
||||
|
||||
set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/spi_pulsar_adc_execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk]
|
||||
set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/spi_pulsar_adc_execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk]
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
###############################################################################
|
||||
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
|
||||
## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
|
|
@ -10,14 +10,17 @@ set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS33} [get_ports adaq400x_sp
|
|||
set_property -dict {PACKAGE_PIN AA9 IOSTANDARD LVCMOS33} [get_ports adaq400x_spi_sclk] ; ## JA4
|
||||
set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_ports adaq400x_spi_cs] ; ## JA1
|
||||
|
||||
# NOTE: clk_fpga_0 is the first PL fabric clock, also called $sys_cpu_clk
|
||||
|
||||
create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] -master_clock clk_fpga_0 [get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]]
|
||||
|
||||
## There is a multi-cycle path between the axi_spi_engine's SDO_FIFO and the
|
||||
# execution's shift register, because we load new data into the shift register
|
||||
# in every DATA_WIDTH's x 8 cycle. (worst case scenario)
|
||||
# Set a multi-cycle delay of 8 spi_clk cycle, slightly over constraining the path.
|
||||
|
||||
set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks clk_fpga_2]
|
||||
set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks clk_fpga_2]
|
||||
|
||||
set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/execution/inst/left_aligned_reg*}] -from [get_clocks clk_fpga_2]
|
||||
set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/execution/inst/left_aligned_reg*}] -from [get_clocks clk_fpga_2]
|
||||
set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk]
|
||||
set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk]
|
||||
|
||||
set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/spi_pulsar_adc_execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk]
|
||||
set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/spi_pulsar_adc_execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk]
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
###############################################################################
|
||||
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
|
||||
## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
|
|
@ -15,8 +15,8 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
|
|||
##
|
||||
## ADAQ4003
|
||||
##
|
||||
## NOTE: Make sure that you set up your required ADC resolution and sampling rate
|
||||
## in system_bd.tcl
|
||||
## NOTE: Make sure that you set up your required ADC resolution in pulsar_adc_bd.tcl
|
||||
##
|
||||
|
||||
## Please select which eval board do you want to use
|
||||
##
|
||||
|
|
@ -25,24 +25,22 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
|
|||
##
|
||||
set AD40XX_ADAQ400X_N [get_env_param AD40XX_ADAQ400X_N 1]
|
||||
|
||||
adi_project ad40xx_fmc_zed
|
||||
adi_project pulsar_adc_pmdz_zed
|
||||
|
||||
if {$AD40XX_ADAQ400X_N == 1} {
|
||||
adi_project_files ad40xx_fmc_zed [list \
|
||||
"$ad_hdl_dir/library/common/ad_iobuf.v" \
|
||||
"system_top_ad40xx.v" \
|
||||
"system_constr_ad40xx.xdc" \
|
||||
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
|
||||
} elseif {$AD40XX_ADAQ400X_N == 0} {
|
||||
adi_project_files ad40xx_fmc_zed [list \
|
||||
if {$AD40XX_ADAQ400X_N == 0} {
|
||||
adi_project_files pulsar_adc_pmdz_zed [list \
|
||||
"$ad_hdl_dir/library/common/ad_iobuf.v" \
|
||||
"system_top_adaq400x.v" \
|
||||
"system_constr_adaq400x.xdc" \
|
||||
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
|
||||
|
||||
} elseif {$AD40XX_ADAQ400X_N == 1} {
|
||||
adi_project_files pulsar_adc_pmdz_zed [list \
|
||||
"$ad_hdl_dir/library/common/ad_iobuf.v" \
|
||||
"system_top_ad40xx.v" \
|
||||
"system_constr_ad40xx.xdc" \
|
||||
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
|
||||
} else {
|
||||
return -code error [format "ERROR: Invalid eval board type! ..."]
|
||||
}
|
||||
|
||||
adi_project_run ad40xx_fmc_zed
|
||||
|
||||
adi_project_run pulsar_adc_pmdz_zed
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
|
||||
// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
|
|
@ -107,7 +107,7 @@ module system_top (
|
|||
|
||||
// instantiations
|
||||
|
||||
assign gpio_i[63:33] = 31'b0;
|
||||
assign gpio_i[63:33] = gpio_o[63:33];
|
||||
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(1)
|
||||
|
|
@ -202,11 +202,12 @@ module system_top (
|
|||
.spi1_sdi_i (1'b0),
|
||||
.spi1_sdo_i (1'b0),
|
||||
.spi1_sdo_o (),
|
||||
.ad40xx_spi_sdo (ad40xx_spi_sdo),
|
||||
.ad40xx_spi_sdo_t (),
|
||||
.ad40xx_spi_sdi (ad40xx_spi_sdi),
|
||||
.ad40xx_spi_cs (ad40xx_spi_cs),
|
||||
.ad40xx_spi_sclk (ad40xx_spi_sclk),
|
||||
.pulsar_adc_spi_cs(ad40xx_spi_cs),
|
||||
.pulsar_adc_spi_sclk(ad40xx_spi_sclk),
|
||||
.pulsar_adc_spi_sdi(ad40xx_spi_sdi),
|
||||
.pulsar_adc_spi_sdo(ad40xx_spi_sdo),
|
||||
.pulsar_adc_spi_sdo_t(),
|
||||
.pulsar_adc_spi_three_wire(),
|
||||
.otg_vbusoc (otg_vbusoc),
|
||||
.spdif (spdif));
|
||||
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||
// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
|
|
@ -105,7 +105,7 @@ module system_top (
|
|||
|
||||
// instantiations
|
||||
|
||||
assign gpio_i[63:32] = 31'b0;
|
||||
assign gpio_i[63:32] = gpio_o[63:32];
|
||||
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(32)
|
||||
|
|
@ -192,11 +192,12 @@ module system_top (
|
|||
.spi1_sdi_i (1'b0),
|
||||
.spi1_sdo_i (1'b0),
|
||||
.spi1_sdo_o (),
|
||||
.ad40xx_spi_sdo (adaq400x_spi_sdo),
|
||||
.ad40xx_spi_sdo_t (),
|
||||
.ad40xx_spi_sdi (adaq400x_spi_sdi),
|
||||
.ad40xx_spi_cs (adaq400x_spi_cs),
|
||||
.ad40xx_spi_sclk (adaq400x_spi_sclk),
|
||||
.pulsar_adc_spi_cs (adaq400x_spi_cs),
|
||||
.pulsar_adc_spi_sclk (adaq400x_spi_sclk),
|
||||
.pulsar_adc_spi_sdi (adaq400x_spi_sdi),
|
||||
.pulsar_adc_spi_sdo (adaq400x_spi_sdo),
|
||||
.pulsar_adc_spi_sdo_t (),
|
||||
.pulsar_adc_spi_three_wire (),
|
||||
.otg_vbusoc (otg_vbusoc),
|
||||
.spdif (spdif));
|
||||
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
####################################################################################
|
||||
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
|
||||
### SPDX short identifier: BSD-1-Clause
|
||||
## Auto-generated, do not modify!
|
||||
####################################################################################
|
||||
|
||||
include ../scripts/project-toplevel.mk
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
# PULSAR_ADC_PMDZ HDL Project
|
||||
|
||||
Here are some pointers to help you:
|
||||
* [Board Product Page](https://www.analog.com/eval-ad400x-fmcz)
|
||||
* Parts : [AD7942: 14-Bit, 250 kSPS PulSAR, Pseudo Differential ADC in MSOP/LFCSP](https://www.analog.com/ad7942)
|
||||
* Parts : [AD7946: 14-Bit, 500 kSPS PulSAR ADC in MSOP](https://www.analog.com/ad7946)
|
||||
* Parts : [AD7988-1: 16-Bit Lower Power PulSAR ADCs in MSOP/LFCSP](https://www.analog.com/ad7988-1)
|
||||
* Parts : [AD7685: 16-Bit, 250 kSPS PulSAR ADC in MSOP/QFN](https://www.analog.com/ad7685)
|
||||
* Parts : [AD7687: 16-Bit, 1.5 LSB INL, 250 kSPS PulSAR Differential ADC in MSOP/QFN](https://www.analog.com/ad7687)
|
||||
* Parts : [AD7691: 18-Bit, 1.5 LSB INL, 250 kSPS PulSAR Differential ADC in MSOP/QFN](https://www.analog.com/ad7691)
|
||||
* Parts : [AD7686: 500 kSPS 16-BIT PulSAR A/D Converter in MSOP/QFN](https://www.analog.com/ad7686)
|
||||
* Parts : [AD7688: 500 kSPS 16- BIT Differential PulSAR A/D Converter in µSOIC/QFN](https://www.analog.com/ad7688)
|
||||
* Parts : [AD7693: 16-Bit, ±0.5 LSB, 500 kSPS PulSAR Differential A/D Converter in MSOP/QFN](https://www.analog.com/ad7693)
|
||||
* Parts : [AD7988-5: 16-Bit Lower Power PulSAR ADCs in MSOP/LFCSP](https://www.analog.com/ad7988-5)
|
||||
* Parts : [AD7980: 16-Bit, 1 MSPS, PulSAR ADC in MSOP/LFCSP](https://www.analog.com/ad7980)
|
||||
* Parts : [AD7983: 16-Bit, 1.33 MSPS PulSAR ADC in MSOP/LFCSP](https://www.analog.com/ad7983)
|
||||
* Parts : [AD7690: 18-Bit, 1.5 LSB INL, 400 kSPS PulSAR Differential ADC in MSOP/QFN](https://www.analog.com/ad7690)
|
||||
* Project Doc: https://wiki.analog.com/resources/eval/10-lead-pulsar-adc-evaluation-board
|
||||
* HDL Doc: https://wiki.analog.com/resources/eval/user-guides/pulsar_adc_pmods_hdl
|
||||
* Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/ad7476a
|
||||
|
||||
## Supported parts
|
||||
|
||||
* AD7942
|
||||
* AD7946
|
||||
* AD7988-1
|
||||
* AD7685
|
||||
* AD7687
|
||||
* AD7691
|
||||
* AD7686
|
||||
* AD7688
|
||||
* AD7693
|
||||
* AD7988-5
|
||||
* AD7980
|
||||
* AD7983
|
||||
* AD7690
|
||||
* AD7982
|
||||
* AD7984
|
||||
Loading…
Reference in New Issue