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daq2/a10gx-- xcvr+base changes

main
Rejeesh Kutty 2015-07-21 11:01:45 -04:00
parent 86dabbe5fc
commit b3102b5095
4 changed files with 11 additions and 23 deletions
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8
projects/daq2/a10gx/system_bd.qsys
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@ -289,6 +289,14 @@
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="FIFO" />

11
projects/daq2/a10gx/system_constr.sdc
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@ -1,19 +1,10 @@
create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
create_clock -period "4.286 ns" -name ddr3_ref_clk_233mhz [get_ports {ddr3_ref_clk}]
create_clock -period "7.500 ns" -name ddr3_ref_clk_133mhz [get_ports {ddr3_ref_clk}]
create_clock -period "8.000 ns" -name eth_ref_clk_125mhz [get_ports {eth_ref_clk}]
create_clock -period "2.000 ns" -name rx_ref_clk_500mhz [get_ports {rx_ref_clk}]
create_clock -period "2.000 ns" -name tx_ref_clk_500mhz [get_ports {tx_ref_clk}]
derive_pll_clocks
create_generated_clock -source {i_system_bd|daq2|axi_jesd_xcvr|i_sys_xcvr|i_rx_pll|iopll_0|altera_pll_i|general[0].gpll~IOPLL|refclk[0]} \
-divide_by 8 -multiply_by 4 -duty_cycle 50.00 -name {i_system_bd|daq2|axi_jesd_xcvr|rx_clk} \
{i_system_bd|daq2|axi_jesd_xcvr|i_sys_xcvr|i_rx_pll|iopll_0|altera_pll_i|general[0].gpll~IOPLL|outclk[0]}
create_generated_clock -source {i_system_bd|daq2|axi_jesd_xcvr|i_sys_xcvr|i_tx_pll|iopll_0|altera_pll_i|general[0].gpll~IOPLL|refclk[0]} \
-divide_by 8 -multiply_by 4 -duty_cycle 50.00 -name {i_system_bd|daq2|axi_jesd_xcvr|tx_clk} \
{i_system_bd|daq2|axi_jesd_xcvr|i_sys_xcvr|i_tx_pll|iopll_0|altera_pll_i|general[0].gpll~IOPLL|outclk[0]}
derive_clock_uncertainty

11
projects/daq2/a10gx/system_project.tcl
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@ -7,21 +7,10 @@ project_new daq2_a10gx -overwrite
source $ad_hdl_dir/projects/common/a10gx/a10gx_system_assign.tcl
file copy -force $ad_hdl_dir/projects/common/a10gx/a10gx_system_bd.qsys .
file copy -force $ad_hdl_dir/projects/daq2/common/daq2_bd.qsys .
#set_global_assignment -name QSYS_FILE a10gx_system_bd.qsys
#set_global_assignment -name QSYS_FILE daq2_bd.qsys
set_global_assignment -name QSYS_FILE sys_xcvr_tx_lane_pll.qsys
set_global_assignment -name QSYS_FILE sys_xcvr_core.qsys
set_global_assignment -name QSYS_FILE sys_xcvr_rstcntrl.qsys
set_global_assignment -name QSYS_FILE sys_xcvr_rx_pll.qsys
set_global_assignment -name QSYS_FILE sys_xcvr_tx_pll.qsys
set_global_assignment -name QSYS_FILE sys_xcvr_rx_ip.qsys
set_global_assignment -name QSYS_FILE sys_xcvr_tx_ip.qsys
set_global_assignment -name QSYS_FILE system_bd.qsys
set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/ad_iobuf.v
set_global_assignment -name VERILOG_FILE ../common/daq2_spi.v
set_global_assignment -name VERILOG_FILE ../common/sys_xcvr.v
set_global_assignment -name VERILOG_FILE system_top.v
set_global_assignment -name SDC_FILE system_constr.sdc

4
projects/daq2/a10gx/system_top.v
View File

@ -273,11 +273,11 @@ module system_top (
.a10gx_base_sys_spi_MOSI (spi_mosi_s),
.a10gx_base_sys_spi_SCLK (spi_clk),
.a10gx_base_sys_spi_SS_n (spi_csn_s),
.daq2_rx_data_rx_d (rx_data),
.daq2_rx_data_rx_serial_data (rx_data),
.daq2_rx_ref_clk_clk (rx_ref_clk),
.daq2_rx_sync_rx_sync (rx_sync),
.daq2_rx_sysref_rx_ext_sysref_in (rx_sysref),
.daq2_tx_data_tx_d (tx_data),
.daq2_tx_data_tx_serial_data (tx_data),
.daq2_tx_ref_clk_clk (tx_ref_clk),
.daq2_tx_sync_tx_sync (tx_sync),
.daq2_tx_sysref_tx_ext_sysref_in (tx_sysref),