diff --git a/projects/common/a10soc/a10soc_system_assign.tcl b/projects/common/a10soc/a10soc_system_assign.tcl
index 8182175fd..34474b390 100755
--- a/projects/common/a10soc/a10soc_system_assign.tcl
+++ b/projects/common/a10soc/a10soc_system_assign.tcl
@@ -3,8 +3,12 @@
 
 set_global_assignment -name FAMILY "Arria 10"
 set_global_assignment -name DEVICE 10AS066N3F40E2SGE2
+
+# ignored warnings and such
+
 set_global_assignment -name MESSAGE_DISABLE 17951 ; ## disable unused RX channels message
 set_global_assignment -name MESSAGE_DISABLE 18655 ; ## disable unused TX channels message
+set_global_assignment -name SOURCE_FILE $ad_hdl_dir/projects/common/altera/messages.srf
 
 # clocks and resets
 
diff --git a/projects/common/altera/messages.srf b/projects/common/altera/messages.srf
new file mode 100644
index 000000000..d0dd20c4d
--- /dev/null
+++ b/projects/common/altera/messages.srf
@@ -0,0 +1 @@
+{ "" "" "" "Timing analysis was performed using a non-final timing model and/or constraints. You must regenerate the external memory interface IP and recheck timing closure in a future version of Quartus Prime." {  } {  } 0 0 "" 0 0 "Design Software" 0 -1 0 ""}