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altera- ignore preliminary timing messages

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Rejeesh Kutty 2017-03-20 12:48:43 -04:00
parent 7dfa8c599f
commit b39fecadd9
2 changed files with 5 additions and 0 deletions
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4
projects/common/a10soc/a10soc_system_assign.tcl
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@ -3,8 +3,12 @@
set_global_assignment -name FAMILY "Arria 10"
set_global_assignment -name DEVICE 10AS066N3F40E2SGE2
# ignored warnings and such
set_global_assignment -name MESSAGE_DISABLE 17951 ; ## disable unused RX channels message
set_global_assignment -name MESSAGE_DISABLE 18655 ; ## disable unused TX channels message
set_global_assignment -name SOURCE_FILE $ad_hdl_dir/projects/common/altera/messages.srf
# clocks and resets

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projects/common/altera/messages.srf Normal file
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@ -0,0 +1 @@
{ "" "" "" "Timing analysis was performed using a non-final timing model and/or constraints. You must regenerate the external memory interface IP and recheck timing closure in a future version of Quartus Prime." { } { } 0 0 "" 0 0 "Design Software" 0 -1 0 ""}