docs: Include the DMA SG documentation
Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>main
Ionut Podgoreanu
podgori
parent
2687bbc02e
commit
b3c58abcdc
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@ -68,9 +82,9 @@
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<text x="126.37469" y="123.3473" style="line-height:125%" xml:space="preserve"><tspan x="126.37469" y="123.3473" stroke-width=".26458px">Register Map</tspan></text>
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<text x="119.46967" y="135.42929" style="line-height:125%" xml:space="preserve"><tspan x="119.46967" y="135.42929" stroke-width=".26458px">S_AXI</tspan></text>
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<text x="144.32582" y="137.99905" style="line-height:125%" xml:space="preserve"><tspan x="144.32582" y="137.99905" stroke-width=".26458px">irq</tspan></text>
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<text x="156.62027" y="89.125519" fill="#000000" font-family="'Liberation Sans'" font-size="2.6458px" letter-spacing="0px" stroke-width=".26458px" word-spacing="0px" style="line-height:125%" xml:space="preserve"><tspan x="156.62027" y="89.125519">AXI-MM /</tspan><tspan x="156.62027" y="92.432816">AXI-Streaming /</tspan><tspan x="156.62027" y="95.74012">FIFO</tspan></text>
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@ -121,5 +137,12 @@
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Before Width: | Height: | Size: 12 KiB After Width: | Height: | Size: 14 KiB |
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@ -25,6 +25,7 @@ Features
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- Cyclic transfers
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- 2D transfers
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- Scatter-Gather transfers
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Utilization
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--------------------------------------------------------------------------------
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@ -78,21 +79,31 @@ Configuration Parameters
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- Data path width of the source interface in bits.
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* - DMA_DATA_WIDTH_DEST
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- Data path width of the destination interface in bits.
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* - DMA_DATA_WIDTH_SG
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- Data path width of the scatter-gather interface in bits.
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* - DMA_LENGTH_WIDTH
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- Width of transfer length control register in bits.
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Limits length of the transfers to 2*\*\ ``DMA_LENGTH_WIDTH``.
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* - DMA_2D_TRANSFER
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- Enable support for 2D transfers.
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* - DMA_SG_TRANSFER
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- Enable support for scatter-gather transfers.
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* - ASYNC_CLK_REQ_SRC
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- Whether the request and source clock domains are asynchronous.
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* - ASYNC_CLK_SRC_DEST
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- Whether the source and destination clock domains are asynchronous.
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* - ASYNC_CLK_DEST_REQ
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- Whether the destination and request clock domains are asynchronous.
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* - ASYNC_CLK_REQ_SG
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- Whether the request and scatter-gather clock domains are asynchronous.
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* - ASYNC_CLK_SRC_SG
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- Whether the source and scatter-gather clock domains are asynchronous.
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* - ASYNC_CLK_DEST_SG
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- Whether the destination and scatter-gather clock domains are asynchronous.
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* - AXI_SLICE_DEST
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- Whether to insert a extra register slice on the source data path.
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- Whether to insert an extra register slice on the source data path.
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* - AXI_SLICE_SRC
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- Whether to insert a extra register slice on the destination data path.
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- Whether to insert an extra register slice on the destination data path.
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* - SYNC_TRANSFER_START
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- Enable the transfer start synchronization feature.
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* - CYCLIC
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@ -100,7 +111,9 @@ Configuration Parameters
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* - DMA_AXI_PROTOCOL_SRC
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- AXI protocol version of the source interface (0 = AXI4, 1 = AXI3).
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* - DMA_AXI_PROTOCOL_DEST
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- AXI protocol version of the destionation interface (0 = AXI4, 1 = AXI3).
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- AXI protocol version of the destination interface (0 = AXI4, 1 = AXI3).
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* - DMA_AXI_PROTOCOL_SG
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- AXI protocol version of the scatter-gather interface (0 = AXI4, 1 = AXI3).
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* - DMA_TYPE_SRC
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- Interface type for the source interface
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(0 = AXI-MM, 1 = AXI-Streaming, 2 = ADI-FIFO).
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@ -149,7 +162,7 @@ Interface
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- Reset for the ``m_src_axi`` interface.
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Only present when ``DMA_TYPE_SRC`` parameter is set to AXI-MM (0).
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* - m_src_axi
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-
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- Only present when ``DMA_TYPE_SRC`` parameter is set to AXI-MM (0).
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* - m_dest_axi_aclk
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- The ``m_src_axi`` interface is synchronous to this clock.
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Only present when ``DMA_TYPE_DEST`` parameter is set to AXI-MM (0).
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@ -157,7 +170,15 @@ Interface
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- Reset for the ``m_dest_axi`` interface.
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Only present when ``DMA_TYPE_DEST`` parameter is set to AXI-MM (0).
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* - m_dest_axi
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-
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- Only present when ``DMA_TYPE_DEST`` parameter is set to AXI-MM (0).
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* - m_sg_axi_aclk
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- The ``m_sg_axi`` interface is synchronous to this clock.
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Only present when ``DMA_SG_TRANSFER`` parameter is set.
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* - m_sg_axi_aresetn
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- Reset for the ``m_sg_axi`` interface.
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Only present when ``DMA_SG_TRANSFER`` parameter is set.
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* - m_sg_axi
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- Only present when ``DMA_SG_TRANSFER`` parameter is set.
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* - s_axis_aclk
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- The ``s_axis`` interface is synchronous to this clock.
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Only present when ``DMA_TYPE_SRC`` parameter is set to AXI-Streaming
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@ -539,6 +560,101 @@ cyclic transfer the DMA channel must be disabled.
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Any additional transfers that are submitted after the submission of a cyclic
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transfer (and before stopping the cyclic transfer) will never be executed.
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Scatter-Gather Transfers
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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If the ``DMA_SG_TRANSFER`` HDL synthesis configuration parameter is set the DMA
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controller has support for scatter-gather transfers.
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The scatter-gather optional feature allows the DMA to access noncontiguous areas
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of memory within a single transfer.
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The DMA can read from or write to different memory addresses in one transaction
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by using a list of vectors called *descriptors*. Each descriptor provides the
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starting address and the length of the current memory block to be accessed, as
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well as the next address of the following descriptor to be processed. By chaining
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these descriptors, the DMA can *gather* the data into a contiguous transfer from
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the *scattered* memory data from multiple addresses.
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The scatter-gather has its own dedicated AXI3/4 memory mapped interface
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``m_sg_axi`` through which it receives the descriptor data.
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Descriptor Structure
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The scatter-gather interface fetches the descriptor information from memory in
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the following order:
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.. list-table::
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:header-rows: 1
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* - Size
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- Name
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- Description
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* - 32-bit
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- flags
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- | This field includes 2 control bits:
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* bit0: if set, the transfer will complete after this last descriptor is
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processed and the DMA core will go back to idle state; if cleared, the
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next DMA descriptor pointed to by ``next_sg_addr`` will be loaded.
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* bit1: if set, an end-of-transfer interrupt will be raised after the
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memory segment pointed to by this descriptor has been transferred.
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* - 32-bit
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- id
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- This field corresponds to an identifier of the descriptor.
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* - 64-bit
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- dest_addr
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- This field contains the destination address of the transfer.
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* - 64-bit
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- src_addr
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- This field contains the source address of the transfer.
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* - 64-bit
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- next_sg_addr
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- This field contains the address of the next descriptor.
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* - 32-bit
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- y_len
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- This field contains the number of rows to transfer, minus one.
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* - 32-bit
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- x_len
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- This field contains the number of bytes to transfer, minus one.
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* - 32-bit
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- src_stride
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- This field contains the number of bytes between the start of one row and
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the next row for the source address.
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* - 32-bit
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- dst_stride
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- This field contains the number of bytes between the start of one row and
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the next row for the destination address.
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The ``y_len``, ``src_stride`` and ``dst_stride`` fields are only useful for 2D
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transfers and should be set to 0 if 2D transfers are not required.
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Transfer Configuration
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The scatter-gather transfers are enabled through the ``HWDESC`` bit from the
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``CONTROL`` (``0x400``) register. Once this bit is set, cyclic transfers are
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disabled, since the same cyclic behavior can be replicated using a descriptor
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chain loop.
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To start a scatter-gather transfer, the address of the first DMA descriptor must
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be written to the register pair [``SG_ADDRESS_HIGH`` (``0x4BC``), ``SG_ADDRESS``
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(``0x47C``)].
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To end a scatter-gather transfer, the last descriptor of the transfer must have
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the ``flags[0]`` bit set.
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The scatter-gather transfer is queued in a similar way to the simple transfers,
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through the ``TRANSFER_SUBMIT``. Software should always poll this bit to be 0
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before setting it, otherwise the scatter-gather transfer will not be queued.
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The scatter-gather transfers support the generation of the same two types of
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interrupt events as the simple transfers. However, the scatter-gather transfers
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have the distinct advantage of generating fewer interrupts by treating the
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chained descriptor transfers as a single transfer, thus improving the performance
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of the application.
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Transfer Start Synchronization
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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@ -580,7 +696,7 @@ must hold:
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* ``MAX_BYTES_PER_BURST`` ≤ 4096;
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* ``MAX_BYTES_PER_BURST`` is power of 2;
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* ``SRC/DEST_ADDRESS`` mod ``MAX_BYTES_PER_BURST`` == 0
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* ``SRC/DEST_ADDRESS`` mod ``MAX_BYTES_PER_BURST`` == 0
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* ``SRC/DEST_ADDRESS[11:0]`` + MIN(``X_LENGTH``\ +1,\ ``MAX_BYTES_PER_BURST``) ≤ 4096
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Address Alignment
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@ -617,6 +733,12 @@ bytes.
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Note that the address alignment requirement is not affected by this. The address
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still needs to be aligned to the width of the MM interface that it belongs to.
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Scatter-Gather Datapath Width
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The scatter-gather dedicated interface ``m_sg_axi`` currently supports only
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64-bit transfers. ``DMA_DATA_WIDTH_SG`` can only be set to 64.
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Software Support
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--------------------------------------------------------------------------------
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@ -659,6 +781,6 @@ Glossary
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consecutive beats.
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* - partial transfer
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- Represents a transfer which is shorter than the programmed length that
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is based on the X_LENGTH and Y_LENGTH registers. This can occur on AXIS
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source interfaces when TLAST asserts earlier than the programmed
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is based on the ``X_LENGTH`` and ``Y_LENGTH`` registers. This can occur
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on AXIS source interfaces when TLAST asserts earlier than the programmed
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length.
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@ -9,7 +9,7 @@ ENDTITLE
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REG
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0x000
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VERSION
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Version of the peripheral. Follows semantic versioning. Current version 4.04.61.
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Version of the peripheral. Follows semantic versioning. Current version 4.05.61.
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ENDREG
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FIELD
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@ -19,7 +19,7 @@ RO
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ENDFIELD
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FIELD
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[15:8] 0x03
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[15:8] 0x05
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VERSION_MINOR
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RO
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ENDFIELD
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@ -200,6 +200,15 @@ REG
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CONTROL
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ENDREG
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FIELD
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[2] 0x0
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HWDESC
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RW
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When set to 1 the scatter-gather transfers are enabled.
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Note, this field is only valid if the DMA channel has been configured with SG transfer support.
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ENDFIELD
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FIELD
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[1] 0x0
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PAUSE
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@ -242,7 +251,7 @@ TRANSFER_SUBMIT
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ENDREG
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FIELD
|
||||
[0] 0x00
|
||||
[0] 0x0
|
||||
TRANSFER_SUBMIT
|
||||
RW
|
||||
Writing a 1 to this register queues a new transfer. The bit transitions back to 0 once
|
||||
|
|
@ -464,7 +473,7 @@ STATUS
|
|||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00
|
||||
[31:0] 0x00000000
|
||||
RESERVED
|
||||
RO
|
||||
This register is reserved for future usage. Reading it will always return 0.
|
||||
|
|
@ -479,7 +488,7 @@ CURRENT_DEST_ADDRESS
|
|||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00
|
||||
[31:0] 0x00000000
|
||||
CURRENT_DEST_ADDRESS
|
||||
RO
|
||||
Address to which the next data sample is written to.
|
||||
|
|
@ -496,7 +505,7 @@ CURRENT_SRC_ADDRESS
|
|||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00
|
||||
[31:0] 0x00000000
|
||||
CURRENT_SRC_ADDRESS
|
||||
RO
|
||||
Address form which the next data sample is read.
|
||||
|
|
@ -530,7 +539,7 @@ PARTIAL_TRANSFER_LENGTH
|
|||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x000000
|
||||
[31:0] 0x00000000
|
||||
PARTIAL_LENGTH
|
||||
RO
|
||||
Length of the partial transfer in bytes. Represents the number of bytes received
|
||||
|
|
@ -558,6 +567,41 @@ ENDFIELD
|
|||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x115
|
||||
DESCRIPTOR_ID
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
DESCRIPTOR_ID
|
||||
RO
|
||||
ID of the descriptor that points to the current memory segment being transferred.
|
||||
If HWDESC is set to 0, then this register returns 0.
|
||||
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x11f
|
||||
SG_ADDRESS
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
SG_ADDRESS
|
||||
RW
|
||||
This register contains the starting address of the scatter-gather transfer. The address needs
|
||||
to be aligned to the bus width.
|
||||
|
||||
This register is only valid if the DMA channel has been configured with SG transfer support.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x124
|
||||
DEST_ADDRESS_HIGH
|
||||
|
|
@ -569,7 +613,8 @@ DEST_ADDRESS_HIGH
|
|||
RW
|
||||
This register contains the HIGH segment of the destination address of the transfer.
|
||||
|
||||
This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if DMA channel has been configured for write to memory support.
|
||||
This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if DMA channel
|
||||
has been configured for write to memory support.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
|
|
@ -586,7 +631,8 @@ SRC_ADDRESS_HIGH
|
|||
RW
|
||||
This register contains the HIGH segment of the source address of the transfer.
|
||||
|
||||
This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel has been configured for read from memory support.
|
||||
This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel
|
||||
has been configured for read from memory support.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
|
|
@ -598,12 +644,13 @@ CURRENT_DEST_ADDRESS_HIGH
|
|||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00
|
||||
[31:0] 0x00000000
|
||||
CURRENT_DEST_ADDRESS_HIGH
|
||||
RO
|
||||
HIGH segment of the address to which the next data sample is written to.
|
||||
|
||||
This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel has been configured for write to memory support.
|
||||
This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel
|
||||
has been configured for write to memory support.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
|
|
@ -615,12 +662,31 @@ CURRENT_SRC_ADDRESS_HIGH
|
|||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00
|
||||
[31:0] 0x00000000
|
||||
CURRENT_SRC_ADDRESS_HIGH
|
||||
RO
|
||||
HIGH segment of the address from which the next data sample is read.
|
||||
|
||||
This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel has been configured for read from memory support.
|
||||
This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel
|
||||
has been configured for read from memory support.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x12f
|
||||
SG_ADDRESS_HIGH
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:0] 0x00000000
|
||||
SG_ADDRESS_HIGH
|
||||
RW
|
||||
HIGH segment of the starting address of the scatter-gather transfer.
|
||||
|
||||
This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel
|
||||
has been configured with SG transfer support.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
|
|
|
|||
Loading…
Reference in New Issue