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ad9467_fmc: Made some cosmetic changes on the block design script.

main
Istvan Csomortani 2014-10-20 13:28:34 +03:00
parent 4b8720b551
commit b3c784f76a
1 changed files with 160 additions and 151 deletions
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9
projects/ad9467_fmc/common/ad9467_bd.tcl
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@ -45,6 +45,7 @@ if {$sys_zynq == 1} {
}
# spi
if {$sys_zynq == 0} {
set axi_ad9467_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_ad9467_spi]
set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_ad9467_spi
@ -56,6 +57,7 @@ if {$sys_zynq == 0} {
}
# additions to default configuration
if {$sys_zynq == 0} {
set_property -dict [list CONFIG.NUM_MI {10}] $axi_cpu_interconnect
} else {
@ -68,6 +70,7 @@ if {$sys_zynq == 0} {
}
# clock for ila
if {$sys_zynq == 1} {
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
@ -95,6 +98,7 @@ if {$sys_zynq == 1} {
}
# connections (spi)
if {$sys_zynq == 0} {
connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_ad9467_spi/ss_i]
connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_ad9467_spi/ss_o]
@ -118,6 +122,7 @@ if {$sys_zynq == 0} {
}
# connections (ad9467)
connect_bd_net -net axi_ad9467_adc_clk_in_n [get_bd_ports adc_clk_in_p] [get_bd_pins axi_ad9467/adc_clk_in_p]
connect_bd_net -net axi_ad9467_adc_clk_in_p [get_bd_ports adc_clk_in_n] [get_bd_pins axi_ad9467/adc_clk_in_n]
connect_bd_net -net axi_ad9467_adc_data_in_n [get_bd_ports adc_data_in_n] [get_bd_pins axi_ad9467/adc_data_in_n]
@ -137,6 +142,7 @@ connect_bd_net -net axi_ad9467_dma_dovf [get_bd_pins axi_ad9467/adc_dovf
connect_bd_net -net axi_ad9467_dma_irq [get_bd_pins axi_ad9467_dma/irq] [get_bd_pins sys_concat_intc/In2]
# interconnect (cpu)
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] [get_bd_pins $sys_100m_clk_source]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] [get_bd_pins $sys_100m_clk_source]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] [get_bd_pins $sys_100m_resetn_source]
@ -163,6 +169,7 @@ if {$sys_zynq == 0} {
}
# interconnect (mem/adc)
if {$sys_zynq == 0} {
connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_ad9467_dma/m_dest_axi]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_200m_clk_source
@ -185,6 +192,7 @@ if {$sys_zynq == 0} {
}
# ila (with fifo to prevent timing failure)
set ila_fifo [create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:12.0 ila_fifo]
set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM}] $ila_fifo
set_property -dict [list CONFIG.Input_Data_Width {16}] $ila_fifo
@ -205,6 +213,7 @@ connect_bd_net -net sys_ila_clk [get_bd_pins ila_fifo/rd_clk] [get_bd_pins ila_
connect_bd_net -net xlconstant_0_const [get_bd_pins ila_fifo/rd_en] [get_bd_pins ila_fifo/wr_en] [get_bd_pins ila_constant_1/const]
connect_bd_net -net ila_fifo_dout [get_bd_pins ila_fifo/dout] [get_bd_pins ila_ad9467_mon/probe0]
# address mapping
create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9467/s_axi/axi_lite] SEG_data_ad9467_core