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altera srf files do not work

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Rejeesh Kutty 2017-03-22 09:25:50 -04:00
parent 66a5d44a18
commit b3f06af77a
3 changed files with 0 additions and 3 deletions
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1
projects/common/a10gx/a10gx_system_assign.tcl
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@ -8,7 +8,6 @@ set_global_assignment -name DEVICE 10AX115S3F45E2SGE3
set_global_assignment -name MESSAGE_DISABLE 17951 ; ## disable unused RX channels message set_global_assignment -name MESSAGE_DISABLE 17951 ; ## disable unused RX channels message
set_global_assignment -name MESSAGE_DISABLE 18655 ; ## disable unused TX channels message set_global_assignment -name MESSAGE_DISABLE 18655 ; ## disable unused TX channels message
set_global_assignment -name SOURCE_FILE $ad_hdl_dir/projects/common/altera/messages.srf
# clocks and resets # clocks and resets

1
projects/common/a10soc/a10soc_system_assign.tcl
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@ -8,7 +8,6 @@ set_global_assignment -name DEVICE 10AS066N3F40E2SGE2
set_global_assignment -name MESSAGE_DISABLE 17951 ; ## disable unused RX channels message set_global_assignment -name MESSAGE_DISABLE 17951 ; ## disable unused RX channels message
set_global_assignment -name MESSAGE_DISABLE 18655 ; ## disable unused TX channels message set_global_assignment -name MESSAGE_DISABLE 18655 ; ## disable unused TX channels message
set_global_assignment -name SOURCE_FILE $ad_hdl_dir/projects/common/altera/messages.srf
# clocks and resets # clocks and resets

1
projects/common/altera/messages.srf
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@ -1 +0,0 @@
{ "" "" "" "Timing analysis was performed using a non-final timing model and/or constraints. You must regenerate the external memory interface IP and recheck timing closure in a future version of Quartus Prime." { } { } 0 0 "" 0 0 "Design Software" 0 -1 0 ""}