From b434fe6dd59655562e73f7e34ed89f24a71a4fd4 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Mon, 7 Jul 2014 14:03:01 -0400 Subject: [PATCH] fmcomms5: register map changes --- library/axi_fifo2s/axi_fifo2s_wr.v | 48 +++--- projects/ad9625_fmc/zc706/system_constr.xdc | 4 + projects/common/zc706/zc706_system_mig.prj | 2 +- projects/common/zc706/zc706_system_plddr3.tcl | 7 +- projects/fmcomms5/common/fmcomms5_bd.tcl | 141 ++++++++++++------ 5 files changed, 133 insertions(+), 69 deletions(-) diff --git a/library/axi_fifo2s/axi_fifo2s_wr.v b/library/axi_fifo2s/axi_fifo2s_wr.v index 3b4a75c6a..b43596dfb 100755 --- a/library/axi_fifo2s/axi_fifo2s_wr.v +++ b/library/axi_fifo2s/axi_fifo2s_wr.v @@ -96,8 +96,8 @@ module axi_fifo2s_wr ( parameter AXI_ADDRESS = 32'h00000000; parameter AXI_ADDRLIMIT = 32'h00000000; localparam AXI_AWINCR = (AXI_LENGTH * DATA_WIDTH)/8; - localparam BUF_THRESHOLD_LO = 6'd3; - localparam BUF_THRESHOLD_HI = 6'd60; + localparam BUF_THRESHOLD_LO = 8'd6; + localparam BUF_THRESHOLD_HI = 8'd250; // request and synchronization @@ -153,24 +153,24 @@ module axi_fifo2s_wr ( reg m_xfer_limit = 'd0; reg m_xfer_enable = 'd0; reg [ 31:0] m_xfer_addr = 'd0; - reg [ 5:0] m_waddr = 'd0; - reg [ 5:0] m_waddr_g = 'd0; + reg [ 7:0] m_waddr = 'd0; + reg [ 7:0] m_waddr_g = 'd0; reg m_rel_enable = 'd0; reg m_rel_toggle = 'd0; - reg [ 5:0] m_rel_waddr = 'd0; + reg [ 7:0] m_rel_waddr = 'd0; reg [ 2:0] axi_rel_toggle_m = 'd0; - reg [ 5:0] axi_rel_waddr = 'd0; - reg [ 5:0] axi_waddr_m1 = 'd0; - reg [ 5:0] axi_waddr_m2 = 'd0; - reg [ 5:0] axi_waddr = 'd0; - reg [ 5:0] axi_addr_diff = 'd0; + reg [ 7:0] axi_rel_waddr = 'd0; + reg [ 7:0] axi_waddr_m1 = 'd0; + reg [ 7:0] axi_waddr_m2 = 'd0; + reg [ 7:0] axi_waddr = 'd0; + reg [ 7:0] axi_addr_diff = 'd0; reg axi_almost_full = 'd0; reg axi_dwunf = 'd0; reg axi_almost_empty = 'd0; reg axi_dwovf = 'd0; reg [ 2:0] axi_xfer_req_m = 'd0; reg axi_xfer_init = 'd0; - reg [ 5:0] axi_raddr = 'd0; + reg [ 7:0] axi_raddr = 'd0; reg axi_rd = 'd0; reg axi_rlast = 'd0; reg axi_rd_d = 'd0; @@ -186,7 +186,7 @@ module axi_fifo2s_wr ( // internal signals wire axi_rel_toggle_s; - wire [ 6:0] axi_addr_diff_s; + wire [ 8:0] axi_addr_diff_s; wire axi_wready_s; wire axi_rd_s; wire axi_req_s; @@ -195,11 +195,13 @@ module axi_fifo2s_wr ( // binary to grey conversion - function [5:0] b2g; - input [5:0] b; - reg [5:0] g; + function [7:0] b2g; + input [7:0] b; + reg [7:0] g; begin - g[5] = b[5]; + g[7] = b[7]; + g[6] = b[7] ^ b[6]; + g[5] = b[6] ^ b[5]; g[4] = b[5] ^ b[4]; g[3] = b[4] ^ b[3]; g[2] = b[3] ^ b[2]; @@ -211,11 +213,13 @@ module axi_fifo2s_wr ( // grey to binary conversion - function [5:0] g2b; - input [5:0] g; - reg [5:0] b; + function [7:0] g2b; + input [7:0] g; + reg [7:0] b; begin - b[5] = g[5]; + b[7] = g[7]; + b[6] = b[7] ^ g[6]; + b[5] = b[6] ^ g[5]; b[4] = b[5] ^ g[4]; b[3] = b[4] ^ g[3]; b[2] = b[3] ^ g[2]; @@ -304,7 +308,7 @@ module axi_fifo2s_wr ( axi_almost_empty <= 'd0; axi_dwovf <= 'd0; end else begin - axi_addr_diff <= axi_addr_diff_s[5:0]; + axi_addr_diff <= axi_addr_diff_s[7:0]; if (axi_addr_diff > BUF_THRESHOLD_HI) begin axi_almost_full <= 1'b1; axi_dwunf <= axi_almost_empty; @@ -453,7 +457,7 @@ module axi_fifo2s_wr ( // buffer - ad_mem #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(6)) i_mem ( + ad_mem #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(8)) i_mem ( .clka (m_clk), .wea (m_wr), .addra (m_waddr), diff --git a/projects/ad9625_fmc/zc706/system_constr.xdc b/projects/ad9625_fmc/zc706/system_constr.xdc index 9764a9c37..a339401e3 100644 --- a/projects/ad9625_fmc/zc706/system_constr.xdc +++ b/projects/ad9625_fmc/zc706/system_constr.xdc @@ -39,9 +39,13 @@ set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports adc_fd] create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p] create_clock -name rx_div_clk -period 6.40 [get_nets i_system_wrapper/system_i/axi_ad9625_gt_rx_clk] create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2] +create_clock -name pl_ddr_clk -period 5.00 [get_pins i_system_wrapper/system_i/plddr3_fifo/axi_ddr_cntrl/ui_clk] +create_clock -name pl_dma_clk -period 15.62 [get_pins i_system_wrapper/system_i/plddr3_fifo/axi_ddr_cntrl/ui_addn_clk_0] set_clock_groups -asynchronous -group {rx_div_clk} set_clock_groups -asynchronous -group {fmc_dma_clk} +set_clock_groups -asynchronous -group {pl_ddr_clk} +set_clock_groups -asynchronous -group {pl_dma_clk} set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE] set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE] diff --git a/projects/common/zc706/zc706_system_mig.prj b/projects/common/zc706/zc706_system_mig.prj index 41d1f5695..056ffa08b 100644 --- a/projects/common/zc706/zc706_system_mig.prj +++ b/projects/common/zc706/zc706_system_mig.prj @@ -24,7 +24,7 @@ 4:1 200 1 - 6.000 + 12.500 1 1 1 diff --git a/projects/common/zc706/zc706_system_plddr3.tcl b/projects/common/zc706/zc706_system_plddr3.tcl index 55aac0382..51365c682 100644 --- a/projects/common/zc706/zc706_system_plddr3.tcl +++ b/projects/common/zc706/zc706_system_plddr3.tcl @@ -44,6 +44,7 @@ proc p_plddr3_fifo {p_name m_name m_width} { set_property -dict [list CONFIG.INTERFACE_TYPE {Native}] $wfifo_mem set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM}] $wfifo_mem set_property -dict [list CONFIG.Input_Data_Width $m_width] $wfifo_mem + set_property -dict [list CONFIG.Input_Depth {32}] $wfifo_mem set_property -dict [list CONFIG.Output_Data_Width {512}] $wfifo_mem set_property -dict [list CONFIG.Overflow_Flag {true}] $wfifo_mem @@ -51,10 +52,12 @@ proc p_plddr3_fifo {p_name m_name m_width} { set_property -dict [list CONFIG.INTERFACE_TYPE {Native}] $rfifo_mem set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM}] $rfifo_mem set_property -dict [list CONFIG.Input_Data_Width {512}] $rfifo_mem + set_property -dict [list CONFIG.Input_Depth {32}] $rfifo_mem set_property -dict [list CONFIG.Output_Data_Width {64}] $rfifo_mem set_property -dict [list CONFIG.Overflow_Flag {true}] $rfifo_mem - set_property -dict [list CONFIG.Programmable_Full_Type {Single_Programmable_Full_Threshold_Constant}] $rfifo_mem - set_property -dict [list CONFIG.Full_Threshold_Assert_Value {800}] $rfifo_mem + set_property -dict [list CONFIG.Programmable_Full_Type {Multiple_Programmable_Full_Threshold_Constants}] $rfifo_mem + set_property -dict [list CONFIG.Full_Threshold_Assert_Value {24}] $rfifo_mem + set_property -dict [list CONFIG.Full_Threshold_Negate_Value {12}] $rfifo_mem set axi_fifo2s [create_bd_cell -type ip -vlnv analog.com:user:axi_fifo2s:1.0 axi_fifo2s] set_property -dict [list CONFIG.AXI_ADDRESS {0x80000000}] $axi_fifo2s diff --git a/projects/fmcomms5/common/fmcomms5_bd.tcl b/projects/fmcomms5/common/fmcomms5_bd.tcl index 41792c8f0..a92359fc6 100644 --- a/projects/fmcomms5/common/fmcomms5_bd.tcl +++ b/projects/fmcomms5/common/fmcomms5_bd.tcl @@ -128,6 +128,11 @@ if {$sys_zynq == 0} { set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_fmcomms2_gpio } +set util_adc_pack_0 [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 util_adc_pack_0] +set util_dac_unpack_0 [create_bd_cell -type ip -vlnv analog.com:user:util_dac_unpack:1.0 util_dac_unpack_0] +set util_adc_pack_1 [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 util_adc_pack_1] +set util_dac_unpack_1 [create_bd_cell -type ip -vlnv analog.com:user:util_dac_unpack:1.0 util_dac_unpack_1] + # additions to default configuration if {$sys_zynq == 0} { @@ -196,52 +201,100 @@ connect_bd_net -net axi_ad9361_0_clk [get_bd_pins axi_ad9361_0/l_clk] connect_bd_net -net axi_ad9361_1_clk [get_bd_pins axi_ad9361_1/l_clk] connect_bd_net -net axi_ad9361_0_clk [get_bd_pins axi_ad9361_0/clk] connect_bd_net -net axi_ad9361_0_clk [get_bd_pins axi_ad9361_1/clk] +connect_bd_net -net axi_ad9361_0_clk [get_bd_pins util_adc_pack_0/clk] +connect_bd_net -net axi_ad9361_0_clk [get_bd_pins util_adc_pack_1/clk] connect_bd_net -net axi_ad9361_0_clk [get_bd_pins axi_ad9361_adc_dma/fifo_wr_clk] connect_bd_net -net axi_ad9361_0_clk [get_bd_pins axi_ad9361_dac_dma/fifo_rd_clk] -connect_bd_net -net axi_ad9361_0_dac_enable [get_bd_pins axi_ad9361_0/dac_enable_out] -connect_bd_net -net axi_ad9361_0_dac_enable [get_bd_pins axi_ad9361_0/dac_enable_in] -connect_bd_net -net axi_ad9361_0_dac_enable [get_bd_pins axi_ad9361_1/dac_enable_in] +connect_bd_net -net axi_ad9361_0_dac_sync [get_bd_pins axi_ad9361_0/dac_sync_out] +connect_bd_net -net axi_ad9361_0_dac_sync [get_bd_pins axi_ad9361_0/dac_sync_in] +connect_bd_net -net axi_ad9361_0_dac_sync [get_bd_pins axi_ad9361_1/dac_sync_in] -connect_bd_net -net axi_ad9361_0_rx_clk_in_p [get_bd_ports rx_clk_in_0_p] [get_bd_pins axi_ad9361_0/rx_clk_in_p] -connect_bd_net -net axi_ad9361_0_rx_clk_in_n [get_bd_ports rx_clk_in_0_n] [get_bd_pins axi_ad9361_0/rx_clk_in_n] -connect_bd_net -net axi_ad9361_0_rx_frame_in_p [get_bd_ports rx_frame_in_0_p] [get_bd_pins axi_ad9361_0/rx_frame_in_p] -connect_bd_net -net axi_ad9361_0_rx_frame_in_n [get_bd_ports rx_frame_in_0_n] [get_bd_pins axi_ad9361_0/rx_frame_in_n] -connect_bd_net -net axi_ad9361_0_rx_data_in_p [get_bd_ports rx_data_in_0_p] [get_bd_pins axi_ad9361_0/rx_data_in_p] -connect_bd_net -net axi_ad9361_0_rx_data_in_n [get_bd_ports rx_data_in_0_n] [get_bd_pins axi_ad9361_0/rx_data_in_n] -connect_bd_net -net axi_ad9361_0_tx_clk_out_p [get_bd_ports tx_clk_out_0_p] [get_bd_pins axi_ad9361_0/tx_clk_out_p] -connect_bd_net -net axi_ad9361_0_tx_clk_out_n [get_bd_ports tx_clk_out_0_n] [get_bd_pins axi_ad9361_0/tx_clk_out_n] -connect_bd_net -net axi_ad9361_0_tx_frame_out_p [get_bd_ports tx_frame_out_0_p] [get_bd_pins axi_ad9361_0/tx_frame_out_p] -connect_bd_net -net axi_ad9361_0_tx_frame_out_n [get_bd_ports tx_frame_out_0_n] [get_bd_pins axi_ad9361_0/tx_frame_out_n] -connect_bd_net -net axi_ad9361_0_tx_data_out_p [get_bd_ports tx_data_out_0_p] [get_bd_pins axi_ad9361_0/tx_data_out_p] -connect_bd_net -net axi_ad9361_0_tx_data_out_n [get_bd_ports tx_data_out_0_n] [get_bd_pins axi_ad9361_0/tx_data_out_n] -connect_bd_net -net axi_ad9361_1_rx_clk_in_p [get_bd_ports rx_clk_in_1_p] [get_bd_pins axi_ad9361_1/rx_clk_in_p] -connect_bd_net -net axi_ad9361_1_rx_clk_in_n [get_bd_ports rx_clk_in_1_n] [get_bd_pins axi_ad9361_1/rx_clk_in_n] -connect_bd_net -net axi_ad9361_1_rx_frame_in_p [get_bd_ports rx_frame_in_1_p] [get_bd_pins axi_ad9361_1/rx_frame_in_p] -connect_bd_net -net axi_ad9361_1_rx_frame_in_n [get_bd_ports rx_frame_in_1_n] [get_bd_pins axi_ad9361_1/rx_frame_in_n] -connect_bd_net -net axi_ad9361_1_rx_data_in_p [get_bd_ports rx_data_in_1_p] [get_bd_pins axi_ad9361_1/rx_data_in_p] -connect_bd_net -net axi_ad9361_1_rx_data_in_n [get_bd_ports rx_data_in_1_n] [get_bd_pins axi_ad9361_1/rx_data_in_n] -connect_bd_net -net axi_ad9361_1_tx_clk_out_p [get_bd_ports tx_clk_out_1_p] [get_bd_pins axi_ad9361_1/tx_clk_out_p] -connect_bd_net -net axi_ad9361_1_tx_clk_out_n [get_bd_ports tx_clk_out_1_n] [get_bd_pins axi_ad9361_1/tx_clk_out_n] -connect_bd_net -net axi_ad9361_1_tx_frame_out_p [get_bd_ports tx_frame_out_1_p] [get_bd_pins axi_ad9361_1/tx_frame_out_p] -connect_bd_net -net axi_ad9361_1_tx_frame_out_n [get_bd_ports tx_frame_out_1_n] [get_bd_pins axi_ad9361_1/tx_frame_out_n] -connect_bd_net -net axi_ad9361_1_tx_data_out_p [get_bd_ports tx_data_out_1_p] [get_bd_pins axi_ad9361_1/tx_data_out_p] -connect_bd_net -net axi_ad9361_1_tx_data_out_n [get_bd_ports tx_data_out_1_n] [get_bd_pins axi_ad9361_1/tx_data_out_n] - -connect_bd_net -net axi_ad9361_0_adc_dwr [get_bd_pins axi_ad9361_0/adc_dwr] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_en] -connect_bd_net -net axi_ad9361_0_adc_dsync [get_bd_pins axi_ad9361_0/adc_dsync] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_sync] -connect_bd_net -net axi_ad9361_0_adc_ddata [get_bd_pins axi_ad9361_0/adc_ddata] [get_bd_ports ad9361_0_adc_ddata] -connect_bd_net -net axi_ad9361_1_adc_ddata [get_bd_pins axi_ad9361_1/adc_ddata] [get_bd_ports ad9361_1_adc_ddata] -connect_bd_net -net axi_ad9361_adc_ddata [get_bd_ports ad9361_adc_ddata] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_din] -connect_bd_net -net axi_ad9361_0_adc_dovf [get_bd_pins axi_ad9361_0/adc_dovf] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_overflow] -connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins sys_concat_intc/In2] - -connect_bd_net -net axi_ad9361_0_dac_drd [get_bd_pins axi_ad9361_0/dac_drd] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_en] -connect_bd_net -net axi_ad9361_0_dac_ddata [get_bd_pins axi_ad9361_0/dac_ddata] [get_bd_ports ad9361_0_dac_ddata] -connect_bd_net -net axi_ad9361_1_dac_ddata [get_bd_pins axi_ad9361_1/dac_ddata] [get_bd_ports ad9361_1_dac_ddata] -connect_bd_net -net axi_ad9361_dac_ddata [get_bd_ports ad9361_dac_ddata] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_dout] -connect_bd_net -net axi_ad9361_0_dac_dunf [get_bd_pins axi_ad9361_0/dac_dunf] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_underflow] -connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_pins sys_concat_intc/In3] +connect_bd_net -net axi_ad9361_0_rx_clk_in_p [get_bd_ports rx_clk_in_0_p] [get_bd_pins axi_ad9361_0/rx_clk_in_p] +connect_bd_net -net axi_ad9361_0_rx_clk_in_n [get_bd_ports rx_clk_in_0_n] [get_bd_pins axi_ad9361_0/rx_clk_in_n] +connect_bd_net -net axi_ad9361_0_rx_frame_in_p [get_bd_ports rx_frame_in_0_p] [get_bd_pins axi_ad9361_0/rx_frame_in_p] +connect_bd_net -net axi_ad9361_0_rx_frame_in_n [get_bd_ports rx_frame_in_0_n] [get_bd_pins axi_ad9361_0/rx_frame_in_n] +connect_bd_net -net axi_ad9361_0_rx_data_in_p [get_bd_ports rx_data_in_0_p] [get_bd_pins axi_ad9361_0/rx_data_in_p] +connect_bd_net -net axi_ad9361_0_rx_data_in_n [get_bd_ports rx_data_in_0_n] [get_bd_pins axi_ad9361_0/rx_data_in_n] +connect_bd_net -net axi_ad9361_0_tx_clk_out_p [get_bd_ports tx_clk_out_0_p] [get_bd_pins axi_ad9361_0/tx_clk_out_p] +connect_bd_net -net axi_ad9361_0_tx_clk_out_n [get_bd_ports tx_clk_out_0_n] [get_bd_pins axi_ad9361_0/tx_clk_out_n] +connect_bd_net -net axi_ad9361_0_tx_frame_out_p [get_bd_ports tx_frame_out_0_p] [get_bd_pins axi_ad9361_0/tx_frame_out_p] +connect_bd_net -net axi_ad9361_0_tx_frame_out_n [get_bd_ports tx_frame_out_0_n] [get_bd_pins axi_ad9361_0/tx_frame_out_n] +connect_bd_net -net axi_ad9361_0_tx_data_out_p [get_bd_ports tx_data_out_0_p] [get_bd_pins axi_ad9361_0/tx_data_out_p] +connect_bd_net -net axi_ad9361_0_tx_data_out_n [get_bd_ports tx_data_out_0_n] [get_bd_pins axi_ad9361_0/tx_data_out_n] +connect_bd_net -net axi_ad9361_1_rx_clk_in_p [get_bd_ports rx_clk_in_1_p] [get_bd_pins axi_ad9361_1/rx_clk_in_p] +connect_bd_net -net axi_ad9361_1_rx_clk_in_n [get_bd_ports rx_clk_in_1_n] [get_bd_pins axi_ad9361_1/rx_clk_in_n] +connect_bd_net -net axi_ad9361_1_rx_frame_in_p [get_bd_ports rx_frame_in_1_p] [get_bd_pins axi_ad9361_1/rx_frame_in_p] +connect_bd_net -net axi_ad9361_1_rx_frame_in_n [get_bd_ports rx_frame_in_1_n] [get_bd_pins axi_ad9361_1/rx_frame_in_n] +connect_bd_net -net axi_ad9361_1_rx_data_in_p [get_bd_ports rx_data_in_1_p] [get_bd_pins axi_ad9361_1/rx_data_in_p] +connect_bd_net -net axi_ad9361_1_rx_data_in_n [get_bd_ports rx_data_in_1_n] [get_bd_pins axi_ad9361_1/rx_data_in_n] +connect_bd_net -net axi_ad9361_1_tx_clk_out_p [get_bd_ports tx_clk_out_1_p] [get_bd_pins axi_ad9361_1/tx_clk_out_p] +connect_bd_net -net axi_ad9361_1_tx_clk_out_n [get_bd_ports tx_clk_out_1_n] [get_bd_pins axi_ad9361_1/tx_clk_out_n] +connect_bd_net -net axi_ad9361_1_tx_frame_out_p [get_bd_ports tx_frame_out_1_p] [get_bd_pins axi_ad9361_1/tx_frame_out_p] +connect_bd_net -net axi_ad9361_1_tx_frame_out_n [get_bd_ports tx_frame_out_1_n] [get_bd_pins axi_ad9361_1/tx_frame_out_n] +connect_bd_net -net axi_ad9361_1_tx_data_out_p [get_bd_ports tx_data_out_1_p] [get_bd_pins axi_ad9361_1/tx_data_out_p] +connect_bd_net -net axi_ad9361_1_tx_data_out_n [get_bd_ports tx_data_out_1_n] [get_bd_pins axi_ad9361_1/tx_data_out_n] +connect_bd_net -net axi_ad9361_0_adc_enable_i0 [get_bd_pins axi_ad9361_0/adc_enable_i0] [get_bd_pins util_adc_pack_0/chan_enable_0] +connect_bd_net -net axi_ad9361_0_adc_valid_i0 [get_bd_pins axi_ad9361_0/adc_valid_i0] [get_bd_pins util_adc_pack_0/chan_valid_0] +connect_bd_net -net axi_ad9361_0_adc_data_i0 [get_bd_pins axi_ad9361_0/adc_data_i0] [get_bd_pins util_adc_pack_0/chan_data_0] +connect_bd_net -net axi_ad9361_0_adc_enable_q0 [get_bd_pins axi_ad9361_0/adc_enable_q0] [get_bd_pins util_adc_pack_0/chan_enable_1] +connect_bd_net -net axi_ad9361_0_adc_valid_q0 [get_bd_pins axi_ad9361_0/adc_valid_q0] [get_bd_pins util_adc_pack_0/chan_valid_1] +connect_bd_net -net axi_ad9361_0_adc_data_q0 [get_bd_pins axi_ad9361_0/adc_data_q0] [get_bd_pins util_adc_pack_0/chan_data_1] +connect_bd_net -net axi_ad9361_0_adc_enable_i1 [get_bd_pins axi_ad9361_0/adc_enable_i1] [get_bd_pins util_adc_pack_0/chan_enable_2] +connect_bd_net -net axi_ad9361_0_adc_valid_i1 [get_bd_pins axi_ad9361_0/adc_valid_i1] [get_bd_pins util_adc_pack_0/chan_valid_2] +connect_bd_net -net axi_ad9361_0_adc_data_i1 [get_bd_pins axi_ad9361_0/adc_data_i1] [get_bd_pins util_adc_pack_0/chan_data_2] +connect_bd_net -net axi_ad9361_0_adc_enable_q1 [get_bd_pins axi_ad9361_0/adc_enable_q1] [get_bd_pins util_adc_pack_0/chan_enable_3] +connect_bd_net -net axi_ad9361_0_adc_valid_q1 [get_bd_pins axi_ad9361_0/adc_valid_q1] [get_bd_pins util_adc_pack_0/chan_valid_3] +connect_bd_net -net axi_ad9361_0_adc_data_q1 [get_bd_pins axi_ad9361_0/adc_data_q1] [get_bd_pins util_adc_pack_0/chan_data_3] +connect_bd_net -net axi_ad9361_1_adc_enable_i0 [get_bd_pins axi_ad9361_1/adc_enable_i0] [get_bd_pins util_adc_pack_1/chan_enable_0] +connect_bd_net -net axi_ad9361_1_adc_valid_i0 [get_bd_pins axi_ad9361_1/adc_valid_i0] [get_bd_pins util_adc_pack_1/chan_valid_0] +connect_bd_net -net axi_ad9361_1_adc_data_i0 [get_bd_pins axi_ad9361_1/adc_data_i0] [get_bd_pins util_adc_pack_1/chan_data_0] +connect_bd_net -net axi_ad9361_1_adc_enable_q0 [get_bd_pins axi_ad9361_1/adc_enable_q0] [get_bd_pins util_adc_pack_1/chan_enable_1] +connect_bd_net -net axi_ad9361_1_adc_valid_q0 [get_bd_pins axi_ad9361_1/adc_valid_q0] [get_bd_pins util_adc_pack_1/chan_valid_1] +connect_bd_net -net axi_ad9361_1_adc_data_q0 [get_bd_pins axi_ad9361_1/adc_data_q0] [get_bd_pins util_adc_pack_1/chan_data_1] +connect_bd_net -net axi_ad9361_1_adc_enable_i1 [get_bd_pins axi_ad9361_1/adc_enable_i1] [get_bd_pins util_adc_pack_1/chan_enable_2] +connect_bd_net -net axi_ad9361_1_adc_valid_i1 [get_bd_pins axi_ad9361_1/adc_valid_i1] [get_bd_pins util_adc_pack_1/chan_valid_2] +connect_bd_net -net axi_ad9361_1_adc_data_i1 [get_bd_pins axi_ad9361_1/adc_data_i1] [get_bd_pins util_adc_pack_1/chan_data_2] +connect_bd_net -net axi_ad9361_1_adc_enable_q1 [get_bd_pins axi_ad9361_1/adc_enable_q1] [get_bd_pins util_adc_pack_1/chan_enable_3] +connect_bd_net -net axi_ad9361_1_adc_valid_q1 [get_bd_pins axi_ad9361_1/adc_valid_q1] [get_bd_pins util_adc_pack_1/chan_valid_3] +connect_bd_net -net axi_ad9361_1_adc_data_q1 [get_bd_pins axi_ad9361_1/adc_data_q1] [get_bd_pins util_adc_pack_1/chan_data_3] +connect_bd_net -net axi_ad9361_0_dvalid [get_bd_pins util_adc_pack_0/dvalid] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_en] +connect_bd_net -net axi_ad9361_0_dsync [get_bd_pins util_adc_pack_0/dsync] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_sync] +connect_bd_net -net axi_ad9361_0_adc_ddata [get_bd_pins util_adc_pack_0/ddata] [get_bd_ports ad9361_0_adc_ddata] +connect_bd_net -net axi_ad9361_1_adc_ddata [get_bd_pins util_adc_pack_1/ddata] [get_bd_ports ad9361_1_adc_ddata] +connect_bd_net -net axi_ad9361_adc_ddata [get_bd_ports ad9361_adc_ddata] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_din] +connect_bd_net -net axi_ad9361_0_dac_enable_0 [get_bd_pins axi_ad9361_0/dac_enable_i0] [get_bd_pins util_dac_unpack_0/dac_enable_00] +connect_bd_net -net axi_ad9361_0_dac_valid_0 [get_bd_pins axi_ad9361_0/dac_valid_i0] [get_bd_pins util_dac_unpack_0/dac_valid_00] +connect_bd_net -net axi_ad9361_0_dac_data_0 [get_bd_pins axi_ad9361_0/dac_data_i0] [get_bd_pins util_dac_unpack_0/dac_data_00] +connect_bd_net -net axi_ad9361_0_dac_enable_1 [get_bd_pins axi_ad9361_0/dac_enable_q0] [get_bd_pins util_dac_unpack_0/dac_enable_01] +connect_bd_net -net axi_ad9361_0_dac_valid_1 [get_bd_pins axi_ad9361_0/dac_valid_q0] [get_bd_pins util_dac_unpack_0/dac_valid_01] +connect_bd_net -net axi_ad9361_0_dac_data_1 [get_bd_pins axi_ad9361_0/dac_data_q0] [get_bd_pins util_dac_unpack_0/dac_data_01] +connect_bd_net -net axi_ad9361_0_dac_enable_2 [get_bd_pins axi_ad9361_0/dac_enable_i1] [get_bd_pins util_dac_unpack_0/dac_enable_02] +connect_bd_net -net axi_ad9361_0_dac_valid_2 [get_bd_pins axi_ad9361_0/dac_valid_i1] [get_bd_pins util_dac_unpack_0/dac_valid_02] +connect_bd_net -net axi_ad9361_0_dac_data_2 [get_bd_pins axi_ad9361_0/dac_data_i1] [get_bd_pins util_dac_unpack_0/dac_data_02] +connect_bd_net -net axi_ad9361_0_dac_enable_3 [get_bd_pins axi_ad9361_0/dac_enable_q1] [get_bd_pins util_dac_unpack_0/dac_enable_03] +connect_bd_net -net axi_ad9361_0_dac_valid_3 [get_bd_pins axi_ad9361_0/dac_valid_q1] [get_bd_pins util_dac_unpack_0/dac_valid_03] +connect_bd_net -net axi_ad9361_0_dac_data_3 [get_bd_pins axi_ad9361_0/dac_data_q1] [get_bd_pins util_dac_unpack_0/dac_data_03] +connect_bd_net -net axi_ad9361_1_dac_enable_0 [get_bd_pins axi_ad9361_1/dac_enable_i0] [get_bd_pins util_dac_unpack_1/dac_enable_00] +connect_bd_net -net axi_ad9361_1_dac_valid_0 [get_bd_pins axi_ad9361_1/dac_valid_i0] [get_bd_pins util_dac_unpack_1/dac_valid_00] +connect_bd_net -net axi_ad9361_1_dac_data_0 [get_bd_pins axi_ad9361_1/dac_data_i0] [get_bd_pins util_dac_unpack_1/dac_data_00] +connect_bd_net -net axi_ad9361_1_dac_enable_1 [get_bd_pins axi_ad9361_1/dac_enable_q0] [get_bd_pins util_dac_unpack_1/dac_enable_01] +connect_bd_net -net axi_ad9361_1_dac_valid_1 [get_bd_pins axi_ad9361_1/dac_valid_q0] [get_bd_pins util_dac_unpack_1/dac_valid_01] +connect_bd_net -net axi_ad9361_1_dac_data_1 [get_bd_pins axi_ad9361_1/dac_data_q0] [get_bd_pins util_dac_unpack_1/dac_data_01] +connect_bd_net -net axi_ad9361_1_dac_enable_2 [get_bd_pins axi_ad9361_1/dac_enable_i1] [get_bd_pins util_dac_unpack_1/dac_enable_02] +connect_bd_net -net axi_ad9361_1_dac_valid_2 [get_bd_pins axi_ad9361_1/dac_valid_i1] [get_bd_pins util_dac_unpack_1/dac_valid_02] +connect_bd_net -net axi_ad9361_1_dac_data_2 [get_bd_pins axi_ad9361_1/dac_data_i1] [get_bd_pins util_dac_unpack_1/dac_data_02] +connect_bd_net -net axi_ad9361_1_dac_enable_3 [get_bd_pins axi_ad9361_1/dac_enable_q1] [get_bd_pins util_dac_unpack_1/dac_enable_03] +connect_bd_net -net axi_ad9361_1_dac_valid_3 [get_bd_pins axi_ad9361_1/dac_valid_q1] [get_bd_pins util_dac_unpack_1/dac_valid_03] +connect_bd_net -net axi_ad9361_1_dac_data_3 [get_bd_pins axi_ad9361_1/dac_data_q1] [get_bd_pins util_dac_unpack_1/dac_data_03] +connect_bd_net -net axi_ad9361_0_dac_drd [get_bd_pins util_dac_unpack_0/dma_rd] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_en] +connect_bd_net -net axi_ad9361_0_dac_ddata [get_bd_pins util_dac_unpack_0/dma_data] [get_bd_ports ad9361_0_dac_ddata] +connect_bd_net -net axi_ad9361_1_dac_ddata [get_bd_pins util_dac_unpack_1/dma_data] [get_bd_ports ad9361_1_dac_ddata] +connect_bd_net -net axi_ad9361_dac_ddata [get_bd_ports ad9361_dac_ddata] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_dout] +connect_bd_net -net axi_ad9361_0_adc_dovf [get_bd_pins axi_ad9361_0/adc_dovf] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_overflow] +connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins sys_concat_intc/In2] +connect_bd_net -net axi_ad9361_0_dac_dunf [get_bd_pins axi_ad9361_0/dac_dunf] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_underflow] +connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_pins sys_concat_intc/In3] # interconnect (cpu) @@ -335,7 +388,7 @@ if {$xl_board eq "zc702"} { set_property -dict [list CONFIG.C_PROBE1_WIDTH {128}] $ila_adc_0 connect_bd_net -net axi_ad9361_0_clk [get_bd_pins ila_adc_0/clk] - connect_bd_net -net axi_ad9361_0_adc_dwr [get_bd_pins ila_adc_0/probe0] + connect_bd_net -net axi_ad9361_0_dvalid [get_bd_pins ila_adc_0/probe0] connect_bd_net -net axi_ad9361_adc_ddata [get_bd_pins ila_adc_0/probe1] } else { @@ -354,7 +407,7 @@ if {$xl_board eq "zc702"} { connect_bd_net -net axi_ad9361_0_dev_l_dbg_data [get_bd_pins axi_ad9361_0/dev_l_dbg_data] [get_bd_pins ila_adc_0/probe0] connect_bd_net -net axi_ad9361_0_dev_dbg_data [get_bd_pins axi_ad9361_0/dev_dbg_data] [get_bd_pins ila_adc_0/probe1] connect_bd_net -net axi_ad9361_1_dev_dbg_data [get_bd_pins axi_ad9361_1/dev_dbg_data] [get_bd_pins ila_adc_0/probe2] - connect_bd_net -net axi_ad9361_0_adc_dwr [get_bd_pins ila_adc_0/probe3] + connect_bd_net -net axi_ad9361_0_dvalid [get_bd_pins ila_adc_0/probe3] connect_bd_net -net axi_ad9361_adc_ddata [get_bd_pins ila_adc_0/probe4] # ila (adc) slave