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axi_adc_trigger: Fix triggered flag

main
Adrian Costina 2017-07-03 13:00:51 +03:00
parent 291718d6a8
commit b4467ff4dc
5 changed files with 32 additions and 22 deletions
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1
library/axi_adc_trigger/Makefile
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@ -7,7 +7,6 @@
M_DEPS += ../common/up_axi.v M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_xfer_cntrl.v M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += axi_adc_trigger.v M_DEPS += axi_adc_trigger.v

27
library/axi_adc_trigger/axi_adc_trigger.v
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@ -157,6 +157,14 @@ module axi_adc_trigger(
reg trigger_b; reg trigger_b;
reg trigger_out_mixed; reg trigger_out_mixed;
reg up_triggered;
reg up_triggered_d1;
reg up_triggered_d2;
reg up_triggered_set;
reg up_triggered_reset;
reg up_triggered_reset_d1;
reg up_triggered_reset_d2;
reg [14:0] data_a_r; reg [14:0] data_a_r;
reg [14:0] data_b_r; reg [14:0] data_b_r;
@ -210,6 +218,23 @@ module axi_adc_trigger(
end end
end end
always @(posedge clk) begin
if (data_valid_a_r == 1'b1 && trigger_out_mixed == 1'b1) begin
up_triggered_set <= 1'b1;
end else if (up_triggered_reset == 1'b1) begin
up_triggered_set <= 1'b0;
end
up_triggered_reset_d1 <= up_triggered;
up_triggered_reset_d2 <= up_triggered_reset_d1;
up_triggered_reset <= up_triggered_reset_d2;
end
always @(posedge up_clk) begin
up_triggered_d1 <= up_triggered_set;
up_triggered_d2 <= up_triggered_d1;
up_triggered <= up_triggered_d2;
end
always @(posedge clk) begin always @(posedge clk) begin
data_a_r <= data_a[14:0]; data_a_r <= data_a[14:0];
data_valid_a_r <= data_valid_a; data_valid_a_r <= data_valid_a;
@ -365,7 +390,7 @@ module axi_adc_trigger(
.io_selection(io_selection), .io_selection(io_selection),
.trigger_o(trigger_o), .trigger_o(trigger_o),
.triggered(trigger_out_mixed), .triggered(up_triggered),
.low_level(low_level), .low_level(low_level),
.high_level(high_level), .high_level(high_level),

6
library/axi_adc_trigger/axi_adc_trigger_constr.xdc
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@ -7,6 +7,8 @@ set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *trigger_b_d*}]
set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg && IS_SEQUENTIAL}] set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg && IS_SEQUENTIAL}] set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_data* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}] set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_data* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *trigger_a_d1_reg* && IS_SEQUENTIAL}] set_false_path -to [get_cells -hier -filter {name =~ *trigger_a_d1_reg* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *trigger_b_d1_reg* && IS_SEQUENTIAL}] set_false_path -to [get_cells -hier -filter {name =~ *trigger_b_d1_reg* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *up_triggered_d1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *up_triggered_reset_d1* && IS_SEQUENTIAL}]

1
library/axi_adc_trigger/axi_adc_trigger_ip.tcl
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@ -6,7 +6,6 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_adc_trigger adi_ip_create axi_adc_trigger
adi_ip_files axi_adc_trigger [list \ adi_ip_files axi_adc_trigger [list \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_axi.v" \ "$ad_hdl_dir/library/common/up_axi.v" \
"axi_adc_trigger_constr.xdc" \ "axi_adc_trigger_constr.xdc" \
"axi_adc_trigger_reg.v" \ "axi_adc_trigger_reg.v" \

19
library/axi_adc_trigger/axi_adc_trigger_reg.v
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@ -79,7 +79,6 @@ module axi_adc_trigger_reg (
// internal signals // internal signals
wire [ 9:0] config_trigger; wire [ 9:0] config_trigger;
wire adc_triggered;
// internal registers // internal registers
@ -168,10 +167,10 @@ module axi_adc_trigger_reg (
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'he)) begin if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'he)) begin
up_fifo_depth <= up_wdata; up_fifo_depth <= up_wdata;
end end
if (adc_triggered == 1'b1) begin if (triggered == 1'b1) begin
up_triggered <= 1'b1; up_triggered <= 1'b1;
end else if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hf)) begin end else if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hf)) begin
up_triggered <= up_wdata[0]; up_triggered <= up_triggered & ~up_wdata[0];
end end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h10)) begin if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h10)) begin
up_trigger_delay <= up_wdata; up_trigger_delay <= up_wdata;
@ -246,20 +245,6 @@ module axi_adc_trigger_reg (
fifo_depth, // 32 fifo_depth, // 32
trigger_delay})); // 32 trigger_delay})); // 32
up_xfer_status #(.DATA_WIDTH(1)) i_xfer_status (
// up interface
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_data_status(adc_triggered),
// device interface
.d_rst(1'd0),
.d_clk(clk),
.d_data_status(triggered));
endmodule endmodule
// *************************************************************************** // ***************************************************************************