Replace other master branch references to main
* README.md * adi_regmap_xcvr.txt * build_hdl.rst * hdl_coding_guideline.rst * data_offload/README.md Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>main
Iulia Moldovan
imoldovan
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README.md
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README.md
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@ -43,7 +43,7 @@ There is no free replacement for consulting services. If you have questions that
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## Getting started
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This repository supports reference designs for different [Analog Devices boards](../master/projects) based on [Intel and Xilinx FPGA development boards](../master/projects/common) or standalone.
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This repository supports reference designs for different [Analog Devices boards](../main/projects) based on [Intel and Xilinx FPGA development boards](../main/projects/common) or standalone.
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### Building documentation
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@ -95,12 +95,14 @@ more information.
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* If you want to use the most stable code base, always use the [latest release branch](https://github.com/analogdevicesinc/hdl/releases).
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* If you want to use the greatest and latest, check out the [master branch](https://github.com/analogdevicesinc/hdl/tree/master).
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* If you want to use the greatest and latest, check out the [main branch](https://github.com/analogdevicesinc/hdl/tree/main).
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## Use already built files
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You can download already built files and use them as they are. They are available on [this link]( https://swdownloads.analog.com/cse/hdl_builds/master/latest_boot_partition.tar.gz).
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The files are built from [master branch](https://github.com/analogdevicesinc/hdl/tree/master) whenever there are new commits in HDL or Linux repositories.
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You can download already built files and use them as they are.
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For the main branch, they are available at the link inside [this document](https://swdownloads.analog.com/cse/boot_partition_files/main/latest_boot.txt). Keep in mind that the ones from the main branch are not stable all the time.
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We suggest using the latest release branch [2022_r2, here](https://swdownloads.analog.com/cse/boot_partition_files/2022_r2/latest_boot.txt).
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The files are built from [main branch](https://github.com/analogdevicesinc/hdl/tree/main) whenever there are new commits in HDL or Linux repositories.
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> :warning: Pay attention when using already built files, since they are not tested in HW!
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@ -114,14 +116,14 @@ terms.
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The user should read each of these license terms, and understand the
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freedoms and responsibilities that he or she has by using this source/core.
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See [LICENSE](../master/LICENSE) for more details. The separate license files
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See [LICENSE](../main/LICENSE) for more details. The separate license files
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cab be found here:
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* [LICENSE_ADIBSD](../master/LICENSE_ADIBSD)
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* [LICENSE_ADIBSD](../main/LICENSE_ADIBSD)
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* [LICENSE_GPL2](../master/LICENSE_GPL2)
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* [LICENSE_GPL2](../main/LICENSE_GPL2)
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* [LICENSE_LGPL](../master/LICENSE_LGPL)
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* [LICENSE_LGPL](../main/LICENSE_LGPL)
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## Comprehensive user guide
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@ -110,7 +110,7 @@ ENDFIELD
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REG
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0x0007
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FPGA_INFO
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FPGA device information [[https://github.com/analogdevicesinc/hdl/blob/master/library/scripts/adi_xilinx_device_info_enc.tcl |Xilinx encoded values]]
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FPGA device information [[https://github.com/analogdevicesinc/hdl/blob/main/library/scripts/adi_xilinx_device_info_enc.tcl |Xilinx encoded values]]
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ENDREG
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FIELD
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@ -198,7 +198,7 @@ FIELD
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[19:16]
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XCVR_TYPE[3:0]
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RO
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[[https://github.com/analogdevicesinc/hdl/blob/master/library/scripts/adi_xilinx_device_info_enc.tcl | Xilinx encoded values.]]
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[[https://github.com/analogdevicesinc/hdl/blob/main/library/scripts/adi_xilinx_device_info_enc.tcl | Xilinx encoded values.]]
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ENDFIELD
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FIELD
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@ -31,8 +31,8 @@ HDL project from the repository:
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- Starting with ``hdl_2021_r1`` release branch:
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:git-hdl:`scripts/adi_env.tcl`
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- For ``hdl_2019_r2`` and older:
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:git-hdl:`hdl/projects/scripts/adi_project_xilinx.tcl <projects/scripts/adi_project_xilinx.tcl>` for Vivado, and
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:git-hdl:`hdl/projects/scripts/adi_project_intel.tcl <projects/scripts/adi_project_intel.tcl>` for Quartus.
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:git-hdl:`hdl/projects/scripts/adi_project_xilinx.tcl <hdl_2019_r2:projects/scripts/adi_project_xilinx.tcl>` for Vivado, and
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:git-hdl:`hdl/projects/scripts/adi_project_intel.tcl <hdl_2019_r2:projects/scripts/adi_project_intel.tcl>` for Quartus.
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#. Download the tools from the following links:
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@ -95,7 +95,7 @@ Setup the HDL repository
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-------------------------------------------------------------------------------
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These designs are built upon ADI's generic HDL reference designs framework.
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ADI does not distribute the bit/elf files of these projects so they
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must be built from the sources available :git-hdl:`here <master:/>`. To get
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must be built from the sources available :git-hdl:`here </>`. To get
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the source you must
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`clone <https://git-scm.com/book/en/v2/Git-Basics-Getting-a-Git-Repository>`__
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the repository. This is the best method to get the sources. Here, we are
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@ -668,10 +668,10 @@ to use an unsupported version of tools.
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The easiest way is to check the `release
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notes <https://github.com/analogdevicesinc/hdl/releases>`__. You may
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also check out or browse the desired branch, and verify the tool version
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in the base Tcl script
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(`./hdl/projects/scripts/adi_project_xilinx.tcl <https://github.com/analogdevicesinc/hdl/blob/master/projects/scripts/adi_project_xilinx.tcl#L4>`__)
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in the base Tcl script ./hdl/scripts/adi_env.tcl
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(:git-hdl:`for Vivado version <scripts/adi_env.tcl#L18>`)
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or
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(`./hdl/projects/scripts/adi_project_intel.tcl <https://github.com/analogdevicesinc/hdl/blob/master/projects/scripts/adi_project_intel.tcl#L5>`__),
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(:git-hdl:`or for Quartus version <scripts/adi_env.tcl#L34>`),
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which build the projects.
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Environment
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@ -686,7 +686,7 @@ Annex 1 Verilog file format
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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@ -783,7 +783,7 @@ Annex 2 VHDL file format
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--
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-- 2. An ADI specific BSD license, which can be found in the top level directory
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-- of this repository (LICENSE_ADIBSD), and also on-line at:
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-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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-- https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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-- This will allow to generate bit files and not release the source code,
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-- as long as it attaches to an ADI device.
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--
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@ -256,7 +256,7 @@ A general frequency relationship of the above clocks are:
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CLKdma <= CLKddr <= CLKconverter
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```
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The clock domain crossing should be handled by the [util_axis_fifo](https://github.com/analogdevicesinc/hdl/tree/master/library/util_axis_fifo) module.
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The clock domain crossing should be handled by the [util_axis_fifo](https://github.com/analogdevicesinc/hdl/tree/main/library/util_axis_fifo) module.
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* **TODO** : Make sure that we support both AXIS and FIFO
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* **TODO** : Add support for asymmetric aspect ratio.
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