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ad_ip_jesd204_tpl_adc: add support for 64 channels

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Laszlo Nagy 2020-02-17 16:44:45 +00:00 committed by Laszlo Nagy
parent 2ca09adaf7
commit b49928fca6
3 changed files with 14 additions and 14 deletions
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4
library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v
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@ -64,7 +64,7 @@ module ad_ip_jesd204_tpl_adc #(
input s_axi_awvalid, input s_axi_awvalid,
output s_axi_awready, output s_axi_awready,
input [11:0] s_axi_awaddr, input [12:0] s_axi_awaddr,
input [2:0] s_axi_awprot, input [2:0] s_axi_awprot,
input s_axi_wvalid, input s_axi_wvalid,
@ -78,7 +78,7 @@ module ad_ip_jesd204_tpl_adc #(
input s_axi_arvalid, input s_axi_arvalid,
output s_axi_arready, output s_axi_arready,
input [11:0] s_axi_araddr, input [12:0] s_axi_araddr,
input [2:0] s_axi_arprot, input [2:0] s_axi_arprot,
output s_axi_rvalid, output s_axi_rvalid,

2
library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl
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@ -72,7 +72,7 @@ adi_add_bus_clock "link_clk" "link"
foreach {p v} { foreach {p v} {
"NUM_LANES" "1 2 3 4 8 16" \ "NUM_LANES" "1 2 3 4 8 16" \
"NUM_CHANNELS" "1 2 4 6 8 16 32" \ "NUM_CHANNELS" "1 2 4 6 8 16 32 64" \
"BITS_PER_SAMPLE" "8 12 16" \ "BITS_PER_SAMPLE" "8 12 16" \
"CONVERTER_RESOLUTION" "8 11 12 16" \ "CONVERTER_RESOLUTION" "8 11 12 16" \
"SAMPLES_PER_FRAME" "1 2 3 4 6 8 12 16" \ "SAMPLES_PER_FRAME" "1 2 3 4 6 8 12 16" \

22
library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v
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@ -37,7 +37,7 @@ module ad_ip_jesd204_tpl_adc_regmap #(
input s_axi_aclk, input s_axi_aclk,
input s_axi_aresetn, input s_axi_aresetn,
input s_axi_awvalid, input s_axi_awvalid,
input [11:0] s_axi_awaddr, input [12:0] s_axi_awaddr,
input [2:0] s_axi_awprot, input [2:0] s_axi_awprot,
output s_axi_awready, output s_axi_awready,
input s_axi_wvalid, input s_axi_wvalid,
@ -48,7 +48,7 @@ module ad_ip_jesd204_tpl_adc_regmap #(
output [ 1:0] s_axi_bresp, output [ 1:0] s_axi_bresp,
input s_axi_bready, input s_axi_bready,
input s_axi_arvalid, input s_axi_arvalid,
input [11:0] s_axi_araddr, input [12:0] s_axi_araddr,
input [2:0] s_axi_arprot, input [2:0] s_axi_arprot,
output s_axi_arready, output s_axi_arready,
output s_axi_rvalid, output s_axi_rvalid,
@ -106,11 +106,11 @@ module ad_ip_jesd204_tpl_adc_regmap #(
wire up_rstn; wire up_rstn;
wire up_wreq_s; wire up_wreq_s;
wire [9:0] up_waddr_s; wire [10:0] up_waddr_s;
wire [31:0] up_wdata_s; wire [31:0] up_wdata_s;
wire [NUM_CHANNELS+1:0] up_wack_s; wire [NUM_CHANNELS+1:0] up_wack_s;
wire up_rreq_s; wire up_rreq_s;
wire [9:0] up_raddr_s; wire [10:0] up_raddr_s;
wire [31:0] up_rdata_s[0:NUM_CHANNELS+1]; wire [31:0] up_rdata_s[0:NUM_CHANNELS+1];
wire [NUM_CHANNELS+1:0] up_rack_s; wire [NUM_CHANNELS+1:0] up_rack_s;
@ -135,13 +135,13 @@ module ad_ip_jesd204_tpl_adc_regmap #(
// up bus interface // up bus interface
up_axi #( up_axi #(
.AXI_ADDRESS_WIDTH (12) .AXI_ADDRESS_WIDTH (13)
) i_up_axi ( ) i_up_axi (
.up_clk (up_clk), .up_clk (up_clk),
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_axi_awvalid (s_axi_awvalid), .up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr ({4'b0,s_axi_awaddr}), .up_axi_awaddr ({3'b0,s_axi_awaddr}),
.up_axi_awready (s_axi_awready), .up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid), .up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata), .up_axi_wdata (s_axi_wdata),
@ -151,7 +151,7 @@ module ad_ip_jesd204_tpl_adc_regmap #(
.up_axi_bresp (s_axi_bresp), .up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready), .up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid), .up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr ({4'b0,s_axi_araddr}), .up_axi_araddr ({3'b0,s_axi_araddr}),
.up_axi_arready (s_axi_arready), .up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid), .up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp), .up_axi_rresp (s_axi_rresp),
@ -244,11 +244,11 @@ module ad_ip_jesd204_tpl_adc_regmap #(
.up_clk (up_clk), .up_clk (up_clk),
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_wreq (up_wreq_s), .up_wreq (up_wreq_s),
.up_waddr ({4'b0,up_waddr_s}), .up_waddr ({3'b0,up_waddr_s}),
.up_wdata (up_wdata_s), .up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]), .up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s), .up_rreq (up_rreq_s),
.up_raddr ({4'b0,up_raddr_s}), .up_raddr ({3'b0,up_raddr_s}),
.up_rdata (up_rdata_s[0]), .up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]) .up_rack (up_rack_s[0])
); );
@ -302,11 +302,11 @@ module ad_ip_jesd204_tpl_adc_regmap #(
.up_clk (up_clk), .up_clk (up_clk),
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_wreq (up_wreq_s), .up_wreq (up_wreq_s),
.up_waddr ({4'b0,up_waddr_s}), .up_waddr ({3'b0,up_waddr_s}),
.up_wdata (up_wdata_s), .up_wdata (up_wdata_s),
.up_wack (up_wack_s[i+1]), .up_wack (up_wack_s[i+1]),
.up_rreq (up_rreq_s), .up_rreq (up_rreq_s),
.up_raddr ({4'b0,up_raddr_s}), .up_raddr ({3'b0,up_raddr_s}),
.up_rdata (up_rdata_s[i+1]), .up_rdata (up_rdata_s[i+1]),
.up_rack (up_rack_s[i+1]) .up_rack (up_rack_s[i+1])
); );