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a5soc: constraints for false paths

main
Rejeesh Kutty 2014-04-30 15:07:47 -04:00
parent a10043c4f4
commit b55d0d7ad1
2 changed files with 90 additions and 88 deletions
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16
projects/fmcjesdadc1/a5soc/system_constr.sdc
View File

@ -1,16 +1,18 @@
create_clock -period "20.000 ns" -name n_clk_50m [get_ports {sys_clk}]
create_clock -period "4.000 ns" -name n_clk_250m [get_ports {ref_clk}]
create_clock -period "20.000 ns" -name clk_50m [get_ports {sys_clk}]
create_clock -period "4.000 ns" -name clk_250m [get_ports {ref_clk}]
create_clock -period "5.000 ns" -name clk_200m [get_pins {i_system_bd|sys_hps|fpga_interfaces|clocks_resets|h2f_user0_clk}]
derive_pll_clocks
derive_clock_uncertainty
#set clk_500m [get_clocks {i_system_bd|sys_jesd204b_s1_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_rxlink [get_clocks {i_system_bd|sys_jesd204b_s1_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
set_false_path -from {sys_resetn} -to *
#set_false_path -from $clk_50m -to $clk_rxlink
#set_false_path -from $clk_rxlink -to $clk_50m
set_false_path -from clk_50m -to clk_200m
set_false_path -from clk_50m -to $clk_rxlink
set_false_path -from clk_200m -to clk_50m
set_false_path -from clk_200m -to $clk_rxlink
set_false_path -from $clk_rxlink -to clk_50m
set_false_path -from $clk_rxlink -to clk_200m

4
projects/fmcjesdadc1/a5soc/system_top.v
View File

@ -152,7 +152,7 @@ module system_top (
// hps
output [14:0] ddr3_a;
output [ 14:0] ddr3_a;
output [ 2:0] ddr3_ba;
output ddr3_ck_p;
output ddr3_ck_n;
@ -162,7 +162,7 @@ module system_top (
output ddr3_cas_n;
output ddr3_we_n;
output ddr3_reset_n;
inout [39:0] ddr3_dq;
inout [ 39:0] ddr3_dq;
inout [ 4:0] ddr3_dqs_p;
inout [ 4:0] ddr3_dqs_n;
output ddr3_odt;