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daq2/kcu105: timing improvement -register slices hang

main
Rejeesh Kutty 2014-09-08 10:23:40 -04:00
parent 0966366514
commit b58e425b44
2 changed files with 59 additions and 15 deletions
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46
projects/common/kcu105/kcu105_system_bd.tcl
View File

@ -98,13 +98,31 @@ set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect
# instance: axi interconnect
set axi_mem_aux_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_aux_interconnect]
set_property -dict [list CONFIG.NUM_SI {2}] $axi_mem_aux_interconnect
set_property -dict [list CONFIG.NUM_MI {1}] $axi_mem_aux_interconnect
set_property -dict [list CONFIG.ENABLE_ADVANCED_OPTIONS {1}] $axi_mem_aux_interconnect
set_property -dict [list CONFIG.XBAR_DATA_WIDTH {512}] $axi_mem_aux_interconnect
set_property -dict [list CONFIG.STRATEGY {2}] $axi_mem_aux_interconnect
# set_property -dict [list CONFIG.S00_HAS_REGSLICE {4}] $axi_mem_aux_interconnect
# set_property -dict [list CONFIG.S01_HAS_REGSLICE {4}] $axi_mem_aux_interconnect
set_property -dict [list CONFIG.M00_HAS_REGSLICE {4}] $axi_mem_aux_interconnect
set axi_mem_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_interconnect]
set_property -dict [list CONFIG.NUM_SI {8}] $axi_mem_interconnect
set_property -dict [list CONFIG.NUM_MI {1}] $axi_mem_interconnect
set_property -dict [list CONFIG.ENABLE_ADVANCED_OPTIONS {1}] $axi_mem_interconnect
set_property -dict [list CONFIG.XBAR_DATA_WIDTH {512}] $axi_mem_interconnect
set_property -dict [list CONFIG.STRATEGY {2}] $axi_mem_interconnect
set_property -dict [list CONFIG.M00_HAS_REGSLICE {4}] $axi_mem_interconnect
# set_property -dict [list CONFIG.S00_HAS_REGSLICE {4}] $axi_mem_interconnect
# set_property -dict [list CONFIG.S01_HAS_REGSLICE {4}] $axi_mem_interconnect
# set_property -dict [list CONFIG.S02_HAS_REGSLICE {4}] $axi_mem_interconnect
# set_property -dict [list CONFIG.S03_HAS_REGSLICE {4}] $axi_mem_interconnect
# set_property -dict [list CONFIG.S04_HAS_REGSLICE {4}] $axi_mem_interconnect
# set_property -dict [list CONFIG.S05_HAS_REGSLICE {4}] $axi_mem_interconnect
# set_property -dict [list CONFIG.S06_HAS_REGSLICE {4}] $axi_mem_interconnect
# set_property -dict [list CONFIG.S07_HAS_REGSLICE {4}] $axi_mem_interconnect
# set_property -dict [list CONFIG.M00_HAS_REGSLICE {4}] $axi_mem_interconnect
# instance: default peripherals
@ -249,11 +267,13 @@ connect_bd_net -net sys_200m_clk $sys_200m_clk_source
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M06_ARESETN] $sys_resetn_source
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/ARESETN] $sys_resetn_source
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/ARESETN] $sys_resetn_source
connect_bd_net -net sys_mem_rstn [get_bd_pins axi_mem_interconnect/ARESETN] $sys_mem_resetn_source
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M06_ACLK] $sys_cpu_clk_source
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/ACLK] $sys_cpu_clk_source
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/ACLK] $sys_cpu_clk_source
connect_bd_net -net sys_mem_clk [get_bd_pins axi_mem_interconnect/ACLK] $sys_mem_clk_source
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/ARESETN] $sys_resetn_source
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_aux_interconnect/ARESETN] $sys_resetn_source
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M06_ACLK] $sys_cpu_clk_source
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/ACLK] $sys_cpu_clk_source
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/ACLK] $sys_cpu_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/ACLK] $sys_200m_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_aux_interconnect/ACLK] $sys_200m_clk_source
connect_bd_net -net sys_cpu_rstn [get_bd_pins sys_mb_debug/S_AXI_ARESETN]
connect_bd_net -net sys_mem_rstn [get_bd_pins axi_ddr_cntrl/c0_ddr4_aresetn]
@ -325,19 +345,27 @@ connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M00_ACLK] $sys
# defaults (interconnect - memory)
connect_bd_intf_net -intf_net axi_mem_interconnect_m00 [get_bd_intf_pins axi_mem_interconnect/M00_AXI] [get_bd_intf_pins axi_ddr_cntrl/C0_DDR4_S_AXI]
connect_bd_intf_net -intf_net axi_mem_aux_interconnect_m00 [get_bd_intf_pins axi_mem_aux_interconnect/M00_AXI] [get_bd_intf_pins axi_ddr_cntrl/C0_DDR4_S_AXI]
connect_bd_intf_net -intf_net axi_mem_aux_interconnect_s00 [get_bd_intf_pins axi_mem_aux_interconnect/S00_AXI] [get_bd_intf_pins axi_mem_interconnect/M00_AXI]
connect_bd_net -net sys_mem_rstn [get_bd_pins axi_mem_aux_interconnect/M00_ARESETN] $sys_mem_resetn_source
connect_bd_net -net sys_mem_clk [get_bd_pins axi_mem_aux_interconnect/M00_ACLK] $sys_mem_clk_source
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_aux_interconnect/S00_ARESETN] $sys_resetn_source
connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_aux_interconnect/S00_ACLK] $sys_200m_clk_source
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_aux_interconnect/S01_ARESETN] $sys_resetn_source
connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_aux_interconnect/S01_ACLK] $sys_200m_clk_source
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/M00_ARESETN] $sys_resetn_source
connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/M00_ACLK] $sys_200m_clk_source
connect_bd_intf_net -intf_net axi_mem_interconnect_s00 [get_bd_intf_pins axi_mem_interconnect/S00_AXI] [get_bd_intf_pins sys_mb/M_AXI_DC]
connect_bd_intf_net -intf_net axi_mem_interconnect_s01 [get_bd_intf_pins axi_mem_interconnect/S01_AXI] [get_bd_intf_pins sys_mb/M_AXI_IC]
connect_bd_intf_net -intf_net axi_mem_interconnect_s05 [get_bd_intf_pins axi_mem_interconnect/S05_AXI] [get_bd_intf_pins axi_ethernet_dma/M_AXI_SG]
connect_bd_intf_net -intf_net axi_mem_interconnect_s06 [get_bd_intf_pins axi_mem_interconnect/S06_AXI] [get_bd_intf_pins axi_ethernet_dma/M_AXI_MM2S]
connect_bd_intf_net -intf_net axi_mem_interconnect_s07 [get_bd_intf_pins axi_mem_interconnect/S07_AXI] [get_bd_intf_pins axi_ethernet_dma/M_AXI_S2MM]
connect_bd_net -net sys_mem_rstn [get_bd_pins axi_mem_interconnect/M00_ARESETN] $sys_mem_resetn_source
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S00_ARESETN] $sys_resetn_source
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S01_ARESETN] $sys_resetn_source
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S05_ARESETN] $sys_resetn_source
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S06_ARESETN] $sys_resetn_source
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S07_ARESETN] $sys_resetn_source
connect_bd_net -net sys_mem_clk [get_bd_pins axi_mem_interconnect/M00_ACLK] $sys_mem_clk_source
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S00_ACLK] $sys_cpu_clk_source
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S01_ACLK] $sys_cpu_clk_source
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S05_ACLK] $sys_cpu_clk_source

28
projects/daq2/kcu105/system_bd.tcl
View File

@ -161,8 +161,9 @@ if {$sys_zynq == 0} {
if {$sys_zynq == 0} {
set_property -dict [list CONFIG.NUM_SI {11}] $axi_mem_interconnect
set_property -dict [list CONFIG.S09_HAS_REGSLICE {4}] $axi_mem_interconnect
set_property -dict [list CONFIG.S10_HAS_REGSLICE {4}] $axi_mem_interconnect
# set_property -dict [list CONFIG.S08_HAS_REGSLICE {4}] $axi_mem_interconnect
# set_property -dict [list CONFIG.S09_HAS_REGSLICE {4}] $axi_mem_interconnect
# set_property -dict [list CONFIG.S10_HAS_REGSLICE {4}] $axi_mem_interconnect
set_property -dict [list CONFIG.NUM_PORTS {7}] $sys_concat_intc
}
@ -419,14 +420,14 @@ if {$sys_zynq == 1} {
if {$sys_zynq == 0} {
connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9144_dma/m_src_axi]
connect_bd_net -net sys_mem_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_mem_clk_source
connect_bd_net -net sys_mem_clk [get_bd_pins axi_ad9144_dma/m_src_axi_aclk]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_200m_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9144_dma/m_src_axi_aclk]
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_resetn_source
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_ad9144_dma/m_src_axi_aresetn]
connect_bd_intf_net -intf_net axi_mem_interconnect_s10_axi [get_bd_intf_pins axi_mem_interconnect/S10_AXI] [get_bd_intf_pins axi_ad9680_dma/m_dest_axi]
connect_bd_net -net sys_mem_clk [get_bd_pins axi_mem_interconnect/S10_ACLK] $sys_mem_clk_source
connect_bd_net -net sys_mem_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S10_ACLK] $sys_200m_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk]
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S10_ARESETN] $sys_resetn_source
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn]
@ -459,6 +460,10 @@ if {$sys_zynq == 0} {
# ila
set ila_gt_enabled 0
if {$ila_gt_enabled == 1} {
set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_rx_mon]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_jesd_rx_mon
@ -487,6 +492,17 @@ if {$sys_zynq == 0} {
connect_bd_net -net axi_daq2_gt_tx_mon_data [get_bd_pins ila_jesd_tx_mon/PROBE0]
connect_bd_net -net axi_daq2_gt_tx_mon_trigger [get_bd_pins ila_jesd_tx_mon/PROBE1]
} else {
set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_rx_mon]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_NUM_OF_PROBES {1}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE0_WIDTH {128}] $ila_jesd_rx_mon
connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK]
connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE0]
}
# address map
create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_core/s_axi/axi_lite] SEG_data_ad9144_core