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added adc/dac gpio registers

main
Rejeesh Kutty 2014-06-27 14:45:58 -04:00
parent ba7955c531
commit b6052773b7
12 changed files with 87 additions and 8 deletions
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2
library/axi_ad9250/axi_ad9250.v
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@ -278,6 +278,8 @@ module axi_ad9250 (
.drp_locked (1'd1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd1),
.up_adc_gpio_in (32'd0),
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),

4
library/axi_ad9250/axi_ad9250_alt.v
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@ -163,8 +163,8 @@ module axi_ad9250_alt (
// defaults
assign s_axi_bid = 'd0;
assign s_axi_rid = 'd0;
assign s_axi_bid = s_axi_awid;
assign s_axi_rid = s_axi_arid;
assign s_axi_rlast = 1'd0;
// ad9250 lite version

18
library/axi_ad9361/axi_ad9361.v
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@ -127,6 +127,13 @@ module axi_ad9361 (
s_axi_rresp,
s_axi_rready,
// gpio
up_dac_gpio_in,
up_dac_gpio_out,
up_adc_gpio_in,
up_adc_gpio_out,
// chipscope signals
dev_dbg_data,
@ -229,6 +236,13 @@ module axi_ad9361 (
output [ 1:0] s_axi_rresp;
input s_axi_rready;
// gpio
input [31:0] up_dac_gpio_in;
output [31:0] up_dac_gpio_out;
input [31:0] up_adc_gpio_in;
output [31:0] up_adc_gpio_out;
// chipscope signals
output [111:0] dev_dbg_data;
@ -361,6 +375,8 @@ module axi_ad9361 (
.adc_data_q1 (adc_data_q1),
.adc_dovf (adc_dovf),
.adc_dunf (adc_dunf),
.up_adc_gpio_in (up_adc_gpio_in),
.up_adc_gpio_out (up_adc_gpio_out),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
@ -397,6 +413,8 @@ module axi_ad9361 (
.dac_data_q1 (dac_data_q1),
.dac_dovf(dac_dovf),
.dac_dunf(dac_dunf),
.up_dac_gpio_in (up_dac_gpio_in),
.up_dac_gpio_out (up_dac_gpio_out),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),

8
library/axi_ad9361/axi_ad9361_alt.v
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@ -265,8 +265,8 @@ module axi_ad9361_alt (
// defaults
assign s_axi_bid = 'd0;
assign s_axi_rid = 'd0;
assign s_axi_bid = s_axi_awid;
assign s_axi_rid = s_axi_arid;
assign s_axi_rlast = 1'd0;
// ad9361 lite version
@ -343,6 +343,10 @@ module axi_ad9361_alt (
.s_axi_rresp (s_axi_rresp),
.s_axi_rdata (s_axi_rdata),
.s_axi_rready (s_axi_rready),
.up_dac_gpio_in (32'd0),
.up_dac_gpio_out (),
.up_adc_gpio_in (32'd0),
.up_adc_gpio_out (),
.dev_dbg_data (dev_dbg_data),
.dev_l_dbg_data (dev_l_dbg_data));

12
library/axi_ad9361/axi_ad9361_rx.v
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@ -80,6 +80,11 @@ module axi_ad9361_rx (
adc_dovf,
adc_dunf,
// gpio
up_adc_gpio_in,
up_adc_gpio_out,
// processor interface
up_rstn,
@ -134,6 +139,11 @@ module axi_ad9361_rx (
input adc_dovf;
input adc_dunf;
// gpio
input [31:0] up_adc_gpio_in;
output [31:0] up_adc_gpio_out;
// processor interface
input up_rstn;
@ -347,6 +357,8 @@ module axi_ad9361_rx (
.drp_locked (1'd1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd3),
.up_adc_gpio_in (up_adc_gpio_in),
.up_adc_gpio_out (up_adc_gpio_out),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),

12
library/axi_ad9361/axi_ad9361_tx.v
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@ -71,6 +71,11 @@ module axi_ad9361_tx (
dac_dovf,
dac_dunf,
// gpio
up_dac_gpio_in,
up_dac_gpio_out,
// processor interface
up_rstn,
@ -117,6 +122,11 @@ module axi_ad9361_tx (
input dac_dovf;
input dac_dunf;
// gpio
input [31:0] up_dac_gpio_in;
output [31:0] up_dac_gpio_out;
// processor interface
input up_rstn;
@ -329,6 +339,8 @@ module axi_ad9361_tx (
.drp_locked (1'd1),
.up_usr_chanmax (),
.dac_usr_chanmax (8'd3),
.up_dac_gpio_in (up_dac_gpio_in),
.up_dac_gpio_out (up_dac_gpio_out),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),

10
library/axi_ad9361/axi_ad9361_tx_channel.v
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@ -119,6 +119,8 @@ module axi_ad9361_tx_channel (
reg [15:0] dac_pat_data = 'd0;
reg [15:0] dac_dds_phase_0 = 'd0;
reg [15:0] dac_dds_phase_1 = 'd0;
reg [15:0] dac_dds_incr_0 = 'd0;
reg [15:0] dac_dds_incr_1 = 'd0;
reg [15:0] dac_dds_data = 'd0;
// internal signals
@ -345,10 +347,14 @@ module axi_ad9361_tx_channel (
if (dac_data_sync == 1'b1) begin
dac_dds_phase_0 <= dac_dds_init_1_s;
dac_dds_phase_1 <= dac_dds_init_2_s;
dac_dds_incr_0 <= dac_dds_incr_1_s;
dac_dds_incr_1 <= dac_dds_incr_2_s;
dac_dds_data <= 16'd0;
end else if (dac_valid == 1'b1) begin
dac_dds_phase_0 <= dac_dds_phase_0 + dac_dds_incr_1_s;
dac_dds_phase_1 <= dac_dds_phase_1 + dac_dds_incr_2_s;
dac_dds_phase_0 <= dac_dds_phase_0 + dac_dds_incr_0;
dac_dds_phase_1 <= dac_dds_phase_1 + dac_dds_incr_1;
dac_dds_incr_0 <= dac_dds_incr_0;
dac_dds_incr_1 <= dac_dds_incr_1;
dac_dds_data <= dac_dds_data_s;
end
end

4
library/axi_hdmi_tx/axi_hdmi_tx_alt.v
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@ -207,8 +207,8 @@ module axi_hdmi_tx_alt (
// defaults
assign s_axi_bid = 'd0;
assign s_axi_rid = 'd0;
assign s_axi_bid = s_axi_awid;
assign s_axi_rid = s_axi_arid;
assign s_axi_rlast = 1'd0;
// hdmi tx lite version

2
library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl
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@ -122,6 +122,7 @@ add_interface_port hdmi_clock hdmi_clk clk Input 1
add_interface hdmi_if conduit end
set_interface_property hdmi_if associatedClock hdmi_clock
set_interface_property hdmi_if associatedReset s_axi_reset
add_interface_port hdmi_if hdmi_out_clk h_clk Output 1
add_interface_port hdmi_if hdmi_16_hsync h16_hsync Output 1
add_interface_port hdmi_if hdmi_16_vsync h16_vsync Output 1
@ -144,6 +145,7 @@ add_interface_port vdma_clock vdma_clk clk Input 1
add_interface vdma_if avalon_streaming end
set_interface_property vdma_if associatedClock vdma_clock
set_interface_property vdma_if associatedReset s_axi_reset
add_interface_port vdma_if vdma_valid valid Input 1
add_interface_port vdma_if vdma_data data Input 64
add_interface_port vdma_if vdma_ready ready Output 1

11
library/common/up_adc_common.v
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@ -91,6 +91,8 @@ module up_adc_common (
up_usr_chanmax,
adc_usr_chanmax,
up_adc_gpio_in,
up_adc_gpio_out,
// bus interface
@ -158,6 +160,8 @@ module up_adc_common (
output [ 7:0] up_usr_chanmax;
input [ 7:0] adc_usr_chanmax;
input [31:0] up_adc_gpio_in;
output [31:0] up_adc_gpio_out;
// bus interface
@ -189,6 +193,7 @@ module up_adc_common (
reg up_status_ovf = 'd0;
reg up_status_unf = 'd0;
reg [ 7:0] up_usr_chanmax = 'd0;
reg [31:0] up_adc_gpio_out = 'd0;
reg up_ack = 'd0;
reg [31:0] up_rdata = 'd0;
@ -235,6 +240,7 @@ module up_adc_common (
up_status_ovf <= 'd0;
up_status_unf <= 'd0;
up_usr_chanmax <= 'd0;
up_adc_gpio_out <= 'd0;
end else begin
if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
@ -273,6 +279,9 @@ module up_adc_common (
if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h28)) begin
up_usr_chanmax <= up_wdata[7:0];
end
if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h2f)) begin
up_adc_gpio_out <= up_wdata;
end
end
end
@ -301,6 +310,8 @@ module up_adc_common (
8'h22: up_rdata <= {29'd0, up_status_ovf, up_status_unf, 1'b0};
8'h23: up_rdata <= 32'd8;
8'h28: up_rdata <= {24'd0, adc_usr_chanmax};
8'h2e: up_rdata <= up_adc_gpio_in;
8'h2f: up_rdata <= up_adc_gpio_out;
default: up_rdata <= 0;
endcase
end else begin

11
library/common/up_dac_common.v
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@ -77,6 +77,8 @@ module up_dac_common (
up_usr_chanmax,
dac_usr_chanmax,
up_dac_gpio_in,
up_dac_gpio_out,
// bus interface
@ -130,6 +132,8 @@ module up_dac_common (
output [ 7:0] up_usr_chanmax;
input [ 7:0] dac_usr_chanmax;
input [31:0] up_dac_gpio_in;
output [31:0] up_dac_gpio_out;
// bus interface
@ -161,6 +165,7 @@ module up_dac_common (
reg up_status_ovf = 'd0;
reg up_status_unf = 'd0;
reg [ 7:0] up_usr_chanmax = 'd0;
reg [31:0] up_dac_gpio_out = 'd0;
reg up_ack = 'd0;
reg [31:0] up_rdata = 'd0;
reg dac_sync_d = 'd0;
@ -216,6 +221,7 @@ module up_dac_common (
up_status_ovf <= 'd0;
up_status_ovf <= 'd0;
up_usr_chanmax <= 'd0;
up_dac_gpio_out <= 'd0;
end else begin
if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
@ -266,6 +272,9 @@ module up_dac_common (
if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h28)) begin
up_usr_chanmax <= up_wdata[7:0];
end
if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h2f)) begin
up_dac_gpio_out <= up_wdata;
end
end
end
@ -295,6 +304,8 @@ module up_dac_common (
8'h1d: up_rdata <= {14'd0, up_drp_locked_s, up_drp_status_s, up_drp_rdata_s};
8'h22: up_rdata <= {30'd0, up_status_ovf, up_status_unf};
8'h28: up_rdata <= {24'd0, dac_usr_chanmax};
8'h2e: up_rdata <= up_dac_gpio_in;
8'h2f: up_rdata <= up_dac_gpio_out;
default: up_rdata <= 0;
endcase
end else begin

1
library/common/up_hdmi_tx.v
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@ -317,6 +317,7 @@ module up_hdmi_tx (
up_vs_width,
up_ve_max,
up_ve_min}),
.up_xfer_done (),
.d_rst (hdmi_rst),
.d_clk (hdmi_clk),
.d_data_cntrl ({ hdmi_full_range,