diff --git a/projects/cn0506_rmii/zc706/Makefile b/projects/cn0506_rmii/zc706/Makefile
index da5d3c9f7..f5385e716 100644
--- a/projects/cn0506_rmii/zc706/Makefile
+++ b/projects/cn0506_rmii/zc706/Makefile
@@ -17,5 +17,6 @@ LIB_DEPS += axi_hdmi_tx
 LIB_DEPS += axi_spdif_tx
 LIB_DEPS += axi_sysid
 LIB_DEPS += sysid_rom
+LIB_DEPS += util_mii_to_rmii
 
 include ../../scripts/project-xilinx.mk
diff --git a/projects/cn0506_rmii/zc706/system_bd.tcl b/projects/cn0506_rmii/zc706/system_bd.tcl
index 2eca13ce0..4134e5b54 100644
--- a/projects/cn0506_rmii/zc706/system_bd.tcl
+++ b/projects/cn0506_rmii/zc706/system_bd.tcl
@@ -19,37 +19,35 @@ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:rmii_rtl:1.0 RMII_PH
 make_bd_intf_pins_external  [get_bd_intf_pins sys_ps7/MDIO_ETHERNET_0]
 make_bd_intf_pins_external  [get_bd_intf_pins sys_ps7/MDIO_ETHERNET_1]
 
-ad_ip_instance mii_to_rmii mii_to_rmii_0
-ad_ip_parameter mii_to_rmii_0 CONFIG.C_MODE 1
-ad_ip_parameter mii_to_rmii_0 CONFIG.C_SPEED_100 1
-ad_ip_parameter mii_to_rmii_0 CONFIG.C_FIXED_SPEED 0
+ad_ip_instance util_mii_to_rmii mii_to_rmii_0
+ad_ip_parameter mii_to_rmii_0 CONFIG.INTF_CFG 1
+ad_ip_parameter mii_to_rmii_0 CONFIG.RATE_10_100 0
 
 ad_connect mii_to_rmii_0/GMII    sys_ps7/GMII_ETHERNET_0
 ad_connect mii_to_rmii_0/ref_clk ref_clk_50_a
 
-ad_connect mii_to_rmii_0/RMII_PHY_M RMII_PHY_M_0
+ad_connect mii_to_rmii_0/RMII RMII_PHY_M_0
 
-ad_ip_instance mii_to_rmii mii_to_rmii_1
-ad_ip_parameter mii_to_rmii_1 CONFIG.C_MODE 1
-ad_ip_parameter mii_to_rmii_1 CONFIG.C_SPEED_100 1
-ad_ip_parameter mii_to_rmii_1 CONFIG.C_FIXED_SPEED 0
+ad_ip_instance util_mii_to_rmii mii_to_rmii_1
+ad_ip_parameter mii_to_rmii_1 CONFIG.INTF_CFG 1
+ad_ip_parameter mii_to_rmii_1 CONFIG.RATE_10_100 0
 
 ad_connect mii_to_rmii_1/GMII    sys_ps7/GMII_ETHERNET_1
 ad_connect mii_to_rmii_1/ref_clk ref_clk_50_b
 
-ad_connect mii_to_rmii_1/RMII_PHY_M RMII_PHY_M_1
+ad_connect mii_to_rmii_1/RMII RMII_PHY_M_1
 
 ad_ip_instance proc_sys_reset proc_sys_reset_eth0
 ad_connect proc_sys_reset_eth0/slowest_sync_clk  ref_clk_50_a
 ad_connect proc_sys_reset_eth0/ext_reset_in  sys_rstgen/peripheral_aresetn
 ad_connect proc_sys_reset_eth0/peripheral_reset  reset_a
-ad_connect proc_sys_reset_eth0/peripheral_aresetn  mii_to_rmii_0/rst_n
+ad_connect proc_sys_reset_eth0/peripheral_aresetn  mii_to_rmii_0/reset_n
 
 ad_ip_instance proc_sys_reset proc_sys_reset_eth1
 ad_connect proc_sys_reset_eth1/slowest_sync_clk  ref_clk_50_b
 ad_connect proc_sys_reset_eth1/ext_reset_in  sys_rstgen/peripheral_aresetn
 ad_connect proc_sys_reset_eth1/peripheral_reset  reset_b
-ad_connect proc_sys_reset_eth1/peripheral_aresetn  mii_to_rmii_1/rst_n
+ad_connect proc_sys_reset_eth1/peripheral_aresetn  mii_to_rmii_1/reset_n
 
 source $ad_hdl_dir/projects/scripts/adi_pd.tcl
 
diff --git a/projects/cn0506_rmii/zc706/system_constr.xdc b/projects/cn0506_rmii/zc706/system_constr.xdc
index 2c078d60a..db2b73ca9 100644
--- a/projects/cn0506_rmii/zc706/system_constr.xdc
+++ b/projects/cn0506_rmii/zc706/system_constr.xdc
@@ -44,8 +44,8 @@ set_property -dict {PACKAGE_PIN AE17  IOSTANDARD LVCMOS25} [get_ports led_br_a_c
 create_clock -name rmii_ref_clk_a  -period 20.0 [get_ports rmii_rx_ref_clk_a]
 create_clock -name rmii_ref_clk_b  -period 20.0 [get_ports rmii_rx_ref_clk_b]
 
-create_clock -name rmii_rx_clk_0   -period  20 [get_pins i_system_wrapper/system_i/mii_to_rmii_0/U0/rmii2mac_rx_clk_bi_reg/Q]
-create_clock -name rmii_rx_clk_1   -period  20 [get_pins i_system_wrapper/system_i/mii_to_rmii_1/U0/rmii2mac_rx_clk_bi_reg/Q]
-create_clock -name rmii_tx_clk_0   -period  20 [get_pins i_system_wrapper/system_i/mii_to_rmii_0/U0/rmii2mac_tx_clk_bi_reg/Q]
-create_clock -name rmii_tx_clk_1   -period  20 [get_pins i_system_wrapper/system_i/mii_to_rmii_1/U0/rmii2mac_tx_clk_bi_reg/Q]
+create_clock -name rmii_rx_clk_0   -period  20 [get_pins i_system_wrapper/system_i/mii_to_rmii_0/inst/mii_rx_clk_r1_reg/Q]
+create_clock -name rmii_rx_clk_1   -period  20 [get_pins i_system_wrapper/system_i/mii_to_rmii_1/inst/mii_rx_clk_r1_reg/Q]
+create_clock -name rmii_tx_clk_0   -period  20 [get_pins i_system_wrapper/system_i/mii_to_rmii_0/inst/mii_tx_clk_r1_reg/Q]
+create_clock -name rmii_tx_clk_1   -period  20 [get_pins i_system_wrapper/system_i/mii_to_rmii_1/inst/mii_tx_clk_r1_reg/Q]
 
diff --git a/projects/cn0506_rmii/zcu102/Makefile b/projects/cn0506_rmii/zcu102/Makefile
index d3f03c971..e5aba97e0 100644
--- a/projects/cn0506_rmii/zcu102/Makefile
+++ b/projects/cn0506_rmii/zcu102/Makefile
@@ -12,5 +12,6 @@ M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
 
 LIB_DEPS += axi_sysid
 LIB_DEPS += sysid_rom
+LIB_DEPS += util_mii_to_rmii
 
 include ../../scripts/project-xilinx.mk
diff --git a/projects/cn0506_rmii/zcu102/system_bd.tcl b/projects/cn0506_rmii/zcu102/system_bd.tcl
index c09ee85c2..30c51a6b1 100644
--- a/projects/cn0506_rmii/zcu102/system_bd.tcl
+++ b/projects/cn0506_rmii/zcu102/system_bd.tcl
@@ -24,37 +24,35 @@ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:rmii_rtl:1.0 RMII_PH
 make_bd_intf_pins_external  [get_bd_intf_pins sys_ps8/MDIO_ENET0]
 make_bd_intf_pins_external  [get_bd_intf_pins sys_ps8/MDIO_ENET1]
 
-ad_ip_instance mii_to_rmii mii_to_rmii_0
-ad_ip_parameter mii_to_rmii_0 CONFIG.C_MODE 1
-ad_ip_parameter mii_to_rmii_0 CONFIG.C_SPEED_100 1
-ad_ip_parameter mii_to_rmii_0 CONFIG.C_FIXED_SPEED 0
+ad_ip_instance util_mii_to_rmii mii_to_rmii_0
+ad_ip_parameter mii_to_rmii_0 CONFIG.INTF_CFG 1
+ad_ip_parameter mii_to_rmii_0 CONFIG.RATE_10_100 0
 
 ad_connect mii_to_rmii_0/GMII    sys_ps8/GMII_ENET0
 ad_connect mii_to_rmii_0/ref_clk ref_clk_50_a
 
-ad_connect mii_to_rmii_0/RMII_PHY_M RMII_PHY_M_0
+ad_connect mii_to_rmii_0/RMII RMII_PHY_M_0
 
-ad_ip_instance mii_to_rmii mii_to_rmii_1
-ad_ip_parameter mii_to_rmii_1 CONFIG.C_MODE 1
-ad_ip_parameter mii_to_rmii_1 CONFIG.C_SPEED_100 1
-ad_ip_parameter mii_to_rmii_1 CONFIG.C_FIXED_SPEED 0
+ad_ip_instance util_mii_to_rmii mii_to_rmii_1
+ad_ip_parameter mii_to_rmii_1 CONFIG.INTF_CFG 1
+ad_ip_parameter mii_to_rmii_1 CONFIG.RATE_10_100 0
 
 ad_connect mii_to_rmii_1/GMII    sys_ps8/GMII_ENET1
 ad_connect mii_to_rmii_1/ref_clk ref_clk_50_b
 
-ad_connect mii_to_rmii_1/RMII_PHY_M RMII_PHY_M_1
+ad_connect mii_to_rmii_1/RMII RMII_PHY_M_1
 
 ad_ip_instance proc_sys_reset proc_sys_reset_eth0
 ad_connect proc_sys_reset_eth0/slowest_sync_clk  ref_clk_50_a
 ad_connect proc_sys_reset_eth0/ext_reset_in  sys_rstgen/peripheral_aresetn
 ad_connect proc_sys_reset_eth0/peripheral_reset  reset_a
-ad_connect proc_sys_reset_eth0/peripheral_aresetn  mii_to_rmii_0/rst_n
+ad_connect proc_sys_reset_eth0/peripheral_aresetn  mii_to_rmii_0/reset_n
 
 ad_ip_instance proc_sys_reset proc_sys_reset_eth1
 ad_connect proc_sys_reset_eth1/slowest_sync_clk  ref_clk_50_b
 ad_connect proc_sys_reset_eth1/ext_reset_in  sys_rstgen/peripheral_aresetn
 ad_connect proc_sys_reset_eth1/peripheral_reset  reset_b
-ad_connect proc_sys_reset_eth1/peripheral_aresetn  mii_to_rmii_1/rst_n
+ad_connect proc_sys_reset_eth1/peripheral_aresetn  mii_to_rmii_1/reset_n
 
 source $ad_hdl_dir/projects/scripts/adi_pd.tcl
 
diff --git a/projects/cn0506_rmii/zed/Makefile b/projects/cn0506_rmii/zed/Makefile
index fea9b478e..102357290 100644
--- a/projects/cn0506_rmii/zed/Makefile
+++ b/projects/cn0506_rmii/zed/Makefile
@@ -19,5 +19,6 @@ LIB_DEPS += axi_spdif_tx
 LIB_DEPS += axi_sysid
 LIB_DEPS += sysid_rom
 LIB_DEPS += util_i2c_mixer
+LIB_DEPS += util_mii_to_rmii
 
 include ../../scripts/project-xilinx.mk
diff --git a/projects/cn0506_rmii/zed/system_bd.tcl b/projects/cn0506_rmii/zed/system_bd.tcl
index 76bd30765..de0637f90 100644
--- a/projects/cn0506_rmii/zed/system_bd.tcl
+++ b/projects/cn0506_rmii/zed/system_bd.tcl
@@ -18,37 +18,35 @@ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:rmii_rtl:1.0 RMII_PH
 make_bd_intf_pins_external  [get_bd_intf_pins sys_ps7/MDIO_ETHERNET_0]
 make_bd_intf_pins_external  [get_bd_intf_pins sys_ps7/MDIO_ETHERNET_1]
 
-ad_ip_instance mii_to_rmii mii_to_rmii_0
-ad_ip_parameter mii_to_rmii_0 CONFIG.C_MODE 1
-ad_ip_parameter mii_to_rmii_0 CONFIG.C_SPEED_100 1
-ad_ip_parameter mii_to_rmii_0 CONFIG.C_FIXED_SPEED 0
+ad_ip_instance util_mii_to_rmii mii_to_rmii_0
+ad_ip_parameter mii_to_rmii_0 CONFIG.INTF_CFG 1
+ad_ip_parameter mii_to_rmii_0 CONFIG.RATE_10_100 0
 
 ad_connect mii_to_rmii_0/GMII    sys_ps7/GMII_ETHERNET_0
 ad_connect mii_to_rmii_0/ref_clk ref_clk_50_a
 
-ad_connect mii_to_rmii_0/RMII_PHY_M RMII_PHY_M_0
+ad_connect mii_to_rmii_0/RMII RMII_PHY_M_0
 
-ad_ip_instance mii_to_rmii mii_to_rmii_1
-ad_ip_parameter mii_to_rmii_1 CONFIG.C_MODE 1
-ad_ip_parameter mii_to_rmii_1 CONFIG.C_SPEED_100 1
-ad_ip_parameter mii_to_rmii_1 CONFIG.C_FIXED_SPEED 0
+ad_ip_instance util_mii_to_rmii mii_to_rmii_1
+ad_ip_parameter mii_to_rmii_1 CONFIG.INTF_CFG 1
+ad_ip_parameter mii_to_rmii_1 CONFIG.RATE_10_100 0
 
 ad_connect mii_to_rmii_1/GMII    sys_ps7/GMII_ETHERNET_1
 ad_connect mii_to_rmii_1/ref_clk ref_clk_50_b
 
-ad_connect mii_to_rmii_1/RMII_PHY_M RMII_PHY_M_1
+ad_connect mii_to_rmii_1/RMII RMII_PHY_M_1
 
 ad_ip_instance proc_sys_reset proc_sys_reset_eth0
 ad_connect proc_sys_reset_eth0/slowest_sync_clk  ref_clk_50_a
 ad_connect proc_sys_reset_eth0/ext_reset_in  sys_rstgen/peripheral_aresetn
 ad_connect proc_sys_reset_eth0/peripheral_reset  reset_a
-ad_connect proc_sys_reset_eth0/peripheral_aresetn  mii_to_rmii_0/rst_n
+ad_connect proc_sys_reset_eth0/peripheral_aresetn  mii_to_rmii_0/reset_n
 
 ad_ip_instance proc_sys_reset proc_sys_reset_eth1
 ad_connect proc_sys_reset_eth1/slowest_sync_clk  ref_clk_50_b
 ad_connect proc_sys_reset_eth1/ext_reset_in  sys_rstgen/peripheral_aresetn
 ad_connect proc_sys_reset_eth1/peripheral_reset  reset_b
-ad_connect proc_sys_reset_eth1/peripheral_aresetn  mii_to_rmii_1/rst_n
+ad_connect proc_sys_reset_eth1/peripheral_aresetn  mii_to_rmii_1/reset_n
 
 source $ad_hdl_dir/projects/scripts/adi_pd.tcl
 
diff --git a/projects/cn0506_rmii/zed/system_constr.xdc b/projects/cn0506_rmii/zed/system_constr.xdc
index cd724b4f1..30edc75df 100644
--- a/projects/cn0506_rmii/zed/system_constr.xdc
+++ b/projects/cn0506_rmii/zed/system_constr.xdc
@@ -44,8 +44,8 @@ set_property -dict {PACKAGE_PIN K21  IOSTANDARD LVCMOS25} [get_ports led_br_a_c2
 create_clock -name rmii_ref_clk_a  -period 20.0 [get_ports rmii_rx_ref_clk_a]
 create_clock -name rmii_ref_clk_b  -period 20.0 [get_ports rmii_rx_ref_clk_b]
 
-create_clock -name rmii_rx_clk_0   -period  20 [get_pins i_system_wrapper/system_i/mii_to_rmii_0/U0/rmii2mac_rx_clk_bi_reg/Q]
-create_clock -name rmii_rx_clk_1   -period  20 [get_pins i_system_wrapper/system_i/mii_to_rmii_1/U0/rmii2mac_rx_clk_bi_reg/Q]
-create_clock -name rmii_tx_clk_0   -period  20 [get_pins i_system_wrapper/system_i/mii_to_rmii_0/U0/rmii2mac_tx_clk_bi_reg/Q]
-create_clock -name rmii_tx_clk_1   -period  20 [get_pins i_system_wrapper/system_i/mii_to_rmii_1/U0/rmii2mac_tx_clk_bi_reg/Q]
+create_clock -name rmii_rx_clk_0   -period  20 [get_pins i_system_wrapper/system_i/mii_to_rmii_0/inst/mii_rx_clk_r1_reg/Q]
+create_clock -name rmii_rx_clk_1   -period  20 [get_pins i_system_wrapper/system_i/mii_to_rmii_1/inst/mii_rx_clk_r1_reg/Q]
+create_clock -name rmii_tx_clk_0   -period  20 [get_pins i_system_wrapper/system_i/mii_to_rmii_0/inst/mii_tx_clk_r1_reg/Q]
+create_clock -name rmii_tx_clk_1   -period  20 [get_pins i_system_wrapper/system_i/mii_to_rmii_1/inst/mii_tx_clk_r1_reg/Q]