library/xilinx- lvds/cmos integration
Rejeesh Kutty
parent
eb113c8698
commit
b65802ee1e
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@ -0,0 +1,95 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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||||
// of this file, are permitted under one of the following two license terms:
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||||
//
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||||
// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_data_clk #(
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parameter SINGLE_ENDED = 0,
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parameter DEVICE_TYPE = 0) (
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input rst,
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output locked,
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input clk_in_p,
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input clk_in_n,
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output clk);
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localparam VIRTEX7 = 0;
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localparam VIRTEX6 = 1;
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localparam ULTRASCALE_PLUS = 2;
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localparam ULTRASCALE = 3;
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// internal signals
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wire clk_ibuf_s;
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// defaults
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assign locked = 1'b1;
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// instantiations
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generate
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if (SINGLE_ENDED == 1) begin
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IBUFG i_rx_clk_ibuf (
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.I (clk_in_p),
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.O (clk_ibuf_s));
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end else begin
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IBUFGDS i_rx_clk_ibuf (
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.I (clk_in_p),
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.IB (clk_in_n),
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.O (clk_ibuf_s));
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end
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endgenerate
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generate
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if (DEVICE_TYPE == VIRTEX6) begin
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BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_rbuf (
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.CLR (1'b0),
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.CE (1'b1),
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.I (clk_ibuf_s),
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.O (clk));
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end else begin
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BUFG i_clk_gbuf (
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.I (clk_ibuf_s),
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.O (clk));
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end
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endgenerate
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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@ -0,0 +1,246 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
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||||
//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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||||
//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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||||
// of this file, are permitted under one of the following two license terms:
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||||
//
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||||
// 1. The GNU General Public License version 2 as published by the
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||||
// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
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||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_data_in #(
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// parameters
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parameter SINGLE_ENDED = 0,
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parameter DEVICE_TYPE = 0,
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parameter IODELAY_ENABLE = 1,
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parameter IODELAY_CTRL = 0,
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parameter IODELAY_GROUP = "dev_if_delay_group") (
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// data interface
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input rx_clk,
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input rx_data_in_p,
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input rx_data_in_n,
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output rx_data_p,
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output rx_data_n,
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// delay-data interface
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input up_clk,
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input up_dld,
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input [ 4:0] up_dwdata,
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output [ 4:0] up_drdata,
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// delay-cntrl interface
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input delay_clk,
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input delay_rst,
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output delay_locked);
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// internal parameters
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localparam NONE = -1;
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localparam VIRTEX7 = 0;
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localparam VIRTEX6 = 1;
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localparam ULTRASCALE_PLUS = 2;
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localparam ULTRASCALE = 3;
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localparam IODELAY_CTRL_ENABLED = (IODELAY_ENABLE == 1) ? IODELAY_CTRL : 0;
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localparam IODELAY_CTRL_SIM_DEVICE = (DEVICE_TYPE == ULTRASCALE_PLUS) ? "ULTRASCALE" :
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(DEVICE_TYPE == ULTRASCALE) ? "ULTRASCALE" :
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(DEVICE_TYPE == VIRTEX7) ? "7SERIES" : "VIRTEX6";
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localparam IODELAY_DEVICE_TYPE = (IODELAY_ENABLE == 1) ? DEVICE_TYPE : NONE;
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localparam IODELAY_SIM_DEVICE = (DEVICE_TYPE == ULTRASCALE_PLUS) ? "ULTRASCALE_PLUS_ES1" :
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(DEVICE_TYPE == ULTRASCALE) ? "ULTRASCALE" :
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(DEVICE_TYPE == VIRTEX7) ? "7SERIES" : "VIRTEX6";
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// internal signals
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wire rx_data_ibuf_s;
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wire rx_data_idelay_s;
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wire [ 8:0] up_drdata_s;
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// delay controller
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generate
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if (IODELAY_CTRL_ENABLED == 0) begin
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assign delay_locked = 1'b1;
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end else begin
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IDELAYCTRL #(.SIM_DEVICE (IODELAY_CTRL_SIM_DEVICE)) i_delay_ctrl (
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.RST (delay_rst),
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.REFCLK (delay_clk),
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.RDY (delay_locked));
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end
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endgenerate
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// receive data interface, ibuf -> idelay -> iddr
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generate
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if (SINGLE_ENDED == 1) begin
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IBUF i_rx_data_ibuf (
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.I (rx_data_in_p),
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.O (rx_data_ibuf_s));
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end else begin
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IBUFDS i_rx_data_ibuf (
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.I (rx_data_in_p),
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.IB (rx_data_in_n),
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.O (rx_data_ibuf_s));
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end
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endgenerate
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// idelay
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generate
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if (IODELAY_DEVICE_TYPE == VIRTEX6) begin
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(* IODELAY_GROUP = IODELAY_GROUP *)
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IODELAYE1 #(
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.CINVCTRL_SEL ("FALSE"),
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.DELAY_SRC ("I"),
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.HIGH_PERFORMANCE_MODE ("TRUE"),
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.IDELAY_TYPE ("VAR_LOADABLE"),
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.IDELAY_VALUE (0),
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.ODELAY_TYPE ("FIXED"),
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.ODELAY_VALUE (0),
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.REFCLK_FREQUENCY (200.0),
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.SIGNAL_PATTERN ("DATA"))
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i_rx_data_idelay (
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.T (1'b1),
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.CE (1'b0),
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.INC (1'b0),
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.CLKIN (1'b0),
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.DATAIN (1'b0),
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.ODATAIN (1'b0),
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.CINVCTRL (1'b0),
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.C (up_clk),
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.IDATAIN (rx_data_ibuf_s),
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.DATAOUT (rx_data_idelay_s),
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.RST (up_dld),
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.CNTVALUEIN (up_dwdata),
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.CNTVALUEOUT (up_drdata));
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end
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endgenerate
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generate
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if (IODELAY_DEVICE_TYPE == VIRTEX7) begin
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(* IODELAY_GROUP = IODELAY_GROUP *)
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IDELAYE2 #(
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.CINVCTRL_SEL ("FALSE"),
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.DELAY_SRC ("IDATAIN"),
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.HIGH_PERFORMANCE_MODE ("FALSE"),
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.IDELAY_TYPE ("VAR_LOAD"),
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.IDELAY_VALUE (0),
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.REFCLK_FREQUENCY (200.0),
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.PIPE_SEL ("FALSE"),
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.SIGNAL_PATTERN ("DATA"))
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i_rx_data_idelay (
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.CE (1'b0),
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.INC (1'b0),
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.DATAIN (1'b0),
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.LDPIPEEN (1'b0),
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.CINVCTRL (1'b0),
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.REGRST (1'b0),
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.C (up_clk),
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.IDATAIN (rx_data_ibuf_s),
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.DATAOUT (rx_data_idelay_s),
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.LD (up_dld),
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.CNTVALUEIN (up_dwdata),
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.CNTVALUEOUT (up_drdata));
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end
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endgenerate
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generate
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if ((IODELAY_DEVICE_TYPE == ULTRASCALE) || (IODELAY_DEVICE_TYPE == ULTRASCALE_PLUS)) begin
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assign up_drdata = up_drdata_s[8:4];
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(* IODELAY_GROUP = IODELAY_GROUP *)
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IDELAYE3 #(
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.SIM_DEVICE (IODELAY_SIM_DEVICE),
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.DELAY_SRC ("IDATAIN"),
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.DELAY_TYPE ("VAR_LOAD"),
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.REFCLK_FREQUENCY (200.0),
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.DELAY_FORMAT ("COUNT"))
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i_rx_data_idelay (
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.CASC_RETURN (1'b0),
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.CASC_IN (1'b0),
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.CASC_OUT (),
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.CE (1'b0),
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.CLK (up_clk),
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.INC (1'b0),
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.LOAD (up_dld),
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.CNTVALUEIN ({up_dwdata, 4'd0}),
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.CNTVALUEOUT (up_drdata_s),
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.DATAIN (1'b0),
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.IDATAIN (rx_data_ibuf_s),
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.DATAOUT (rx_data_idelay_s),
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.RST (1'b0),
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.EN_VTC (~up_dld));
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end
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endgenerate
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generate
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if (IODELAY_DEVICE_TYPE == NONE) begin
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assign rx_data_idelay_s = rx_data_ibuf_s;
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assign up_drdata = 5'd0;
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end
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endgenerate
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// iddr
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generate
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if ((DEVICE_TYPE == ULTRASCALE) || (DEVICE_TYPE == ULTRASCALE_PLUS)) begin
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IDDRE1 #(.DDR_CLK_EDGE ("SAME_EDGE")) i_rx_data_iddr (
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.R (1'b0),
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.C (rx_clk),
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.CB (~rx_clk),
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.D (rx_data_idelay_s),
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.Q1 (rx_data_p),
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.Q2 (rx_data_n));
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end
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endgenerate
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generate
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if ((DEVICE_TYPE == VIRTEX7) || (DEVICE_TYPE == VIRTEX6)) begin
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IDDR #(.DDR_CLK_EDGE ("SAME_EDGE")) i_rx_data_iddr (
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.CE (1'b1),
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.R (1'b0),
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.S (1'b0),
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.C (rx_clk),
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.D (rx_data_idelay_s),
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.Q1 (rx_data_p),
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.Q2 (rx_data_n));
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end
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endgenerate
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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@ -0,0 +1,183 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
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// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsabilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
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||||
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`timescale 1ns/100ps
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module ad_data_out #(
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parameter DEVICE_TYPE = 0,
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parameter SINGLE_ENDED = 0,
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parameter IODELAY_ENABLE = 0,
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parameter IODELAY_CTRL = 0,
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parameter IODELAY_GROUP = "dev_if_delay_group") (
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// data interface
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input tx_clk,
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input tx_data_p,
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input tx_data_n,
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output tx_data_out_p,
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output tx_data_out_n,
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// delay-data interface
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input up_clk,
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input up_dld,
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input [ 4:0] up_dwdata,
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output [ 4:0] up_drdata,
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// delay-cntrl interface
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input delay_clk,
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input delay_rst,
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output delay_locked);
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localparam NONE = -1;
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localparam VIRTEX7 = 0;
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localparam VIRTEX6 = 1;
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localparam ULTRASCALE_PLUS = 2;
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localparam ULTRASCALE = 3;
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localparam IODELAY_CTRL_ENABLED = (IODELAY_ENABLE == 1) ? IODELAY_CTRL : 0;
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localparam IODELAY_CTRL_SIM_DEVICE = (DEVICE_TYPE == ULTRASCALE_PLUS) ? "ULTRASCALE" :
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(DEVICE_TYPE == ULTRASCALE) ? "ULTRASCALE" :
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(DEVICE_TYPE == VIRTEX7) ? "7SERIES" : "VIRTEX6";
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localparam IODELAY_DEVICE_TYPE = (IODELAY_ENABLE == 1) ? DEVICE_TYPE : NONE;
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localparam IODELAY_SIM_DEVICE = (DEVICE_TYPE == ULTRASCALE_PLUS) ? "ULTRASCALE_PLUS_ES1" :
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(DEVICE_TYPE == ULTRASCALE) ? "ULTRASCALE" :
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(DEVICE_TYPE == VIRTEX7) ? "7SERIES" : "VIRTEX6";
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// internal signals
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wire tx_data_oddr_s;
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wire tx_data_odelay_s;
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// delay controller
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generate
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if (IODELAY_CTRL_ENABLED == 0) begin
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assign delay_locked = 1'b1;
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end else begin
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IDELAYCTRL #(.SIM_DEVICE (IODELAY_CTRL_SIM_DEVICE)) i_delay_ctrl (
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.RST (delay_rst),
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.REFCLK (delay_clk),
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.RDY (delay_locked));
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end
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endgenerate
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// transmit data interface, oddr -> odelay -> obuf
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generate
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if ((DEVICE_TYPE == ULTRASCALE) || (DEVICE_TYPE == ULTRASCALE_PLUS)) begin
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ODDRE1 i_tx_data_oddr (
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.SR (1'b0),
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.C (tx_clk),
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.D1 (tx_data_n),
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.D2 (tx_data_p),
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.Q (tx_data_oddr_s));
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end
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endgenerate
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generate
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if ((DEVICE_TYPE == VIRTEX7) || (DEVICE_TYPE == VIRTEX6)) begin
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ODDR #(.DDR_CLK_EDGE ("SAME_EDGE")) i_tx_data_oddr (
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.CE (1'b1),
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.R (1'b0),
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.S (1'b0),
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.C (tx_clk),
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.D1 (tx_data_n),
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.D2 (tx_data_p),
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.Q (tx_data_oddr_s));
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end
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endgenerate
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// odelay
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generate
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if (IODELAY_DEVICE_TYPE == VIRTEX7) begin
|
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(* IODELAY_GROUP = IODELAY_GROUP *)
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ODELAYE2 #(
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.CINVCTRL_SEL ("FALSE"),
|
||||
.DELAY_SRC ("ODATAIN"),
|
||||
.HIGH_PERFORMANCE_MODE ("FALSE"),
|
||||
.ODELAY_TYPE ("VAR_LOAD"),
|
||||
.ODELAY_VALUE (0),
|
||||
.REFCLK_FREQUENCY (200.0),
|
||||
.PIPE_SEL ("FALSE"),
|
||||
.SIGNAL_PATTERN ("DATA"))
|
||||
i_tx_data_odelay (
|
||||
.CE (1'b0),
|
||||
.CLKIN (1'b0),
|
||||
.INC (1'b0),
|
||||
.LDPIPEEN (1'b0),
|
||||
.CINVCTRL (1'b0),
|
||||
.REGRST (1'b0),
|
||||
.C (up_clk),
|
||||
.ODATAIN (tx_data_oddr_s),
|
||||
.DATAOUT (tx_data_odelay_s),
|
||||
.LD (up_dld),
|
||||
.CNTVALUEIN (up_dwdata),
|
||||
.CNTVALUEOUT (up_drdata));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (IODELAY_DEVICE_TYPE == NONE) begin
|
||||
assign up_drdata = 5'd0;
|
||||
assign tx_data_odelay_s = tx_data_oddr_s;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// obuf
|
||||
|
||||
generate
|
||||
if (SINGLE_ENDED == 1) begin
|
||||
assign tx_data_out_n = 1'b0;
|
||||
OBUF i_tx_data_obuf (
|
||||
.I (tx_data_odelay_s),
|
||||
.O (tx_data_out_p));
|
||||
end else begin
|
||||
OBUFDS i_tx_data_obuf (
|
||||
.I (tx_data_odelay_s),
|
||||
.O (tx_data_out_p),
|
||||
.OB (tx_data_out_n));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
Loading…
Reference in New Issue