diff --git a/library/axi_ad7175/ad7175_if.v b/library/axi_ad7175/ad7175_if.v new file mode 100644 index 000000000..0d2917e68 --- /dev/null +++ b/library/axi_ad7175/ad7175_if.v @@ -0,0 +1,423 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +//------------------------------------------------------------------------------ +//----------- Module Declaration ----------------------------------------------- +//------------------------------------------------------------------------------ +module ad7175_if + ( + // Clock and Reset signals + input fpga_clk_i, + input adc_clk_i, + input reset_n_i, + + // Conversion control signals + input start_conversion_i, + output [31:0] dma_data_o, + output dma_data_rdy_o, + + // Transmit data on request signals + input start_transmission_i, + input [31:0] tx_data_i, + output tx_data_rdy_o, + + // Read data on request signals + input start_read_i, + output [31:0] rx_data_o, + output rx_data_rdy_o, + + // AD7175 IC control signals + input adc_sdo_i, + output adc_sdi_o, + output adc_cs_o, + output adc_sclk_o, + + // ADC status + output reg adc_status_o + ); + +//------------------------------------------------------------------------------ +//----------- Registers Declarations ------------------------------------------- +//------------------------------------------------------------------------------ +// State Machine Registers +reg [10:0] present_state; // Present FSM State +reg [10:0] next_state; // Next FSM State +reg [10:0] present_state_m1; // Used to synchronise FSM States between different clock domains + +// SCLK Registers +reg [7:0] sclk_cnt; // Used to count SCLK Ticks +reg [7:0] sclk_demand; // Used to set number of SCLK Ticks + +// Transmit Data Registers +reg [47:0] tx_data_reg; // Used to shift data out +reg [47:0] tx_data_reg_switch; // Used to select data that is being sent +reg tx_data_rdy_int; // Used to signal the end of a transmit cycle + +// Receive Data Registers +reg [47:0] rx_data_reg; // Used to shift data in +reg [31:0] rx_read_data_reg; // Used to store read data +reg rx_data_rdy_int; // Used to signal the end of a read cycle + +// Conversion Data Registers +reg [31:0] dma_rx_data_reg; // Used to store conversion result (STATUS_REG[31:24] + DATA_REG[23:0]) +reg dma_rdy_int; // Used to signal the end of a conversion read + +// Internal registers used for external ports +reg adc_sdi_o_int; // Used for adc_sdi_o +reg cs_int; // Used for adc_cs_o + +//------------------------------------------------------------------------------ +//----------- Wires Declarations ----------------------------------------------- +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +//----------- Local Parameters ------------------------------------------------- +//------------------------------------------------------------------------------ +// ADC Controller State Machine States +parameter ADC_IDLE_STATE = 11'b00000000001; // Waits for Start Conversion / Start Transmission / Start Read +parameter ADC_WAIT_FOR_DATA_STATE = 11'b00000000010; // Waits for adc_sdo_i to go low (signals new data is available) +parameter ADC_PREP_READ_RESULT_STATE = 11'b00000000100; // Prepares data to perform Status + Data Register Read +parameter ADC_READ_RESULT_STATE = 11'b00000001000; // Reads Status + Data Register +parameter ADC_READ_RESULT_DONE_STATE = 11'b00000010000; // Signals completion of Status + Data Register Read +parameter ADC_PREP_SEND_DATA_STATE = 11'b00000100000; // Prepares data to perform Data Transmit +parameter ADC_SEND_DATA_STATE = 11'b00001000000; // Transmit Data +parameter ADC_SEND_DATA_DONE_STATE = 11'b00010000000; // Signals completion of Data Transmission +parameter ADC_PREP_READ_DATA_STATE = 11'b00100000000; // Prepares data to perform Data Read +parameter ADC_READ_DATA_STATE = 11'b01000000000; // Reads Data +parameter ADC_READ_DATA_DONE_STATE = 11'b10000000000; // Signals completion of Data Read + +// Number of SCLK Periods required for Status + Data Read +parameter ADC_SCLK_PERIODS = 8'd48; + +//------------------------------------------------------------------------------ +//----------- Assign/Always Blocks --------------------------------------------- +//------------------------------------------------------------------------------ +assign adc_sdi_o = adc_sdi_o_int; +assign adc_sclk_o = (((present_state_m1 == ADC_READ_RESULT_STATE)||(present_state_m1 == ADC_SEND_DATA_STATE)||(present_state_m1 == ADC_READ_DATA_STATE))&&(sclk_cnt != 8'd0)) ? adc_clk_i : 1'b1; +assign dma_data_o = dma_rx_data_reg; +assign dma_data_rdy_o = dma_rdy_int; +assign adc_cs_o = cs_int; +assign tx_data_rdy_o = tx_data_rdy_int; +assign rx_data_o = rx_read_data_reg; +assign rx_data_rdy_o = rx_data_rdy_int; + +// Register States +always @(posedge fpga_clk_i) +begin + if(reset_n_i == 1'b0) + begin + present_state <= ADC_IDLE_STATE; + adc_status_o <= 1'b0; + end + else + begin + present_state <= next_state; + adc_status_o <= 1'b1; + end +end + +// State switch logic +always @(posedge fpga_clk_i) +begin + next_state <= present_state; + case(present_state) + ADC_IDLE_STATE: + begin + // If transmit data is required + if(start_transmission_i == 1'b1) + begin + next_state <= ADC_PREP_SEND_DATA_STATE; + end + // If read data is required + else if(start_read_i == 1'b1) + begin + next_state <= ADC_PREP_READ_DATA_STATE; + end + // If start conversion has been requested + else if(start_conversion_i == 1'b1) + begin + next_state <= ADC_WAIT_FOR_DATA_STATE; + end + end + ADC_WAIT_FOR_DATA_STATE: + begin + // If new data is available + if(adc_sdo_i == 1'b0) + begin + next_state <= ADC_PREP_READ_RESULT_STATE; + end + // If transmit data is required + else if(start_transmission_i == 1'b1) + begin + next_state <= ADC_PREP_SEND_DATA_STATE; + end + // If read data is required + else if(start_read_i == 1'b1) + begin + next_state <= ADC_PREP_READ_DATA_STATE; + end + // If transmit data is not required anymore + else if(start_conversion_i == 1'b0) + begin + next_state <= ADC_IDLE_STATE; + end + end + ADC_PREP_READ_RESULT_STATE: + begin + if(present_state_m1 == ADC_PREP_READ_RESULT_STATE) + begin + next_state <= ADC_READ_RESULT_STATE; + end + end + ADC_READ_RESULT_STATE: + begin + // If data has been sent + if(sclk_cnt == 8'd0) + begin + next_state <= ADC_READ_RESULT_DONE_STATE; + end + end + ADC_READ_RESULT_DONE_STATE: + begin + next_state <= ADC_IDLE_STATE; + end + ADC_PREP_SEND_DATA_STATE: + begin + if(present_state_m1 == ADC_PREP_SEND_DATA_STATE) + begin + next_state <= ADC_SEND_DATA_STATE; + end + end + ADC_SEND_DATA_STATE: + begin + // If data has been sent + if(sclk_cnt == 8'd0) + begin + next_state <= ADC_SEND_DATA_DONE_STATE; + end + end + ADC_SEND_DATA_DONE_STATE: + begin + next_state <= ADC_IDLE_STATE; + end + ADC_PREP_READ_DATA_STATE: + begin + if(present_state_m1 == ADC_PREP_READ_DATA_STATE) + begin + next_state <= ADC_READ_DATA_STATE; + end + end + ADC_READ_DATA_STATE: + begin + // If data has been sent + if(sclk_cnt == 8'd0) + begin + next_state <= ADC_READ_DATA_DONE_STATE; + end + end + ADC_READ_DATA_DONE_STATE: + begin + next_state <= ADC_IDLE_STATE; + end + default: + begin + next_state <= ADC_IDLE_STATE; + end + endcase +end + +// State output logic +always @(posedge fpga_clk_i) +begin + if(reset_n_i == 1'b0) + begin + dma_rdy_int <= 1'b0; + cs_int <= 1'b1; + tx_data_rdy_int <= 1'b0; + rx_data_rdy_int <= 1'b0; + end + else + begin + case(present_state) + ADC_IDLE_STATE: + begin + dma_rdy_int <= 1'b0; + tx_data_rdy_int <= 1'b0; + rx_data_rdy_int <= 1'b0; + cs_int <= 1'b1; + end + ADC_WAIT_FOR_DATA_STATE: + begin + cs_int <= 1'b0; + end + ADC_PREP_READ_RESULT_STATE: + begin + dma_rdy_int <= 1'b0; + tx_data_reg_switch <= 48'h400044000000; + cs_int <= 1'b0; + end + ADC_READ_RESULT_STATE: + begin + dma_rdy_int <= 1'b0; + cs_int <= 1'b0; + end + ADC_READ_RESULT_DONE_STATE: + begin + // Final data = Status Reg + Data Reg + dma_rx_data_reg <= {rx_data_reg[39:32], rx_data_reg[23:0]}; + dma_rdy_int <= 1'b1; + cs_int <= 1'b1; + end + ADC_PREP_SEND_DATA_STATE: + begin + // Maximum 32 bits transmission (that is why I add 16'd0 to the LSB) + tx_data_rdy_int <= 1'b1; + cs_int <= 1'b1; + tx_data_reg_switch <= {tx_data_i, 16'd0}; + end + ADC_SEND_DATA_STATE: + begin + tx_data_rdy_int <= 1'b0; + cs_int <= 1'b0; + end + ADC_SEND_DATA_DONE_STATE: + begin + tx_data_rdy_int <= 1'b1; + cs_int <= 1'b1; + end + ADC_PREP_READ_DATA_STATE: + begin + // Maximum 32 bits transmission (that is why I add 16'd0 to the LSB) + cs_int <= 1'b1; + rx_data_rdy_int <= 1'b1; + tx_data_reg_switch <= {2'b01, tx_data_i[29:0], 16'd0}; + end + ADC_READ_DATA_STATE: + begin + cs_int <= 1'b0; + rx_data_rdy_int <= 1'b0; + end + ADC_READ_DATA_DONE_STATE: + begin + rx_read_data_reg <= rx_data_reg[31:0]; + cs_int <= 1'b1; + rx_data_rdy_int <= 1'b1; + end + default: + begin + tx_data_rdy_int <= 1'b0; + rx_data_rdy_int <= 1'b0; + dma_rdy_int <= 1'b0; + cs_int <= 1'b1; + end + endcase + end +end + +// Synchronise States between different clock domains +always @(posedge adc_clk_i) +begin + present_state_m1 <= present_state; +end + +// Select size of transfered data according to desired registers (see AD7176_2 Datasheet for details) +always @(posedge fpga_clk_i) +begin + case(tx_data_i[29:24]) + 6'h00: + begin + sclk_demand <= 8'd16; + end + 6'h01, 6'h02, 6'h06, 6'h07, 6'h10, 6'h11, 6'h12, 6'h13, 6'h20, 6'h21, 6'h22, 6'h23, 6'h28, 6'h29, 6'h2a, 6'h2b: + begin + sclk_demand <= 8'd24; + end + 6'h03, 6'h04, 6'h30, 6'h31, 6'h32, 6'h33, 6'h38, 6'h39, 6'h3a, 6'h3b: + begin + sclk_demand <= 8'd32; + end + default: + begin + sclk_demand <= 8'd16; + end + endcase +end + +// Serial Data In +always @(posedge adc_clk_i) +begin + if((present_state_m1 == ADC_READ_RESULT_STATE)||(present_state_m1 == ADC_SEND_DATA_STATE)||(present_state_m1 == ADC_READ_DATA_STATE)) + begin + sclk_cnt <= sclk_cnt - 8'd1; + rx_data_reg <= {rx_data_reg[46:0], adc_sdo_i}; + end + else + begin + if((present_state_m1 == ADC_PREP_SEND_DATA_STATE)||(present_state_m1 == ADC_PREP_READ_DATA_STATE)) + begin + sclk_cnt <= sclk_demand; + end + else + begin + sclk_cnt <= ADC_SCLK_PERIODS; + end + if(present_state_m1 == ADC_IDLE_STATE) + begin + rx_data_reg <= 48'd0; + end + end +end + +// Serial Data Out +always @(negedge adc_clk_i) +begin + if((present_state_m1 == ADC_READ_RESULT_STATE)||(present_state_m1 == ADC_SEND_DATA_STATE)||(present_state_m1 == ADC_READ_DATA_STATE)) + begin + adc_sdi_o_int <= tx_data_reg[47]; + tx_data_reg <= {tx_data_reg[46:0], 1'b0}; + end + else + begin + tx_data_reg <= tx_data_reg_switch; + end +end + +endmodule diff --git a/library/axi_ad7175/ad_datafmt.v b/library/axi_ad7175/ad_datafmt.v new file mode 100644 index 000000000..8a356085c --- /dev/null +++ b/library/axi_ad7175/ad_datafmt.v @@ -0,0 +1,117 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// data format (offset binary or 2's complement only) + +`timescale 1ps/1ps + +module ad_datafmt ( + + // data path + + clk, + valid, + data, + valid_out, + data_out, + + // control signals + + dfmt_enable, + dfmt_type, + dfmt_se); + + // delayed data bus width + + parameter DATA_WIDTH = 16; + parameter DATA_WIDTH_OUT = 16; + localparam DW = DATA_WIDTH - 1; + localparam DW1 = DATA_WIDTH_OUT - 1; + + // data path + + input clk; + input valid; + input [ DW:0] data; + output valid_out; + output [DW1:0] data_out; + + // control signals + + input dfmt_enable; + input dfmt_type; + input dfmt_se; + + // internal registers + + reg valid_out = 'd0; + reg [DW1:0] data_out = 'd0; + + // internal signals + + wire type_s; + wire signext_s; + wire [ DW:0] data_s; + wire [DW1:0] sign_s; + wire [DW1:0] data_out_s; + + // if offset-binary convert to 2's complement first + + assign type_s = dfmt_enable & dfmt_type; + assign signext_s = dfmt_enable & dfmt_se; + + assign data_s = (type_s == 1'b1) ? {~data[DW], data[(DW-1):0]} : data; + assign sign_s = (signext_s == 1'b1) ? {{DW1{data_s[DW]}}} : 0; + + generate + if (DW == DW1) begin + assign data_out_s = data_s; + end else begin + assign data_out_s = {sign_s[DW1:(DW+1)], data_s}; + end + endgenerate + + always @(posedge clk) begin + valid_out <= valid; + data_out <= valid ? data_out_s[DW1:0] : data_out; + end + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad7175/axi_ad7175.v b/library/axi_ad7175/axi_ad7175.v new file mode 100644 index 000000000..a4cb5a1c7 --- /dev/null +++ b/library/axi_ad7175/axi_ad7175.v @@ -0,0 +1,427 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad7175 ( + + // adc interface (clk, data, over-range) + + adc_sdo_i, + adc_sdi_o, + adc_cs_o, + adc_sclk_o, + adc_clk_i, + led_clk_o, + + // dma interface + + adc_clk, + adc_enable_0, + adc_data_0, + adc_enable_1, + adc_data_1, + adc_enable_2, + adc_data_2, + adc_enable_3, + adc_data_3, + adc_valid_o, + adc_dovf, + adc_dunf, + + // axi interface + + s_axi_aclk, + s_axi_aresetn, + s_axi_awvalid, + s_axi_awaddr, + s_axi_awready, + s_axi_wvalid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wready, + s_axi_bvalid, + s_axi_bresp, + s_axi_bready, + s_axi_arvalid, + s_axi_araddr, + s_axi_arready, + s_axi_rvalid, + s_axi_rresp, + s_axi_rdata, + s_axi_rready); + + // parameters + + parameter PCORE_ID = 0; + parameter PCORE_DEVICE_TYPE = 0; + parameter PCORE_ADC_DP_DISABLE = 0; + parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; + parameter C_S_AXI_MIN_SIZE = 32'hffff; + + // adc interface (clk, data, over-range) + + input adc_sdo_i; + output adc_sdi_o; + output adc_cs_o; + output adc_sclk_o; + input adc_clk_i; + output led_clk_o; + + // dma interface + + output adc_clk; + output adc_enable_0; + output [31:0] adc_data_0; + output adc_enable_1; + output [31:0] adc_data_1; + output adc_enable_2; + output [31:0] adc_data_2; + output adc_enable_3; + output [31:0] adc_data_3; + output adc_valid_o; + input adc_dovf; + input adc_dunf; + + + // axi interface + + input s_axi_aclk; + input s_axi_aresetn; + input s_axi_awvalid; + input [31:0] s_axi_awaddr; + output s_axi_awready; + input s_axi_wvalid; + input [31:0] s_axi_wdata; + input [ 3:0] s_axi_wstrb; + output s_axi_wready; + output s_axi_bvalid; + output [ 1:0] s_axi_bresp; + input s_axi_bready; + input s_axi_arvalid; + input [31:0] s_axi_araddr; + output s_axi_arready; + output s_axi_rvalid; + output [ 1:0] s_axi_rresp; + output [31:0] s_axi_rdata; + input s_axi_rready; + + // internal registers + + reg [31:0] up_rdata = 'd0; + reg up_rack = 'd0; + reg up_wack = 'd0; + wire adc_valid_s; + reg adc_valid_d1; + + // internal clocks & resets + + wire adc_rst; + wire up_rstn; + wire up_clk; + wire [13:0] up_waddr_s; + wire [13:0] up_raddr_s; + + // internal signals + + wire adc_status_s; + wire up_sel_s; + wire up_wr_s; + wire [13:0] up_addr_s; + wire [31:0] up_wdata_s; + wire [31:0] up_rdata_s[0:4]; + wire up_rack_s[0:4]; + wire up_wack_s[0:4]; + + wire [31:0] adc_data_s; + wire [ 1:0] adc_reg_rw_s; + wire [31:0] adc_reg_address_s; + wire [31:0] adc_reg_data_w_s; + wire [31:0] adc_rx_data_s; + wire adc_rx_data_rdy_s; + wire adc_tx_data_rdy_s; + wire [31:0] adc_gpio_out; + + wire clk_div_update_rdy_s; + wire [31:0] phase_data_s; + + // signal name changes + assign adc_clk = s_axi_aclk; + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + assign adc_valid_o = adc_valid_s & ~adc_valid_d1; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3] | up_rdata_s[4]; + up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3] | up_rack_s[4]; + up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3] | up_wack_s[4]; + adc_valid_d1 <= adc_valid_s; + end + end + + // channel + + axi_ad7175_channel #( + .CHID(0), + .DP_DISABLE (PCORE_ADC_DP_DISABLE)) + i_channel_0 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data ({8'b0, adc_data_s[23:0]}), + .adc_valid_in(data_rd_ready_s && (adc_data_s[25:24] == 2'b0)), + .adc_data_out (adc_data_0), + .adc_valid (), + .adc_enable (adc_enable_0), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + +// channel + + axi_ad7175_channel #( + .CHID(1), + .DP_DISABLE (PCORE_ADC_DP_DISABLE)) + i_channel_1 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data (phase_data_s), + .adc_valid_in(data_rd_ready_s && (adc_data_s[25:24] == 2'b0)), + .adc_data_out (adc_data_1), + .adc_valid (), + .adc_enable (adc_enable_1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[1]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[1]), + .up_rack (up_rack_s[1])); + + // channel + + axi_ad7175_channel #( + .CHID(3), + .DP_DISABLE (PCORE_ADC_DP_DISABLE)) + i_channel_2 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data ({8'b0, adc_data_s[23:0]}), + .adc_valid_in(data_rd_ready_s && (adc_data_s[25:24] == 2'b1)), + .adc_data_out (adc_data_2), + .adc_valid (), + .adc_enable (adc_enable_2), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[2]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[2]), + .up_rack (up_rack_s[2])); + + axi_ad7175_channel #( + .CHID(4), + .DP_DISABLE (PCORE_ADC_DP_DISABLE)) + i_channel_3 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data (phase_data_s), + .adc_valid_in(data_rd_ready_s && (adc_data_s[25:24] == 2'b1)), + .adc_data_out (adc_data_3), + .adc_valid (adc_valid_s), + .adc_enable (adc_enable_3), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[3]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[3]), + .up_rack (up_rack_s[3])); + + // clock divider + clk_div clk_div_i ( + .clk_i(s_axi_aclk), + .reset_n_i(up_rstn), + .new_div_i(adc_reg_rw_s[1] && (adc_reg_address_s[7:0] == 8'h40)), + .div_i(adc_reg_data_w_s[31:0]), + .new_phase_inc_i(adc_reg_rw_s[1] && (adc_reg_address_s[7:0] == 8'h41)), + .phase_inc_i(adc_reg_data_w_s[31:0]), + .reg_update_rdy_o(clk_div_update_rdy_s), + .clk_o(led_clk_o), + .phase_o(phase_data_s)); + + // main (device interface) + + ad7175_if ad7175_if_i( + .fpga_clk_i(s_axi_aclk), + .adc_clk_i(adc_clk_i), + .reset_n_i(~adc_rst), + + .start_conversion_i(adc_gpio_out[0]), + .dma_data_o(adc_data_s), + .dma_data_rdy_o(data_rd_ready_s), + + .start_transmission_i(adc_reg_rw_s[1] && (adc_reg_address_s[7:0] < 8'h39)), + .tx_data_i({adc_reg_address_s[7:0], adc_reg_data_w_s[23:0]}), + .tx_data_rdy_o(adc_tx_data_rdy_s), + + .start_read_i(adc_reg_rw_s[0] && (adc_reg_address_s[7:0] < 8'h39)), + .rx_data_o(adc_rx_data_s), + .rx_data_rdy_o(adc_rx_data_rdy_s), + + .adc_sdo_i(adc_sdo_i), + .adc_sdi_o(adc_sdi_o), + .adc_cs_o(adc_cs_o), + .adc_sclk_o(adc_sclk_o), + .adc_status_o(adc_status_s)); + + // common processor control + + up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common ( + .mmcm_rst (), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status (adc_status_s), + .adc_status_ovf (adc_dovf), + .adc_status_unf (adc_dunf), + .adc_clk_ratio (32'd1), + + .adc_reg_address(adc_reg_address_s), + .adc_reg_data_r(adc_rx_data_s), + .adc_reg_data_w(adc_reg_data_w_s), + .adc_reg_rw(adc_reg_rw_s), + .adc_reg_done(adc_tx_data_rdy_s | adc_rx_data_rdy_s | clk_div_update_rdy_s), + + .up_status_pn_err (1'b0), + .up_status_pn_oos (1'b0), + .up_status_or (1'b0), + .delay_clk (), + .delay_rst (), + .delay_sel (), + .delay_rwn (), + .delay_addr (), + .delay_wdata (), + .delay_rdata (), + .delay_ack_t (), + .delay_locked (), + .drp_clk (1'd0), + .drp_rst (), + .drp_sel (), + .drp_wr (), + .drp_addr (), + .drp_wdata (), + .drp_rdata (16'd0), + .drp_ready (1'd0), + .drp_locked (1'd1), + .up_usr_chanmax (), + .adc_usr_chanmax (8'd0), + .up_adc_gpio_in (), + .up_adc_gpio_out (adc_gpio_out), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[4]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[4]), + .up_rack (up_rack_s[4])); + + // up bus interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_ad7175/axi_ad7175_channel.v b/library/axi_ad7175/axi_ad7175_channel.v new file mode 100644 index 000000000..e813c6099 --- /dev/null +++ b/library/axi_ad7175/axi_ad7175_channel.v @@ -0,0 +1,174 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// ADC channel- + +`timescale 1ns/100ps + +module axi_ad7175_channel ( + + // adc interface + adc_clk, + adc_rst, + adc_data, + adc_valid_in, + + // channel interface + adc_data_out, + adc_valid, + adc_enable, + + + // processor interface + up_rstn, + up_clk, + up_wreq, + up_waddr, + up_wdata, + up_wack, + up_rreq, + up_raddr, + up_rdata, + up_rack); + + // parameters + + parameter CHID = 0; + parameter DP_DISABLE = 0; + + // adc interface + + input adc_clk; + input adc_rst; + input [31:0] adc_data; + input adc_valid_in; + // channel interface + + output [31:0] adc_data_out; + output adc_valid; + output adc_enable; + + // processor interface + + input up_rstn; + input up_clk; + input up_wreq; + input [13:0] up_waddr; + input [31:0] up_wdata; + output up_wack; + input up_rreq; + input [13:0] up_raddr; + output [31:0] up_rdata; + output up_rack; + + // internal signals + + wire adc_dfmt_se_s; + wire adc_dfmt_type_s; + wire adc_dfmt_enable_s; + + generate + if (DP_DISABLE == 1) begin + assign adc_valid = adc_valid_in; + assign adc_data_out = {8'b0, adc_data}; + end else begin + ad_datafmt #( + .DATA_WIDTH(32), + .DATA_WIDTH_OUT(32)) + i_ad_datafmt ( + .clk (adc_clk), + .valid (adc_valid_in), + .data (adc_data), + .valid_out (adc_valid), + .data_out (adc_data_out), + .dfmt_enable (adc_dfmt_enable_s), + .dfmt_type (adc_dfmt_type_s), + .dfmt_se (adc_dfmt_se_s)); + end + endgenerate + + up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_enable (adc_enable), + .adc_iqcor_enb (), + .adc_dcfilt_enb (), + .adc_dfmt_se (adc_dfmt_se_s), + .adc_dfmt_type (adc_dfmt_type_s), + .adc_dfmt_enable (adc_dfmt_enable_s), + .adc_dcfilt_offset (), + .adc_dcfilt_coeff (), + .adc_iqcor_coeff_1 (), + .adc_iqcor_coeff_2 (), + .adc_pnseq_sel (), + .adc_data_sel (), + .adc_pn_err (), + .adc_pn_oos (), + .adc_or (), + .up_adc_pn_err (), + .up_adc_pn_oos (), + .up_adc_or (), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd32), + .adc_usr_datatype_bits (8'd32), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad7175/axi_ad7175_ip.tcl b/library/axi_ad7175/axi_ad7175_ip.tcl new file mode 100644 index 000000000..211a2747e --- /dev/null +++ b/library/axi_ad7175/axi_ad7175_ip.tcl @@ -0,0 +1,27 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_ad7175 +adi_ip_files axi_ad7175 [list \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ + "$ad_hdl_dir/library/common/up_drp_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "up_adc_common.v" \ + "ad_datafmt.v" \ + "ad7175_if.v" \ + "axi_ad7175.v" \ + "axi_ad7175_channel.v" \ + "clk_div.v" ] + +adi_ip_properties axi_ad7175 + +ipx::save_core [ipx::current_core] + + diff --git a/library/axi_ad7175/clk_div.v b/library/axi_ad7175/clk_div.v new file mode 100644 index 000000000..80ce82b01 --- /dev/null +++ b/library/axi_ad7175/clk_div.v @@ -0,0 +1,125 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +//------------------------------------------------------------------------------ +//----------- Module Declaration ----------------------------------------------- +//------------------------------------------------------------------------------ +module clk_div + ( + // Clock and Reset signals + input clk_i, + input reset_n_i, + + // Clock divider + input new_div_i, + input [31:0] div_i, + input new_phase_inc_i, + input [31:0] phase_inc_i, + + // Divided clock output + output reg reg_update_rdy_o, + output clk_o, + output [31:0] phase_o + ); + +//------------------------------------------------------------------------------ +//----------- Registers Declarations ------------------------------------------- +//------------------------------------------------------------------------------ +reg [31:0] div; +reg [31:0] div_cnt; +reg [31:0] phase; +reg [31:0] phase_inc; +reg clk_div; + +//------------------------------------------------------------------------------ +//----------- Assign/Always Blocks --------------------------------------------- +//------------------------------------------------------------------------------ +assign clk_o = clk_div; +assign phase_o = phase; + +// Register update logic +always @(posedge clk_i) +begin + if(reset_n_i == 1'b0) + begin + div <= 'd0; + phase_inc <= 'd0; + reg_update_rdy_o <= 1'b0; + end + else + begin + if(new_div_i == 1'b1) + begin + div <= div_i; + end + if(new_phase_inc_i == 1'b1) + begin + phase_inc <= phase_inc_i; + end + reg_update_rdy_o <= new_div_i | new_phase_inc_i; + end +end + +// Clock division logic +always @(posedge clk_i) +begin + if(reset_n_i == 1'b0) + begin + clk_div <= 'd1; + phase <= 'd0; + end + else + begin + if(div_cnt < div) + begin + div_cnt <= div_cnt + 'd1; + end + else + begin + div_cnt <= 'd1; + //clk_div <= ~clk_div; + end + phase <= phase + phase_inc; + clk_div <= phase[31]; + end +end + +endmodule diff --git a/library/axi_ad7175/up_adc_common.v b/library/axi_ad7175/up_adc_common.v new file mode 100644 index 000000000..3c8025396 --- /dev/null +++ b/library/axi_ad7175/up_adc_common.v @@ -0,0 +1,518 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module up_adc_common ( + + // clock reset + + mmcm_rst, + + // adc interface + + adc_clk, + adc_rst, + adc_r1_mode, + adc_ddr_edgesel, + adc_pin_mode, + adc_status, + adc_sync_status, + adc_status_ovf, + adc_status_unf, + adc_clk_ratio, + adc_start_code, + adc_sync, + adc_reg_address, + adc_reg_data_r, + adc_reg_data_w, + adc_reg_rw, + adc_reg_done, + + // channel interface + + up_status_pn_err, + up_status_pn_oos, + up_status_or, + + // delay interface + + delay_clk, + delay_rst, + delay_sel, + delay_rwn, + delay_addr, + delay_wdata, + delay_rdata, + delay_ack_t, + delay_locked, + + // drp interface + + drp_clk, + drp_rst, + drp_sel, + drp_wr, + drp_addr, + drp_wdata, + drp_rdata, + drp_ready, + drp_locked, + + // user channel control + + up_usr_chanmax, + adc_usr_chanmax, + up_adc_gpio_in, + up_adc_gpio_out, + + // bus interface + + up_rstn, + up_clk, + up_wreq, + up_waddr, + up_wdata, + up_wack, + up_rreq, + up_raddr, + up_rdata, + up_rack); + + // parameters + + localparam PCORE_VERSION = 32'h00080062; + parameter PCORE_ID = 0; + + // clock reset + + output mmcm_rst; + + // adc interface + + input adc_clk; + output adc_rst; + output adc_r1_mode; + output adc_ddr_edgesel; + output adc_pin_mode; + input adc_status; + input adc_sync_status; + input adc_status_ovf; + input adc_status_unf; + input [31:0] adc_clk_ratio; + output [31:0] adc_start_code; + output adc_sync; + output [31:0] adc_reg_address; + input [31:0] adc_reg_data_r; + output [31:0] adc_reg_data_w; + output [ 1:0] adc_reg_rw; + input adc_reg_done; + + // channel interface + + input up_status_pn_err; + input up_status_pn_oos; + input up_status_or; + + // delay interface + + input delay_clk; + output delay_rst; + output delay_sel; + output delay_rwn; + output [ 7:0] delay_addr; + output [ 4:0] delay_wdata; + input [ 4:0] delay_rdata; + input delay_ack_t; + input delay_locked; + + // drp interface + + input drp_clk; + output drp_rst; + output drp_sel; + output drp_wr; + output [11:0] drp_addr; + output [15:0] drp_wdata; + input [15:0] drp_rdata; + input drp_ready; + input drp_locked; + + // user channel control + + output [ 7:0] up_usr_chanmax; + input [ 7:0] adc_usr_chanmax; + input [31:0] up_adc_gpio_in; + output [31:0] up_adc_gpio_out; + + // bus interface + + input up_rstn; + input up_clk; + input up_wreq; + input [13:0] up_waddr; + input [31:0] up_wdata; + output up_wack; + input up_rreq; + input [13:0] up_raddr; + output [31:0] up_rdata; + output up_rack; + + // internal registers + + reg up_wack = 'd0; + reg [31:0] up_scratch = 'd0; + reg up_mmcm_resetn = 'd0; + reg up_resetn = 'd0; + reg up_adc_r1_mode = 'd0; + reg up_adc_ddr_edgesel = 'd0; + reg up_adc_pin_mode = 'd0; + reg up_delay_sel = 'd0; + reg up_delay_rwn = 'd0; + reg [ 7:0] up_delay_addr = 'd0; + reg [ 4:0] up_delay_wdata = 'd0; + reg up_drp_sel_t = 'd0; + reg up_drp_rwn = 'd0; + reg [11:0] up_drp_addr = 'd0; + reg [15:0] up_drp_wdata = 'd0; + reg up_status_ovf = 'd0; + reg up_status_unf = 'd0; + reg [ 7:0] up_usr_chanmax = 'd0; + reg [31:0] up_adc_gpio_out = 'd0; + reg [31:0] up_adc_start_code = 'd0; + reg up_adc_sync = 'd0; + reg up_rack = 'd0; + reg [31:0] up_rdata = 'd0; + reg [31:0] up_adc_reg_address = 'd0; + reg [31:0] up_adc_reg_data = 'd0; + reg up_adc_reg_write = 'd0; + reg up_adc_reg_read = 'd0; + + // internal signals + + wire up_wreq_s; + wire up_rreq_s; + wire up_preset_s; + wire up_mmcm_preset_s; + wire up_status_s; + wire up_sync_status_s; + wire up_status_ovf_s; + wire up_status_unf_s; + wire up_cntrl_xfer_done; + wire [31:0] up_adc_clk_count_s; + wire [ 4:0] up_delay_rdata_s; + wire up_delay_status_s; + wire up_delay_locked_s; + wire [15:0] up_drp_rdata_s; + wire up_drp_status_s; + wire up_drp_locked_s; + wire [31:0] up_adc_reg_data_s; + wire up_adc_reg_done_s; + + // decode block select + + assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0; + assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0; + assign up_preset_s = ~up_resetn; + assign up_mmcm_preset_s = ~up_mmcm_resetn; + + // processor write interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_scratch <= 'd0; + up_mmcm_resetn <= 'd0; + up_resetn <= 'd0; + up_adc_r1_mode <= 'd0; + up_adc_ddr_edgesel <= 'd0; + up_adc_pin_mode <= 'd0; + up_delay_sel <= 'd0; + up_delay_rwn <= 'd0; + up_delay_addr <= 'd0; + up_delay_wdata <= 'd0; + up_drp_sel_t <= 'd0; + up_drp_rwn <= 'd0; + up_drp_addr <= 'd0; + up_drp_wdata <= 'd0; + up_status_ovf <= 'd0; + up_status_unf <= 'd0; + up_usr_chanmax <= 'd0; + up_adc_gpio_out <= 'd0; + up_adc_start_code <= 'd0; + up_adc_reg_address <= 'd0; + up_adc_reg_data <= 'd0; + up_adc_reg_read <= 'd0; + up_adc_reg_write <= 'd0; + end else begin + up_wack <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin + up_scratch <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin + up_mmcm_resetn <= up_wdata[1]; + up_resetn <= up_wdata[0]; + end + if (up_adc_sync == 1'b1) begin + if (up_cntrl_xfer_done == 1'b1) begin + up_adc_sync <= 1'b0; + end + end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin + up_adc_sync <= up_wdata[3]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin + up_adc_r1_mode <= up_wdata[2]; + up_adc_ddr_edgesel <= up_wdata[1]; + up_adc_pin_mode <= up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin + up_adc_reg_address <= up_wdata; + end + + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin + up_adc_reg_data <= up_wdata; + end + else if((up_adc_reg_done_s == 1'b1) && (up_adc_reg_read == 1'b1)) + begin + up_adc_reg_data <= up_adc_reg_data_s; + end + + if (up_adc_reg_read == 1'b1) begin + if (up_adc_reg_done_s == 1'b1) begin + up_adc_reg_read <= 1'b0; + end + end else if (up_adc_reg_write == 1'b1) begin + if (up_adc_reg_done_s == 1'b1) begin + up_adc_reg_write <= 1'b0; + end + end + else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin + up_adc_reg_write <= up_wdata[1]; + up_adc_reg_read <= up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h18)) begin + up_delay_sel <= up_wdata[17]; + up_delay_rwn <= up_wdata[16]; + up_delay_addr <= up_wdata[15:8]; + up_delay_wdata <= up_wdata[4:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin + up_drp_sel_t <= ~up_drp_sel_t; + up_drp_rwn <= up_wdata[28]; + up_drp_addr <= up_wdata[27:16]; + up_drp_wdata <= up_wdata[15:0]; + end + if (up_status_ovf_s == 1'b1) begin + up_status_ovf <= 1'b1; + end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin + up_status_ovf <= up_status_ovf & ~up_wdata[2]; + end + if (up_status_unf_s == 1'b1) begin + up_status_unf <= 1'b1; + end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin + up_status_unf <= up_status_unf & ~up_wdata[1]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin + up_usr_chanmax <= up_wdata[7:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h29)) begin + up_adc_start_code <= up_wdata[31:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2f)) begin + up_adc_gpio_out <= up_wdata; + end + end + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_rack <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr[7:0]) + 8'h00: up_rdata <= PCORE_VERSION; + 8'h01: up_rdata <= PCORE_ID; + 8'h02: up_rdata <= up_scratch; + 8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn}; + 8'h11: up_rdata <= {28'd0, up_adc_sync, up_adc_r1_mode, up_adc_ddr_edgesel, up_adc_pin_mode}; + 8'h12: up_rdata <= up_adc_reg_address; + 8'h13: up_rdata <= up_adc_reg_data; + 8'h14: up_rdata <= {30'd0, up_adc_reg_write, up_adc_reg_read}; + 8'h15: up_rdata <= up_adc_clk_count_s; + 8'h16: up_rdata <= adc_clk_ratio; + 8'h17: up_rdata <= {28'd0, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s}; + 8'h18: up_rdata <= {14'd0, up_delay_sel, up_delay_rwn, up_delay_addr, 3'd0, up_delay_wdata}; + 8'h19: up_rdata <= {22'd0, up_delay_locked_s, up_delay_status_s, 3'd0, up_delay_rdata_s}; + 8'h1a: up_rdata <= {31'd0, up_sync_status_s}; + 8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata}; + 8'h1d: up_rdata <= {14'd0, up_drp_locked_s, up_drp_status_s, up_drp_rdata_s}; + 8'h22: up_rdata <= {29'd0, up_status_ovf, up_status_unf, 1'b0}; + 8'h23: up_rdata <= 32'd8; + 8'h28: up_rdata <= {24'd0, adc_usr_chanmax}; + 8'h29: up_rdata <= up_adc_start_code; + 8'h2e: up_rdata <= up_adc_gpio_in; + 8'h2f: up_rdata <= up_adc_gpio_out; + default: up_rdata <= 0; + endcase + end else begin + up_rdata <= 32'd0; + end + end + end + + // resets + + ad_rst i_mmcm_rst_reg (.preset(up_mmcm_preset_s), .clk(drp_clk), .rst(mmcm_rst)); + ad_rst i_adc_rst_reg (.preset(up_preset_s), .clk(adc_clk), .rst(adc_rst)); + ad_rst i_delay_rst_reg (.preset(up_preset_s), .clk(delay_clk), .rst(delay_rst)); + ad_rst i_drp_rst_reg (.preset(up_preset_s), .clk(drp_clk), .rst(drp_rst)); + + // adc control & status + + up_xfer_cntrl #(.DATA_WIDTH(70)) i_adc_xfer_cntrl ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_cntrl ({ up_adc_reg_address, + up_adc_reg_data, + up_adc_reg_write, + up_adc_reg_read, + up_adc_sync, + up_adc_r1_mode, + up_adc_ddr_edgesel, + up_adc_pin_mode}), + .up_xfer_done (up_cntrl_xfer_done), + .d_rst (adc_rst), + .d_clk (adc_clk), + .d_data_cntrl ({ adc_reg_address, + adc_reg_data_w, + adc_reg_rw[1], + adc_reg_rw[0], + adc_sync, + adc_r1_mode, + adc_ddr_edgesel, + adc_pin_mode})); + + up_xfer_status #(.DATA_WIDTH(37)) i_adc_xfer_status ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_status ({up_adc_reg_data_s, + up_adc_reg_done_s, + up_sync_status_s, + up_status_s, + up_status_ovf_s, + up_status_unf_s}), + .d_rst (adc_rst), + .d_clk (adc_clk), + .d_data_status ({ adc_reg_data_r, + adc_reg_done, + adc_sync_status, + adc_status, + adc_status_ovf, + adc_status_unf})); + + up_xfer_cntrl #(.DATA_WIDTH(32)) i_adc_xfer_start_code ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_cntrl (up_adc_start_code), + .up_xfer_done (), + .d_rst (adc_rst), + .d_clk (adc_clk), + .d_data_cntrl (adc_start_code)); + + // adc clock monitor + + up_clock_mon i_adc_clock_mon ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_d_count (up_adc_clk_count_s), + .d_rst (adc_rst), + .d_clk (adc_clk)); + + // delay control & status + + up_delay_cntrl i_delay_cntrl ( + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_sel (delay_sel), + .delay_rwn (delay_rwn), + .delay_addr (delay_addr), + .delay_wdata (delay_wdata), + .delay_rdata (delay_rdata), + .delay_ack_t (delay_ack_t), + .delay_locked (delay_locked), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_delay_sel (up_delay_sel), + .up_delay_rwn (up_delay_rwn), + .up_delay_addr (up_delay_addr), + .up_delay_wdata (up_delay_wdata), + .up_delay_rdata (up_delay_rdata_s), + .up_delay_status (up_delay_status_s), + .up_delay_locked (up_delay_locked_s)); + + // drp control & status + + up_drp_cntrl i_drp_cntrl ( + .drp_clk (drp_clk), + .drp_rst (drp_rst), + .drp_sel (drp_sel), + .drp_wr (drp_wr), + .drp_addr (drp_addr), + .drp_wdata (drp_wdata), + .drp_rdata (drp_rdata), + .drp_ready (drp_ready), + .drp_locked (drp_locked), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_drp_sel_t (up_drp_sel_t), + .up_drp_rwn (up_drp_rwn), + .up_drp_addr (up_drp_addr), + .up_drp_wdata (up_drp_wdata), + .up_drp_rdata (up_drp_rdata_s), + .up_drp_status (up_drp_status_s), + .up_drp_locked (up_drp_locked_s)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9361/axi_ad9361_rx.v b/library/axi_ad9361/axi_ad9361_rx.v index 42b0c23b4..a39b7f7ea 100644 --- a/library/axi_ad9361/axi_ad9361_rx.v +++ b/library/axi_ad9361/axi_ad9361_rx.v @@ -345,9 +345,12 @@ module axi_ad9361_rx ( .adc_ddr_edgesel (), .adc_pin_mode (), .adc_status (adc_status), + .adc_sync_status(), .adc_status_ovf (adc_dovf), .adc_status_unf (adc_dunf), .adc_clk_ratio (32'd1), + .adc_start_code(), + .adc_sync(), .up_status_pn_err (up_status_pn_err), .up_status_pn_oos (up_status_pn_oos), .up_status_or (up_status_or), diff --git a/library/axi_ad9434/axi_ad9434_pnmon.v b/library/axi_ad9434/axi_ad9434_pnmon.v index 276597a43..a29d7c4ed 100644 --- a/library/axi_ad9434/axi_ad9434_pnmon.v +++ b/library/axi_ad9434/axi_ad9434_pnmon.v @@ -66,6 +66,8 @@ module axi_ad9434_pnmon ( // internal signals wire [47:0] adc_pn_data_pn_s; + wire [47:0] adc_data_inv_s; + // prbs pn9 function function [47:0] pn9; input [47:0] din; @@ -181,7 +183,8 @@ module axi_ad9434_pnmon ( endfunction // pn sequence selection - assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_data : adc_pn_data_pn; + assign adc_data_inv_s = {adc_data[11:0], adc_data[23:12], adc_data[35:24], adc_data[47:36]}; + assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_data_inv_s : adc_pn_data_pn; always @(posedge adc_clk) begin if(adc_pnseq_sel == 4'b0) begin @@ -195,7 +198,7 @@ module axi_ad9434_pnmon ( ad_pnmon #(.DATA_WIDTH(48)) i_pnmon ( .adc_clk (adc_clk), .adc_valid_in (1'b1), - .adc_data_in (adc_data), + .adc_data_in (adc_data_inv_s), .adc_data_pn (adc_pn_data_pn), .adc_pn_oos (adc_pn_oos), .adc_pn_err (adc_pn_err)); diff --git a/library/axi_jesd_gt/axi_jesd_gt.v b/library/axi_jesd_gt/axi_jesd_gt.v index 85d5eeffa..c58a443ba 100644 --- a/library/axi_jesd_gt/axi_jesd_gt.v +++ b/library/axi_jesd_gt/axi_jesd_gt.v @@ -312,8 +312,11 @@ module axi_jesd_gt ( wire drp_ready_gt_s[15:0]; wire [ 7:0] drp_rx_rate_gt_s[15:0]; wire [287:0] tx_gt_data_extn_zero_s; + wire [ 35:0] tx_gt_charisk_extn_zero_s; wire [287:0] tx_gt_data_extn_s; + wire [ 35:0] tx_gt_charisk_extn_s; wire [287:0] tx_gt_data_mux_s; + wire [ 35:0] tx_gt_charisk_mux_s; wire qpll_locked_0_s; wire qpll_locked_1_s; wire [ 7:0] qpll_locked_s; @@ -430,7 +433,9 @@ module axi_jesd_gt ( assign tx_ip_data = tx_data; assign tx_gt_data_extn_zero_s = 288'd0; + assign tx_gt_charisk_extn_zero_s = 36'd0; assign tx_gt_data_extn_s = {tx_gt_data_extn_zero_s[(((9-PCORE_NUM_OF_LANES)*32)-1):0], tx_gt_data}; + assign tx_gt_charisk_extn_s = {tx_gt_charisk_extn_zero_s[(((9-PCORE_NUM_OF_LANES)*4)-1):0], tx_gt_charisk}; assign tx_gt_data_mux_s[((8*32)+31):(8*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_8*32)+31):(PCORE_TX_LANE_SEL_8*32)]; assign tx_gt_data_mux_s[((7*32)+31):(7*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_7*32)+31):(PCORE_TX_LANE_SEL_7*32)]; @@ -441,6 +446,15 @@ module axi_jesd_gt ( assign tx_gt_data_mux_s[((2*32)+31):(2*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_2*32)+31):(PCORE_TX_LANE_SEL_2*32)]; assign tx_gt_data_mux_s[((1*32)+31):(1*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_1*32)+31):(PCORE_TX_LANE_SEL_1*32)]; assign tx_gt_data_mux_s[((0*32)+31):(0*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_0*32)+31):(PCORE_TX_LANE_SEL_0*32)]; + assign tx_gt_charisk_mux_s[((8*4)+3):(8*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_8*4)+3):(PCORE_TX_LANE_SEL_8*4)]; + assign tx_gt_charisk_mux_s[((7*4)+3):(7*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_7*4)+3):(PCORE_TX_LANE_SEL_7*4)]; + assign tx_gt_charisk_mux_s[((6*4)+3):(6*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_6*4)+3):(PCORE_TX_LANE_SEL_6*4)]; + assign tx_gt_charisk_mux_s[((5*4)+3):(5*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_5*4)+3):(PCORE_TX_LANE_SEL_5*4)]; + assign tx_gt_charisk_mux_s[((4*4)+3):(4*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_4*4)+3):(PCORE_TX_LANE_SEL_4*4)]; + assign tx_gt_charisk_mux_s[((3*4)+3):(3*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_3*4)+3):(PCORE_TX_LANE_SEL_3*4)]; + assign tx_gt_charisk_mux_s[((2*4)+3):(2*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_2*4)+3):(PCORE_TX_LANE_SEL_2*4)]; + assign tx_gt_charisk_mux_s[((1*4)+3):(1*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_1*4)+3):(PCORE_TX_LANE_SEL_1*4)]; + assign tx_gt_charisk_mux_s[((0*4)+3):(0*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_0*4)+3):(PCORE_TX_LANE_SEL_0*4)]; // clock buffers @@ -573,7 +587,7 @@ module axi_jesd_gt ( .tx_rst_done (tx_rst_done_s[n]), .tx_pll_locked (tx_pll_locked_s[n]), .tx_clk (tx_clk), - .tx_charisk (tx_gt_charisk[n*4+3:n*4]), + .tx_charisk (tx_gt_charisk_mux_s[n*4+3:n*4]), .tx_data (tx_gt_data_mux_s[n*32+31:n*32]), .drp_clk (drp_clk), .drp_sel (drp_sel_s), diff --git a/library/common/ad_interrupts.v b/library/common/ad_interrupts.v new file mode 100644 index 000000000..aa9c24cdb --- /dev/null +++ b/library/common/ad_interrupts.v @@ -0,0 +1,186 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ps/1ps + +module ad_interrupts ( + // interrupt lines + input timer_irq, + input eth_irq, + input eth_dma_mm2s_irq, + input eth_dma_s2mm_irq, + input uart_irq, + input gpio_lcd_irq, + input gpio_sw_irq, + input spdif_dma_irq, + input hdmi_dma_irq, + input iic_irq, + input dev0_dma_irq, + input dev1_dma_irq, + input dev2_dma_irq, + input dev3_dma_irq, + input dev4_dma_irq, + input dev5_dma_irq, + input spi0_irq, + input spi1_irq, + input spi2_irq, + input spi3_irq, + input gpio0_irq, + input gpio1_irq, + input gpio2_irq, + input gpio3_irq, + // concatanated interrupt outputs + output [31:0] mb_axi_intr, + output [15:0] ps7_irq_f2p +); + + localparam ZYNQ = 1; + localparam MBLAZE = 0; + + parameter C_PROC_TYPE = ZYNQ; + parameter C_DEVICE_NR = 0; + parameter C_XSPI_NR = 0; + parameter C_XGPIO_NR = 0; + + localparam IRQ_F2P_WIDTH = 16; + + localparam IRQ_NUMBER_ZQ = 2 + C_DEVICE_NR + C_XSPI_NR + C_XGPIO_NR; + localparam IRQ_NUMBER_MB = 10 + C_DEVICE_NR + C_XSPI_NR + C_XGPIO_NR; + + localparam DEVICE_OFFSET_ZQ = 2; + localparam XSPI_OFFSET_ZQ = 2 + C_DEVICE_NR; + localparam XGPIO_OFFSET_ZQ = 2 + C_DEVICE_NR + C_XSPI_NR; + localparam DEVICE_OFFSET_MB = 10; + localparam XSPI_OFFSET_MB = 10 + C_DEVICE_NR; + localparam XGPIO_OFFSET_MB = 10 + C_DEVICE_NR + C_XSPI_NR; + + wire [31:0] mb_axi_intr_s; + wire [15:0] ps7_irq_f2p_s; + wire [15:0] ps7_irq_f2p_inv_s; + + // ========================================================================== + // IRQ assignments just for MicroBlaze devices + // ========================================================================== + + assign mb_axi_intr_s[0] = timer_irq; + assign mb_axi_intr_s[1] = eth_irq; + assign mb_axi_intr_s[2] = eth_dma_mm2s_irq; + assign mb_axi_intr_s[3] = eth_dma_s2mm_irq; + assign mb_axi_intr_s[4] = uart_irq; + assign mb_axi_intr_s[5] = gpio_lcd_irq; + assign mb_axi_intr_s[6] = gpio_sw_irq; + assign mb_axi_intr_s[7] = spdif_dma_irq; + + // ========================================================================== + // Common IRQ assignments + // ========================================================================== + + assign mb_axi_intr_s[8] = hdmi_dma_irq; + assign mb_axi_intr_s[9] = iic_irq; + assign ps7_irq_f2p_s[0] = hdmi_dma_irq; + assign ps7_irq_f2p_s[1] = iic_irq; + + // Device's DMA interrupts + + genvar i; + + generate + for(i=0; i < C_DEVICE_NR; i=i+1) begin : DEVICE_IRQ + assign mb_axi_intr_s[DEVICE_OFFSET_MB+i] = (i == 0) ? dev0_dma_irq : + (i == 1) ? dev1_dma_irq : + (i == 2) ? dev2_dma_irq : + (i == 3) ? dev3_dma_irq : + (i == 4) ? dev4_dma_irq : + (i == 5) ? dev5_dma_irq : 1'b0; + assign ps7_irq_f2p_s[DEVICE_OFFSET_ZQ+i] = (i == 0) ? dev0_dma_irq : + (i == 1) ? dev1_dma_irq : + (i == 2) ? dev2_dma_irq : + (i == 3) ? dev3_dma_irq : + (i == 4) ? dev4_dma_irq : + (i == 5) ? dev5_dma_irq : 1'b0; + end + endgenerate + + // Additional external SPI interrupts + + generate + for(i=0; i < C_XSPI_NR; i=i+1) begin : XSPI_NR + assign mb_axi_intr_s[XSPI_OFFSET_MB+i] = (i == 0) ? spi0_irq : + (i == 1) ? spi1_irq : + (i == 2) ? spi2_irq : + (i == 3) ? spi3_irq : 1'b0; + assign ps7_irq_f2p_s[XSPI_OFFSET_ZQ+i] = (i == 0) ? spi0_irq : + (i == 1) ? spi1_irq : + (i == 2) ? spi2_irq : + (i == 3) ? spi3_irq : 1'b0; + end + endgenerate + + // Additional external GPIO interrupts + + generate + for(i=0; i < C_XGPIO_NR; i=i+1) begin : XGPIO_IRQ + assign mb_axi_intr_s[XGPIO_OFFSET_MB+i] = (i == 0) ? gpio0_irq : + (i == 1) ? gpio1_irq : + (i == 2) ? gpio2_irq : + (i == 3) ? gpio3_irq : 1'b0; + assign ps7_irq_f2p_s[XGPIO_OFFSET_ZQ+i] = (i == 0) ? gpio0_irq : + (i == 1) ? gpio1_irq : + (i == 2) ? gpio2_irq : + (i == 3) ? gpio3_irq : 1'b0; + end + endgenerate + + + assign mb_axi_intr_s[31:IRQ_NUMBER_MB] = 'b0; + assign ps7_irq_f2p_s[15:IRQ_NUMBER_ZQ] = 'b0; + + // output logic + + // ZYNQ interrupts are assigned from top to down + generate + for(i=0; i < IRQ_F2P_WIDTH; i=i+1) begin : REVERSE_IRQ_ZYNQ + assign ps7_irq_f2p_inv_s[i] = ps7_irq_f2p_s[(IRQ_F2P_WIDTH-1)-i]; + end + endgenerate + + assign mb_axi_intr = (C_PROC_TYPE == MBLAZE) ? mb_axi_intr_s : 32'b0; + assign ps7_irq_f2p = (C_PROC_TYPE == ZYNQ) ? ps7_irq_f2p_inv_s : 16'b0; + +endmodule diff --git a/library/common/up_axi.v b/library/common/up_axi.v index 8fe2c84bc..e06c47e2b 100644 --- a/library/common/up_axi.v +++ b/library/common/up_axi.v @@ -135,7 +135,7 @@ module up_axi ( reg up_rsel = 'd0; reg up_rreq = 'd0; reg [AW:0] up_raddr = 'd0; - reg [ 2:0] up_rcount = 'd0; + reg [ 3:0] up_rcount = 'd0; reg up_rack_int = 'd0; reg [31:0] up_rdata_int = 'd0; reg up_rack_int_d = 'd0; @@ -245,12 +245,17 @@ module up_axi ( end up_rreq <= 1'b0; up_raddr <= up_raddr; - up_rcount <= up_rcount + 1'b1; end else begin up_rsel <= up_axi_arvalid; up_rreq <= up_axi_arvalid; up_raddr <= up_axi_araddr[AW+2:2]; - up_rcount <= 3'd0; + end + if (up_rack_int == 1'b1) begin + up_rcount <= 4'd0; + end else if (up_rcount[3] == 1'b1) begin + up_rcount <= up_rcount + 1'b1; + end else if (up_rreq == 1'b1) begin + up_rcount <= 4'd8; end end end @@ -262,10 +267,10 @@ module up_axi ( up_rack_int_d <= 'd0; up_rdata_int_d <= 'd0; end else begin - if ((up_rcount == 3'h7) && (up_rack == 1'b0)) begin + if ((up_rcount == 4'hf) && (up_rack == 1'b0)) begin up_rack_int <= 1'b1; up_rdata_int <= {2{16'hdead}}; - end else if (up_rsel == 1'b1) begin + end else begin up_rack_int <= up_rack; up_rdata_int <= up_rdata; end diff --git a/projects/ad9434_fmc/common/ad9434_bd.tcl b/projects/ad9434_fmc/common/ad9434_bd.tcl index 9940eca4d..f6a09d1ac 100644 --- a/projects/ad9434_fmc/common/ad9434_bd.tcl +++ b/projects/ad9434_fmc/common/ad9434_bd.tcl @@ -86,7 +86,7 @@ connect_bd_net -net axi_ad9434_denable [get_bd_pins axi_ad9434/adc_valid] [g connect_bd_net -net axi_ad9434_data [get_bd_pins axi_ad9434/adc_data] [get_bd_pins axi_ad9434_dma/fifo_wr_din] connect_bd_net -net axi_ad9434_ovf [get_bd_pins axi_ad9434/adc_dovf] [get_bd_pins axi_ad9434_dma/fifo_wr_overflow] -connect_bd_net -net axi_ad9434_dma_irq [get_bd_pins axi_ad9434_dma/irq] [get_bd_pins sys_concat_intc/In2] +connect_bd_net -net axi_ad9434_dma_irq [get_bd_pins axi_ad9434_dma/irq] [get_bd_pins sys_concat_intc/In13] # cpu interconnect diff --git a/projects/ad9625_fmc/common/ad9625_fmc_bd.tcl b/projects/ad9625_fmc/common/ad9625_fmc_bd.tcl index 61797156c..472edd928 100644 --- a/projects/ad9625_fmc/common/ad9625_fmc_bd.tcl +++ b/projects/ad9625_fmc/common/ad9625_fmc_bd.tcl @@ -25,6 +25,10 @@ set rx_sysref [create_bd_port -dir O rx_sysref] set rx_data_p [create_bd_port -dir I -from 7 -to 0 rx_data_p] set rx_data_n [create_bd_port -dir I -from 7 -to 0 rx_data_n] +set ad9625_spi_intr [create_bd_port -dir O ad9625_spi_intr] +set ad9625_gpio_intr [create_bd_port -dir O ad9625_gpio_intr] +set ad9625_dma_intr [create_bd_port -dir O ad9625_dma_intr] + if {$sys_zynq == 0} { set gpio_ad9625_i [create_bd_port -dir I -from 1 -to 0 gpio_ad9625_i] @@ -84,6 +88,8 @@ if {$sys_zynq == 1} { connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins axi_ad9625_fifo/sys_clk] } else { + + p_sys_dmafifo [current_bd_instance .] axi_ad9625_fifo 256 } # spi @@ -123,10 +129,6 @@ if {$sys_zynq == 1} { set_property -dict [list CONFIG.NUM_MI {13}] $axi_cpu_interconnect set_property -dict [list CONFIG.NUM_SI {10}] $axi_mem_interconnect - set_property -dict [list CONFIG.NUM_PORTS {7}] $sys_concat_intc - - delete_bd_objs [get_bd_nets sys_concat_intc_din_2] - delete_bd_objs [get_bd_ports unc_int2] } # connections (spi and gpio) @@ -156,19 +158,8 @@ if {$sys_zynq == 1 } { connect_bd_net -net gpio_ad9625_o [get_bd_ports gpio_ad9625_o] [get_bd_pins axi_ad9625_gpio/gpio_io_o] connect_bd_net -net gpio_ad9625_t [get_bd_ports gpio_ad9625_t] [get_bd_pins axi_ad9625_gpio/gpio_io_t] - connect_bd_net -net axi_ad9625_spi_irq [get_bd_pins axi_ad9625_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In10] - connect_bd_net -net axi_ad9625_gpio_irq [get_bd_pins axi_ad9625_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In9] -} - -if {$sys_zynq == 1 } { - - set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2] - set sys_fmc_dma_resetn_source [get_bd_pins sys_ps7/FCLK_RESET2_N] - - connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source - -} else { + connect_bd_net -net axi_ad9625_spi_intr [get_bd_pins axi_ad9625_spi/ip2intc_irpt] [get_bd_ports ad9625_spi_intr] + connect_bd_net -net axi_ad9625_gpio_intr [get_bd_pins axi_ad9625_gpio/ip2intc_irpt] [get_bd_ports ad9625_gpio_intr] } # connections (gt) @@ -188,7 +179,7 @@ connect_bd_net -net axi_ad9625_gt_rx_clk [get_bd_pins axi_ad9625_jesd/rx_core_cl connect_bd_net -net axi_ad9625_gt_rx_rst [get_bd_pins axi_ad9625_gt/rx_rst] connect_bd_net -net axi_ad9625_gt_rx_rst [get_bd_pins axi_ad9625_jesd/rx_reset] connect_bd_net -net axi_ad9625_gt_rx_rst [get_bd_pins axi_ad9625_fifo/adc_rst] [get_bd_pins axi_ad9625_gt/rx_rst] -connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9625_fifo/dma_rstn] $sys_fmc_dma_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_fifo/dma_rstn] $sys_100m_resetn_source connect_bd_net -net axi_ad9625_gt_rx_sysref [get_bd_pins axi_ad9625_jesd/rx_sysref] connect_bd_net -net axi_ad9625_gt_rx_gt_charisk [get_bd_pins axi_ad9625_gt/rx_gt_charisk] [get_bd_pins axi_ad9625_jesd/gt_rxcharisk_in] @@ -206,11 +197,16 @@ connect_bd_net -net axi_ad9625_adc_enable [get_bd_pins axi_ad9625_core connect_bd_net -net axi_ad9625_adc_data [get_bd_pins axi_ad9625_core/adc_data] [get_bd_pins axi_ad9625_fifo/adc_wdata] connect_bd_net -net axi_ad9625_adc_dovf [get_bd_pins axi_ad9625_core/adc_dovf] [get_bd_pins axi_ad9625_fifo/adc_wovf] -connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9625_fifo/dma_clk] [get_bd_pins axi_ad9625_dma/s_axis_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_fifo/dma_clk] [get_bd_pins axi_ad9625_dma/s_axis_aclk] connect_bd_net -net axi_ad9625_dma_dvalid [get_bd_pins axi_ad9625_fifo/dma_wvalid] [get_bd_pins axi_ad9625_dma/s_axis_valid] connect_bd_net -net axi_ad9625_dma_dready [get_bd_pins axi_ad9625_fifo/dma_wready] [get_bd_pins axi_ad9625_dma/s_axis_ready] connect_bd_net -net axi_ad9625_dma_ddata [get_bd_pins axi_ad9625_fifo/dma_wdata] [get_bd_pins axi_ad9625_dma/s_axis_data] -connect_bd_net -net axi_ad9625_dma_irq [get_bd_pins axi_ad9625_dma/irq] [get_bd_pins sys_concat_intc/In13] +connect_bd_net -net axi_ad9625_dma_intr [get_bd_pins axi_ad9625_dma/irq] [get_bd_ports ad9625_dma_intr] + +if {$sys_zynq == 0} { + + connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9625_fifo/axi_clk] $sys_200m_clk_source +} # interconnect (cpu) @@ -267,7 +263,7 @@ if {$sys_zynq == 1} { } else { connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_ad9625_gt/m_axi] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_100m_clk_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_100m_resetn_source } @@ -281,15 +277,15 @@ if {$sys_zynq == 1} { connect_bd_intf_net -intf_net axi_ad9625_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9625_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2] connect_bd_intf_net -intf_net axi_ad9625_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9625_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9625_dma/m_dest_axi] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9625_dma_interconnect/ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9625_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9625_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9625_dma/m_dest_axi_aclk] - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9625_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9625_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9625_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9625_dma/m_dest_axi_aresetn] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_dma_interconnect/ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_dma_interconnect/M00_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_dma_interconnect/S00_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_dma/m_dest_axi_aclk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_dma_interconnect/ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_dma_interconnect/M00_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_dma_interconnect/S00_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_dma/m_dest_axi_aresetn] } else { @@ -338,4 +334,5 @@ if {$sys_zynq == 1} { create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9625_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9625_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl + create_bd_addr_seg -range 0x00200000 -offset 0xc0000000 [get_bd_addr_spaces axi_ad9625_fifo/axi_fifo2s/axi] [get_bd_addr_segs axi_ad9625_fifo/axi_bram_ctl/S_AXI/Mem0] SEG_axi_bram_ctl_mem } diff --git a/projects/ad9625_fmc/vc707/system_bd.tcl b/projects/ad9625_fmc/vc707/system_bd.tcl index f112c6f5f..1bd293548 100644 --- a/projects/ad9625_fmc/vc707/system_bd.tcl +++ b/projects/ad9625_fmc/vc707/system_bd.tcl @@ -3,50 +3,4 @@ source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl source ../common/ad9625_fmc_bd.tcl -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9625_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma - -p_sys_dmafifo [current_bd_instance .] sys_dmafifo 256 - -delete_bd_objs [get_bd_nets axi_ad9625_adc_clk] -delete_bd_objs [get_bd_nets axi_ad9625_adc_enable] -delete_bd_objs [get_bd_nets axi_ad9625_adc_data] -delete_bd_objs [get_bd_nets axi_ad9625_adc_dovf] -delete_bd_objs [get_bd_nets axi_ad9625_adc_valid] - -connect_bd_net -net sys_200m_clk [get_bd_pins sys_dmafifo/axi_clk] $sys_200m_clk_source -connect_bd_net -net sys_200m_clk [get_bd_pins sys_dmafifo/dma_clk] $sys_200m_clk_source -connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9625_dma/fifo_wr_clk] $sys_200m_clk_source - -connect_bd_net -net [get_bd_nets axi_ad9625_gt_rx_rst] [get_bd_pins sys_dmafifo/adc_rst] [get_bd_pins axi_ad9625_gt/rx_rst] -connect_bd_net -net [get_bd_nets sys_200m_resetn] [get_bd_pins sys_dmafifo/dma_rstn] $sys_200m_resetn_source -connect_bd_net -net axi_ad9625_dma_xfer_req [get_bd_pins axi_ad9625_dma/fifo_wr_xfer_req] [get_bd_pins sys_dmafifo/axi_xfer_req] - -connect_bd_net -net axi_ad9625_adc_clk [get_bd_pins axi_ad9625_core/adc_clk] [get_bd_pins sys_dmafifo/adc_clk] -connect_bd_net -net axi_ad9625_adc_enable [get_bd_pins axi_ad9625_core/adc_enable] [get_bd_pins sys_dmafifo/adc_wr] -connect_bd_net -net axi_ad9625_adc_data [get_bd_pins axi_ad9625_core/adc_data] [get_bd_pins sys_dmafifo/adc_wdata] -connect_bd_net -net axi_ad9625_adc_dovf [get_bd_pins axi_ad9625_core/adc_dovf] [get_bd_pins sys_dmafifo/adc_wovf] - -connect_bd_net -net axi_ad9625_dma_dwr [get_bd_pins sys_dmafifo/dma_wr] [get_bd_pins axi_ad9625_dma/fifo_wr_en] -connect_bd_net -net axi_ad9625_dma_ddata [get_bd_pins sys_dmafifo/dma_wdata] [get_bd_pins axi_ad9625_dma/fifo_wr_din] -connect_bd_net -net axi_ad9625_dma_dovf [get_bd_pins sys_dmafifo/dma_wovf] [get_bd_pins axi_ad9625_dma/fifo_wr_overflow] -connect_bd_net -net axi_ad9625_adc_valid [get_bd_pins axi_ad9625_core/adc_valid] [get_bd_pins axi_ad9625_dma/fifo_wr_sync] - -connect_bd_net -net axi_ad9625_adc_data [get_bd_pins ila_jesd_rx_mon/PROBE3] - -set ila_dma_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_dma_mon] -set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_dma_mon -set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_dma_mon -set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_dma_mon -set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_dma_mon -set_property -dict [list CONFIG.C_PROBE2_WIDTH {64}] $ila_dma_mon -set_property -dict [list CONFIG.C_PROBE3_WIDTH {5}] $ila_dma_mon - -connect_bd_net -net sys_200m_clk [get_bd_pins ila_dma_mon/clk] -connect_bd_net -net axi_ad9625_dma_dwr [get_bd_pins ila_dma_mon/probe0] -connect_bd_net -net axi_ad9625_dma_xfer_req [get_bd_pins ila_dma_mon/probe1] -connect_bd_net -net axi_ad9625_dma_ddata [get_bd_pins ila_dma_mon/probe2] -connect_bd_net -net axi_xfer_status [get_bd_pins ila_dma_mon/probe3] [get_bd_pins sys_dmafifo/axi_xfer_status] - -create_bd_addr_seg -range 0x00200000 -offset 0xc0000000 [get_bd_addr_spaces sys_dmafifo/axi_fifo2s/axi] [get_bd_addr_segs sys_dmafifo/axi_bram_ctl/S_AXI/Mem0] SEG_axi_bram_ctl_mem diff --git a/projects/ad9625_fmc/vc707/system_constr.xdc b/projects/ad9625_fmc/vc707/system_constr.xdc index 64538cecc..97f5b442c 100644 --- a/projects/ad9625_fmc/vc707/system_constr.xdc +++ b/projects/ad9625_fmc/vc707/system_constr.xdc @@ -39,12 +39,3 @@ set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVCMOS18} [get_ports adc_fd] create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p] create_clock -name rx_div_clk -period 6.40 [get_nets i_system_wrapper/system_i/axi_ad9625_gt_rx_clk] -set_clock_groups -asynchronous -group {rx_div_clk} - -set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE] - diff --git a/projects/ad9625_fmc/vc707/system_project.tcl b/projects/ad9625_fmc/vc707/system_project.tcl index be837057d..2ca3057b1 100644 --- a/projects/ad9625_fmc/vc707/system_project.tcl +++ b/projects/ad9625_fmc/vc707/system_project.tcl @@ -12,6 +12,9 @@ adi_project_files ad9625_fmc_vc707 [list \ "system_constr.xdc"\ "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ] +set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc] +set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] + adi_project_run ad9625_fmc_vc707 diff --git a/projects/ad9625_fmc/vc707/system_top.v b/projects/ad9625_fmc/vc707/system_top.v index 168ebddc4..d898b52a1 100644 --- a/projects/ad9625_fmc/vc707/system_top.v +++ b/projects/ad9625_fmc/vc707/system_top.v @@ -185,15 +185,16 @@ module system_top ( // internal signals - wire [1:0] gpio_i; - wire [1:0] gpio_o; - wire [1:0] gpio_t; + wire [ 1:0] gpio_i; + wire [ 1:0] gpio_o; + wire [ 1:0] gpio_t; wire rx_ref_clk; wire rx_sysref; wire rx_sync; wire spi_clk; wire spi_miso; wire spi_mosi; + wire [31:0] mb_intrs; // instantiations @@ -233,7 +234,12 @@ module system_top ( .spi_adc_sdio (spi_adc_sdio), .spi_clk_sdio (spi_clk_sdio)); + assign fan_pwm = 1'b1; + system_wrapper i_system_wrapper ( + .ad9625_dma_intr (mb_intrs[13]), + .ad9625_gpio_intr (mb_intrs[12]), + .ad9625_spi_intr (mb_intrs[11]), .ddr3_addr (ddr3_addr), .ddr3_ba (ddr3_ba), .ddr3_cas_n (ddr3_cas_n), @@ -249,7 +255,6 @@ module system_top ( .ddr3_ras_n (ddr3_ras_n), .ddr3_reset_n (ddr3_reset_n), .ddr3_we_n (ddr3_we_n), - .fan_pwm (fan_pwm), .gpio_lcd_tri_o (gpio_lcd), .gpio_led_tri_o (gpio_led), .gpio_sw_tri_i (gpio_sw), @@ -261,11 +266,34 @@ module system_top ( .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), .iic_rstn (iic_rstn), + .mb_intr_10 (mb_intrs[10]), + .mb_intr_11 (mb_intrs[11]), + .mb_intr_12 (mb_intrs[12]), + .mb_intr_13 (mb_intrs[13]), + .mb_intr_14 (mb_intrs[14]), + .mb_intr_15 (mb_intrs[15]), + .mb_intr_16 (mb_intrs[16]), + .mb_intr_17 (mb_intrs[17]), + .mb_intr_18 (mb_intrs[18]), + .mb_intr_19 (mb_intrs[19]), + .mb_intr_20 (mb_intrs[20]), + .mb_intr_21 (mb_intrs[21]), + .mb_intr_22 (mb_intrs[22]), + .mb_intr_23 (mb_intrs[23]), + .mb_intr_24 (mb_intrs[24]), + .mb_intr_25 (mb_intrs[25]), + .mb_intr_26 (mb_intrs[26]), + .mb_intr_27 (mb_intrs[27]), + .mb_intr_28 (mb_intrs[28]), + .mb_intr_29 (mb_intrs[29]), + .mb_intr_30 (mb_intrs[30]), + .mb_intr_31 (mb_intrs[31]), .mdio_mdc (mdio_mdc), .mdio_mdio_io (mdio_mdio), .mgt_clk_clk_n (mgt_clk_n), .mgt_clk_clk_p (mgt_clk_p), .phy_rstn (phy_rstn), + .phy_sd (1'b1), .sgmii_rxn (sgmii_rxn), .sgmii_rxp (sgmii_rxp), .sgmii_txn (sgmii_txn), diff --git a/projects/adv7511/ac701/system_bd.tcl b/projects/adv7511/ac701/system_bd.tcl index bf73139e8..60356edce 100644 --- a/projects/adv7511/ac701/system_bd.tcl +++ b/projects/adv7511/ac701/system_bd.tcl @@ -3,4 +3,4 @@ source $ad_hdl_dir/projects/common/ac701/ac701_system_bd.tcl set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect set_property -dict [list CONFIG.NUM_SI {8}] $axi_mem_interconnect set_property -dict [list CONFIG.NUM_MI {1}] $axi_mem_interconnect -set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc + diff --git a/projects/adv7511/ac701/system_project.tcl b/projects/adv7511/ac701/system_project.tcl index a2d89941a..1f86497b7 100644 --- a/projects/adv7511/ac701/system_project.tcl +++ b/projects/adv7511/ac701/system_project.tcl @@ -7,7 +7,8 @@ source $ad_hdl_dir/projects/scripts/adi_project.tcl adi_project_create adv7511_ac701 adi_project_files adv7511_ac701 [list \ "system_top.v" \ - "$ad_hdl_dir/projects/common/ac701/ac701_system_constr.xdc" ] + "$ad_hdl_dir/projects/common/ac701/ac701_system_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_interrupts.v"] adi_project_run adv7511_ac701 diff --git a/projects/adv7511/ac701/system_top.v b/projects/adv7511/ac701/system_top.v index 140431c52..ffb71597a 100644 --- a/projects/adv7511/ac701/system_top.v +++ b/projects/adv7511/ac701/system_top.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,16 +21,16 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** @@ -147,6 +147,48 @@ module system_top ( assign mgt_clk_sel = 2'd0; + wire timer_irq; + wire eth_irq; + wire eth_dma_mm2s_irq; + wire eth_dma_s2mm_irq; + wire uart_irq; + wire gpio_lcd_irq; + wire gpio_sw_irq; + wire spdif_dma_irq; + wire iic_irq; + wire hdmi_dma_irq; + wire [31:0] mb_axi_intr; + + ad_interrupts #( + .C_PROC_TYPE(0) + ) i_ad_interrupts ( + .timer_irq(timer_irq), + .eth_irq(eth_irq), + .eth_dma_mm2s_irq(eth_dma_mm2s), + .eth_dma_s2mm_irq(eth_dma_s2mm), + .uart_irq(uart_irq), + .gpio_lcd_irq(gpio_lcd_irq), + .gpio_sw_irq(gpio_sw_irq), + .spdif_dma_irq(spdif_dma_irq), + .hdmi_dma_irq(hdmi_dma_irq), + .iic_irq(iic_irq), + .dev0_dma_irq(1'b0), + .dev1_dma_irq(1'b0), + .dev2_dma_irq(1'b0), + .dev3_dma_irq(1'b0), + .dev4_dma_irq(1'b0), + .dev5_dma_irq(1'b0), + .spi0_irq(1'b0), + .spi1_irq(1'b0), + .spi2_irq(1'b0), + .spi3_irq(1'b0), + .gpio0_irq(1'b0), + .gpio1_irq(1'b0), + .gpio2_irq(1'b0), + .gpio3_irq(1'b0), + .mb_axi_intr(mb_axi_intr), + .ps7_irq_f2p()); + // instantiations system_wrapper i_system_wrapper ( @@ -191,7 +233,18 @@ module system_top ( .sys_clk_p (sys_clk_p), .sys_rst (sys_rst), .uart_sin (uart_sin), - .uart_sout (uart_sout)); + .uart_sout (uart_sout), + .timer_irq (timer_irq), + .eth_irq (eth_irq), + .eth_dma_mm2s_irq (eth_dma_mm2s_irq), + .eth_dma_s2mm_irq (eth_dma_s2mm_irq), + .uart_irq (uart_irq), + .gpio_lcd_irq (gpio_lcd_irq), + .gpio_sw_irq (gpio_sw_irq), + .spdif_dma_irq (spdif_dma_irq), + .iic_irq (iic_irq), + .hdmi_dma_irq (hdmi_dma_irq), + .mb_axi_intr (mb_axi_intr)); endmodule diff --git a/projects/adv7511/kc705/system_bd.tcl b/projects/adv7511/kc705/system_bd.tcl index 2b51545f4..4b4831918 100755 --- a/projects/adv7511/kc705/system_bd.tcl +++ b/projects/adv7511/kc705/system_bd.tcl @@ -3,5 +3,4 @@ source $ad_hdl_dir/projects/common/kc705/kc705_system_bd.tcl set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect set_property -dict [list CONFIG.NUM_SI {8}] $axi_mem_interconnect set_property -dict [list CONFIG.NUM_MI {1}] $axi_mem_interconnect -set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc diff --git a/projects/adv7511/kc705/system_project.tcl b/projects/adv7511/kc705/system_project.tcl index 656033b8e..bd1ba6947 100755 --- a/projects/adv7511/kc705/system_project.tcl +++ b/projects/adv7511/kc705/system_project.tcl @@ -7,7 +7,8 @@ source $ad_hdl_dir/projects/scripts/adi_project.tcl adi_project_create adv7511_kc705 adi_project_files adv7511_kc705 [list \ "system_top.v" \ - "$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc" ] + "$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_interrupts.v"] adi_project_run adv7511_kc705 diff --git a/projects/adv7511/kc705/system_top.v b/projects/adv7511/kc705/system_top.v index f436fa348..84702e418 100644 --- a/projects/adv7511/kc705/system_top.v +++ b/projects/adv7511/kc705/system_top.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,16 +21,16 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** @@ -153,6 +153,46 @@ module system_top ( output spdif; + wire timer_irq; + wire eth_irq; + wire uart_irq; + wire gpio_lcd_irq; + wire gpio_sw_irq; + wire spdif_dma_irq; + wire iic_irq; + wire hdmi_dma_irq; + wire [31:0] mb_axi_intr; + + ad_interrupts #( + .C_PROC_TYPE(0) + ) i_ad_interrupts ( + .timer_irq(timer_irq), + .eth_irq(eth_irq), + .eth_dma_mm2s_irq(), + .eth_dma_s2mm_irq(), + .uart_irq(uart_irq), + .gpio_lcd_irq(gpio_lcd_irq), + .gpio_sw_irq(gpio_sw_irq), + .spdif_dma_irq(spdif_dma_irq), + .hdmi_dma_irq(hdmi_dma_irq), + .iic_irq(iic_irq), + .dev0_dma_irq(1'b0), + .dev1_dma_irq(1'b0), + .dev2_dma_irq(1'b0), + .dev3_dma_irq(1'b0), + .dev4_dma_irq(1'b0), + .dev5_dma_irq(1'b0), + .spi0_irq(1'b0), + .spi1_irq(1'b0), + .spi2_irq(1'b0), + .spi3_irq(1'b0), + .gpio0_irq(1'b0), + .gpio1_irq(1'b0), + .gpio2_irq(1'b0), + .gpio3_irq(1'b0), + .mb_axi_intr(mb_axi_intr), + .ps7_irq_f2p()); + // instantiations system_wrapper i_system_wrapper ( @@ -203,10 +243,15 @@ module system_top ( .sys_rst (sys_rst), .uart_sin (uart_sin), .uart_sout (uart_sout), - .unc_int0 (1'b0), - .unc_int1 (1'b0), - .unc_int2 (1'b0), - .unc_int3 (1'b0)); + .timer_irq (timer_irq), + .eth_irq (eth_irq), + .uart_irq (uart_irq), + .gpio_lcd_irq (gpio_lcd_irq), + .gpio_sw_irq (gpio_sw_irq), + .spdif_dma_irq (spdif_dma_irq), + .iic_irq (iic_irq), + .hdmi_dma_irq (hdmi_dma_irq), + .mb_axi_intr (mb_axi_intr)); endmodule diff --git a/projects/adv7511/kcu105/system_project.tcl b/projects/adv7511/kcu105/system_project.tcl index 840298b7a..0c71fa656 100755 --- a/projects/adv7511/kcu105/system_project.tcl +++ b/projects/adv7511/kcu105/system_project.tcl @@ -5,7 +5,8 @@ source $ad_hdl_dir/projects/scripts/adi_project.tcl adi_project_create adv7511_kcu105 adi_project_files adv7511_kcu105 [list \ "system_top.v" \ - "$ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc" ] + "$ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_interrupts.v"] adi_project_run adv7511_kcu105 diff --git a/projects/adv7511/kcu105/system_top.v b/projects/adv7511/kcu105/system_top.v index 56d560b5a..5c447cab3 100644 --- a/projects/adv7511/kcu105/system_top.v +++ b/projects/adv7511/kcu105/system_top.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,16 +21,16 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** @@ -79,7 +79,6 @@ module system_top ( gpio_led, gpio_sw, - iic_rstn, iic_scl, iic_sda, @@ -129,7 +128,6 @@ module system_top ( inout [ 7:0] gpio_led; inout [ 8:0] gpio_sw; - output iic_rstn; inout iic_scl; inout iic_sda; @@ -145,6 +143,48 @@ module system_top ( assign fan_pwm = 1'b1; + wire timer_irq; + wire eth_irq; + wire eth_dma_mm2s_irq; + wire eth_dma_s2mm_irq; + wire uart_irq; + wire gpio_lcd_irq; + wire gpio_sw_irq; + wire spdif_dma_irq; + wire iic_irq; + wire hdmi_dma_irq; + wire [31:0] mb_axi_intr; + + ad_interrupts #( + .C_PROC_TYPE(0) + ) i_ad_interrupts ( + .timer_irq(timer_irq), + .eth_irq(eth_irq), + .eth_dma_mm2s_irq(eth_dma_mm2s), + .eth_dma_s2mm_irq(eth_dma_s2mm), + .uart_irq(uart_irq), + .gpio_lcd_irq(gpio_lcd_irq), + .gpio_sw_irq(gpio_sw_irq), + .spdif_dma_irq(spdif_dma_irq), + .hdmi_dma_irq(hdmi_dma_irq), + .iic_irq(iic_irq), + .dev0_dma_irq(1'b0), + .dev1_dma_irq(1'b0), + .dev2_dma_irq(1'b0), + .dev3_dma_irq(1'b0), + .dev4_dma_irq(1'b0), + .dev5_dma_irq(1'b0), + .spi0_irq(1'b0), + .spi1_irq(1'b0), + .spi2_irq(1'b0), + .spi3_irq(1'b0), + .gpio0_irq(1'b0), + .gpio1_irq(1'b0), + .gpio2_irq(1'b0), + .gpio3_irq(1'b0), + .mb_axi_intr(mb_axi_intr), + .ps7_irq_f2p()); + // instantiations system_wrapper i_system_wrapper ( @@ -173,7 +213,6 @@ module system_top ( .hdmi_vsync (hdmi_vsync), .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), - .iic_rstn (iic_rstn), .mdio_mdc (mdio_mdc), .mdio_mdio_io (mdio_mdio), .phy_clk_clk_n (phy_clk_n), @@ -190,9 +229,17 @@ module system_top ( .sys_rst (sys_rst), .uart_sin (uart_sin), .uart_sout (uart_sout), - .unc_int2 (1'b0), - .unc_int3 (1'b0), - .unc_int4 (1'b0)); + .timer_irq (timer_irq), + .eth_irq (eth_irq), + .eth_dma_mm2s_irq (eth_dma_mm2s_irq), + .eth_dma_s2mm_irq (eth_dma_s2mm_irq), + .uart_irq (uart_irq), + .gpio_lcd_irq (gpio_lcd_irq), + .gpio_sw_irq (gpio_sw_irq), + .spdif_dma_irq (spdif_dma_irq), + .iic_irq (iic_irq), + .hdmi_dma_irq (hdmi_dma_irq), + .mb_axi_intr (mb_axi_intr)); endmodule diff --git a/projects/adv7511/vc707/system_bd.tcl b/projects/adv7511/vc707/system_bd.tcl index 92c6ca7f9..8c0a24c87 100644 --- a/projects/adv7511/vc707/system_bd.tcl +++ b/projects/adv7511/vc707/system_bd.tcl @@ -3,6 +3,5 @@ source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect set_property -dict [list CONFIG.NUM_SI {8}] $axi_mem_interconnect set_property -dict [list CONFIG.NUM_MI {1}] $axi_mem_interconnect -set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc diff --git a/projects/adv7511/vc707/system_project.tcl b/projects/adv7511/vc707/system_project.tcl index 64194c363..fd5ff0d22 100644 --- a/projects/adv7511/vc707/system_project.tcl +++ b/projects/adv7511/vc707/system_project.tcl @@ -5,7 +5,8 @@ source ${ad_hdl_dir}/projects/scripts/adi_project.tcl adi_project_create adv7511_vc707 adi_project_files adv7511_vc707 [list \ "system_top.v" \ - "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ] + "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_interrupts.v"] adi_project_run adv7511_vc707 diff --git a/projects/adv7511/vc707/system_top.v b/projects/adv7511/vc707/system_top.v index d4cd7a819..d224f8e6b 100644 --- a/projects/adv7511/vc707/system_top.v +++ b/projects/adv7511/vc707/system_top.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,16 +21,16 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** @@ -145,6 +145,48 @@ module system_top ( output spdif; + wire timer_irq; + wire eth_irq; + wire eth_dma_mm2s_irq; + wire eth_dma_s2mm_irq; + wire uart_irq; + wire gpio_lcd_irq; + wire gpio_sw_irq; + wire spdif_dma_irq; + wire iic_irq; + wire hdmi_dma_irq; + wire [31:0] mb_axi_intr; + + ad_interrupts #( + .C_PROC_TYPE(0) + ) i_ad_interrupts ( + .timer_irq(timer_irq), + .eth_irq(eth_irq), + .eth_dma_mm2s_irq(eth_dma_mm2s), + .eth_dma_s2mm_irq(eth_dma_s2mm), + .uart_irq(uart_irq), + .gpio_lcd_irq(gpio_lcd_irq), + .gpio_sw_irq(gpio_sw_irq), + .spdif_dma_irq(spdif_dma_irq), + .hdmi_dma_irq(hdmi_dma_irq), + .iic_irq(iic_irq), + .dev0_dma_irq(1'b0), + .dev1_dma_irq(1'b0), + .dev2_dma_irq(1'b0), + .dev3_dma_irq(1'b0), + .dev4_dma_irq(1'b0), + .dev5_dma_irq(1'b0), + .spi0_irq(1'b0), + .spi1_irq(1'b0), + .spi2_irq(1'b0), + .spi3_irq(1'b0), + .gpio0_irq(1'b0), + .gpio1_irq(1'b0), + .gpio2_irq(1'b0), + .gpio3_irq(1'b0), + .mb_axi_intr(mb_axi_intr), + .ps7_irq_f2p()); + // instantiations system_wrapper i_system_wrapper ( @@ -189,7 +231,18 @@ module system_top ( .sys_clk_p (sys_clk_p), .sys_rst (sys_rst), .uart_sin (uart_sin), - .uart_sout (uart_sout)); + .uart_sout (uart_sout), + .timer_irq (timer_irq), + .eth_irq (eth_irq), + .eth_dma_mm2s_irq (eth_dma_mm2s_irq), + .eth_dma_s2mm_irq (eth_dma_s2mm_irq), + .uart_irq (uart_irq), + .gpio_lcd_irq (gpio_lcd_irq), + .gpio_sw_irq (gpio_sw_irq), + .spdif_dma_irq (spdif_dma_irq), + .iic_irq (iic_irq), + .hdmi_dma_irq (hdmi_dma_irq), + .mb_axi_intr (mb_axi_intr)); endmodule diff --git a/projects/adv7511/zc702/system_bd.tcl b/projects/adv7511/zc702/system_bd.tcl index e77b9effd..94515d698 100644 --- a/projects/adv7511/zc702/system_bd.tcl +++ b/projects/adv7511/zc702/system_bd.tcl @@ -2,7 +2,6 @@ source $ad_hdl_dir/projects/common/zc702/zc702_system_bd.tcl set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {32}] $sys_ps7 set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect -set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc set_property LEFT 31 [get_bd_ports GPIO_I] set_property LEFT 31 [get_bd_ports GPIO_O] diff --git a/projects/adv7511/zc702/system_project.tcl b/projects/adv7511/zc702/system_project.tcl index cac17146a..ad801bd6b 100644 --- a/projects/adv7511/zc702/system_project.tcl +++ b/projects/adv7511/zc702/system_project.tcl @@ -7,7 +7,9 @@ source $ad_hdl_dir/projects/scripts/adi_project.tcl adi_project_create adv7511_zc702 adi_project_files adv7511_zc702 [list \ "system_top.v" \ - "$ad_hdl_dir/projects/common/zc702/zc702_system_constr.xdc" ] + "$ad_hdl_dir/projects/common/zc702/zc702_system_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/common/ad_interrupts.v"] adi_project_run adv7511_zc702 diff --git a/projects/adv7511/zc702/system_top.v b/projects/adv7511/zc702/system_top.v index 2cdbf9583..590f2d89c 100644 --- a/projects/adv7511/zc702/system_top.v +++ b/projects/adv7511/zc702/system_top.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,16 +21,16 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** @@ -115,22 +115,53 @@ module system_top ( // internal signals - wire [31:0] gpio_i; - wire [31:0] gpio_o; - wire [31:0] gpio_t; + wire [15:0] gpio_i; + wire [15:0] gpio_o; + wire [15:0] gpio_t; + + wire hdmi_dma_irq; + wire iic_irq; + wire [15:0] ps7_irq_f2p; // instantiations - genvar n; - generate - for (n = 0; n <= 15; n = n + 1) begin: g_iobuf_gpio_bd - IOBUF i_iobuf_gpio_bd ( - .I (gpio_o[n]), - .O (gpio_i[n]), - .T (gpio_t[n]), - .IO (gpio_bd[n])); - end - endgenerate + ad_iobuf #( + .DATA_WIDTH(16) + ) i_gpio_bd ( + .dt(gpio_t), + .di(gpio_o), + .do(gpio_i), + .dio(gpio_bd)); + + ad_interrupts #( + .C_PROC_TYPE(1) + ) i_ad_interrupts ( + .timer_irq(1'b0), + .eth_irq(1'b0), + .eth_dma_mm2s_irq(1'b0), + .eth_dma_s2mm_irq(1'b0), + .uart_irq(1'b0), + .gpio_lcd_irq(1'b0), + .gpio_sw_irq(1'b0), + .spdif_dma_irq(1'b0), + .hdmi_dma_irq(hdmi_dma_irq), + .iic_irq(iic_irq), + .dev0_dma_irq(1'b0), + .dev1_dma_irq(1'b0), + .dev2_dma_irq(1'b0), + .dev3_dma_irq(1'b0), + .dev4_dma_irq(1'b0), + .dev5_dma_irq(1'b0), + .spi0_irq(1'b0), + .spi1_irq(1'b0), + .spi2_irq(1'b0), + .spi3_irq(1'b0), + .gpio0_irq(1'b0), + .gpio1_irq(1'b0), + .gpio2_irq(1'b0), + .gpio3_irq(1'b0), + .mb_axi_intr(), + .ps7_irq_f2p(ps7_irq_f2p)); system_wrapper i_system_wrapper ( .DDR_addr (DDR_addr), @@ -164,7 +195,10 @@ module system_top ( .hdmi_vsync (hdmi_vsync), .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), - .spdif (spdif)); + .spdif (spdif), + .hdmi_dma_irq (hdmi_dma_irq), + .iic_irq (iic_irq), + .ps7_irq_f2p (ps7_irq_f2p)); endmodule diff --git a/projects/adv7511/zc706/system_project.tcl b/projects/adv7511/zc706/system_project.tcl index b99b00274..4fa80af81 100644 --- a/projects/adv7511/zc706/system_project.tcl +++ b/projects/adv7511/zc706/system_project.tcl @@ -1,14 +1,13 @@ - - source ../../scripts/adi_env.tcl source $ad_hdl_dir/projects/scripts/adi_project.tcl adi_project_create adv7511_zc706 adi_project_files adv7511_zc706 [list \ "system_top.v" \ - "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] + "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/common/ad_interrupts.v"] adi_project_run adv7511_zc706 - diff --git a/projects/adv7511/zc706/system_top.v b/projects/adv7511/zc706/system_top.v index 8b6dba76f..321be14be 100644 --- a/projects/adv7511/zc706/system_top.v +++ b/projects/adv7511/zc706/system_top.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,16 +21,16 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** @@ -115,22 +115,53 @@ module system_top ( // internal signals - wire [31:0] gpio_i; - wire [31:0] gpio_o; - wire [31:0] gpio_t; + wire [14:0] gpio_i; + wire [14:0] gpio_o; + wire [14:0] gpio_t; + + wire hdmi_dma_irq; + wire iic_irq; + wire [15:0] ps7_irq_f2p; // instantiations - genvar n; - generate - for (n = 0; n <= 14; n = n + 1) begin: g_iobuf_gpio_bd - IOBUF i_iobuf_gpio_bd ( - .I (gpio_o[n]), - .O (gpio_i[n]), - .T (gpio_t[n]), - .IO (gpio_bd[n])); - end - endgenerate + ad_iobuf #( + .DATA_WIDTH(15) + ) i_gpio_bd ( + .dt(gpio_t), + .di(gpio_o), + .do(gpio_i), + .dio(gpio_bd)); + + ad_interrupts #( + .C_PROC_TYPE(1) + ) i_ad_interrupts ( + .timer_irq(1'b0), + .eth_irq(1'b0), + .eth_dma_mm2s_irq(1'b0), + .eth_dma_s2mm_irq(1'b0), + .uart_irq(1'b0), + .gpio_lcd_irq(1'b0), + .gpio_sw_irq(1'b0), + .spdif_dma_irq(1'b0), + .hdmi_dma_irq(hdmi_dma_irq), + .iic_irq(iic_irq), + .dev0_dma_irq(1'b0), + .dev1_dma_irq(1'b0), + .dev2_dma_irq(1'b0), + .dev3_dma_irq(1'b0), + .dev4_dma_irq(1'b0), + .dev5_dma_irq(1'b0), + .spi0_irq(1'b0), + .spi1_irq(1'b0), + .spi2_irq(1'b0), + .spi3_irq(1'b0), + .gpio0_irq(1'b0), + .gpio1_irq(1'b0), + .gpio2_irq(1'b0), + .gpio3_irq(1'b0), + .mb_axi_intr(), + .ps7_irq_f2p(ps7_irq_f2p)); system_wrapper i_system_wrapper ( .DDR_addr (DDR_addr), @@ -164,7 +195,10 @@ module system_top ( .hdmi_vsync (hdmi_vsync), .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), - .spdif (spdif)); + .spdif (spdif), + .hdmi_dma_irq (hdmi_dma_irq), + .iic_irq (iic_irq), + .ps7_irq_f2p (ps7_irq_f2p)); endmodule diff --git a/projects/common/ac701/ac701_system_bd.tcl b/projects/common/ac701/ac701_system_bd.tcl index 3f933e359..037f04f44 100644 --- a/projects/common/ac701/ac701_system_bd.tcl +++ b/projects/common/ac701/ac701_system_bd.tcl @@ -20,12 +20,6 @@ set iic_main [create_bd_intf_port -mode Master -vlnv xilinx.com:interface set uart_sin [create_bd_port -dir I uart_sin] set uart_sout [create_bd_port -dir O uart_sout] -set unc_int0 [create_bd_port -dir I unc_int0] -set unc_int1 [create_bd_port -dir I unc_int1] -set unc_int2 [create_bd_port -dir I unc_int2] -set unc_int3 [create_bd_port -dir I unc_int3] -set unc_int4 [create_bd_port -dir I unc_int4] - set hdmi_out_clk [create_bd_port -dir O hdmi_out_clk] set hdmi_hsync [create_bd_port -dir O hdmi_hsync] set hdmi_vsync [create_bd_port -dir O hdmi_vsync] @@ -38,6 +32,21 @@ set spdif [create_bd_port -dir O spdif] set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] $sys_rst +# interrupts + +set timer_irq [create_bd_port -dir O timer_irq] +set eth_irq [create_bd_port -dir O eth_irq] +set eth_dma_mm2s_irq [create_bd_port -dir O eth_dma_mm2s_irq] +set eth_dma_s2mm_irq [create_bd_port -dir O eth_dma_s2mm_irq] +set uart_irq [create_bd_port -dir O uart_irq] +set gpio_lcd_irq [create_bd_port -dir O gpio_lcd_irq] +set gpio_sw_irq [create_bd_port -dir O gpio_sw_irq] +set spdif_dma_irq [create_bd_port -dir O spdif_dma_irq] +set iic_irq [create_bd_port -dir O iic_irq] +set hdmi_dma_irq [create_bd_port -dir O hdmi_dma_irq] + +set mb_axi_intr [create_bd_port -dir I -from 31 -to 0 -type intr mb_axi_intr] + # instance: microblaze - processor set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.3 sys_mb] @@ -146,13 +155,6 @@ set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_sw_led set axi_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc] set_property -dict [list CONFIG.C_HAS_FAST {0}] $axi_intc -set sys_concat_aux_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_aux_intc] -set_property -dict [list CONFIG.NUM_PORTS {9}] $sys_concat_aux_intc -set_property -dict [list CONFIG.IN9_WIDTH {5}] $sys_concat_aux_intc - -set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc] -set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc - # hdmi peripherals set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen] @@ -206,8 +208,8 @@ connect_bd_intf_net -intf_net sys_mb_ilmb [get_bd_intf_pins sys_mb/ILMB] [get_bd connect_bd_intf_net -intf_net sys_mb_debug_intf [get_bd_intf_pins sys_mb_debug/MBDEBUG_0] [get_bd_intf_pins sys_mb/DEBUG] connect_bd_intf_net -intf_net sys_mb_interrupt [get_bd_intf_pins axi_intc/interrupt] [get_bd_intf_pins sys_mb/INTERRUPT] -connect_bd_net -net sys_concat_aux_intc_intr [get_bd_pins sys_concat_aux_intc/dout] [get_bd_pins axi_intc/intr] -connect_bd_net -net sys_concat_intc_intr [get_bd_pins sys_concat_intc/dout] [get_bd_pins sys_concat_aux_intc/In8] +connect_bd_net -net sys_concat_intr [get_bd_ports mb_axi_intr] [get_bd_pins axi_intc/intr] +set_property -dict [list CONFIG.PortWidth {32}] [get_bd_ports mb_axi_intr] # defaults (peripherals) @@ -340,19 +342,16 @@ connect_bd_intf_net -intf_net axi_ethernet_dma_rxs [get_bd_intf_pins axi_etherne # defaults (interrupts) -connect_bd_net -net sys_concat_aux_intc_intr_00 [get_bd_pins sys_concat_aux_intc/In0] [get_bd_pins axi_timer/interrupt] -connect_bd_net -net sys_concat_aux_intc_intr_01 [get_bd_pins sys_concat_aux_intc/In1] [get_bd_pins axi_ethernet/interrupt] -connect_bd_net -net sys_concat_aux_intc_intr_02 [get_bd_pins sys_concat_aux_intc/In2] [get_bd_pins axi_ethernet_dma/mm2s_introut] -connect_bd_net -net sys_concat_aux_intc_intr_03 [get_bd_pins sys_concat_aux_intc/In3] [get_bd_pins axi_ethernet_dma/s2mm_introut] -connect_bd_net -net sys_concat_aux_intc_intr_04 [get_bd_pins sys_concat_aux_intc/In4] [get_bd_pins axi_uart/interrupt] -connect_bd_net -net sys_concat_aux_intc_intr_05 [get_bd_pins sys_concat_aux_intc/In5] [get_bd_pins axi_gpio_lcd/ip2intc_irpt] -connect_bd_net -net sys_concat_aux_intc_intr_06 [get_bd_pins sys_concat_aux_intc/In6] [get_bd_pins axi_gpio_sw_led/ip2intc_irpt] -connect_bd_net -net sys_concat_aux_intc_intr_07 [get_bd_pins sys_concat_aux_intc/In7] [get_bd_pins axi_spdif_tx_dma/mm2s_introut] -connect_bd_net -net sys_concat_intc_din_0 [get_bd_pins sys_concat_intc/In0] [get_bd_pins axi_hdmi_dma/mm2s_introut] -connect_bd_net -net sys_concat_intc_din_1 [get_bd_pins sys_concat_intc/In1] [get_bd_pins axi_iic_main/iic2intc_irpt] -connect_bd_net -net sys_concat_intc_din_2 [get_bd_pins sys_concat_intc/In2] [get_bd_ports unc_int2] -connect_bd_net -net sys_concat_intc_din_3 [get_bd_pins sys_concat_intc/In3] [get_bd_ports unc_int3] -connect_bd_net -net sys_concat_intc_din_4 [get_bd_pins sys_concat_intc/In4] [get_bd_ports unc_int4] +connect_bd_net -net sys_base_intr_00 [get_bd_ports timer_irq] [get_bd_pins axi_timer/interrupt] +connect_bd_net -net sys_base_intr_01 [get_bd_ports eth_irq] [get_bd_pins axi_ethernet/interrupt] +connect_bd_net -net sys_base_intr_02 [get_bd_ports eth_dma_mm2s_irq] [get_bd_pins axi_ethernet_dma/mm2s_introut] +connect_bd_net -net sys_base_intr_03 [get_bd_ports eth_dma_s2mm_irq] [get_bd_pins axi_ethernet_dma/s2mm_introut] +connect_bd_net -net sys_base_intr_04 [get_bd_ports uart_irq] [get_bd_pins axi_uart/interrupt] +connect_bd_net -net sys_base_intr_05 [get_bd_ports gpio_lcd_irq] [get_bd_pins axi_gpio_lcd/ip2intc_irpt] +connect_bd_net -net sys_base_intr_06 [get_bd_ports gpio_sw_irq] [get_bd_pins axi_gpio_sw_led/ip2intc_irpt] +connect_bd_net -net sys_base_intr_07 [get_bd_ports spdif_dma_irq] [get_bd_pins axi_spdif_tx_dma/mm2s_introut] +connect_bd_net -net sys_base_intr_08 [get_bd_ports iic_irq] [get_bd_pins axi_hdmi_dma/mm2s_introut] +connect_bd_net -net sys_base_intr_09 [get_bd_ports hdmi_dma_irq] [get_bd_pins axi_iic_main/iic2intc_irpt] # defaults (external interface) diff --git a/projects/common/kc705/kc705_system_bd.tcl b/projects/common/kc705/kc705_system_bd.tcl index 86c0cd4ae..247caaf8b 100644 --- a/projects/common/kc705/kc705_system_bd.tcl +++ b/projects/common/kc705/kc705_system_bd.tcl @@ -24,12 +24,6 @@ set iic_main [create_bd_intf_port -mode Master -vlnv xilinx.com:interface set uart_sin [create_bd_port -dir I uart_sin] set uart_sout [create_bd_port -dir O uart_sout] -set unc_int0 [create_bd_port -dir I unc_int0] -set unc_int1 [create_bd_port -dir I unc_int1] -set unc_int2 [create_bd_port -dir I unc_int2] -set unc_int3 [create_bd_port -dir I unc_int3] -set unc_int4 [create_bd_port -dir I unc_int4] - set hdmi_out_clk [create_bd_port -dir O hdmi_out_clk] set hdmi_hsync [create_bd_port -dir O hdmi_hsync] set hdmi_vsync [create_bd_port -dir O hdmi_vsync] @@ -40,6 +34,19 @@ set hdmi_data [create_bd_port -dir O -from 15 -to 0 hdmi_data] set spdif [create_bd_port -dir O spdif] +# interrupts + +set timer_irq [create_bd_port -dir O timer_irq] +set eth_irq [create_bd_port -dir O eth_irq] +set uart_irq [create_bd_port -dir O uart_irq] +set gpio_lcd_irq [create_bd_port -dir O gpio_lcd_irq] +set gpio_sw_irq [create_bd_port -dir O gpio_sw_irq] +set spdif_dma_irq [create_bd_port -dir O spdif_dma_irq] +set iic_irq [create_bd_port -dir O iic_irq] +set hdmi_dma_irq [create_bd_port -dir O hdmi_dma_irq] + +set mb_axi_intr [create_bd_port -dir I -from 31 -to 0 -type intr mb_axi_intr] + set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] $sys_rst # instance: microblaze - processor @@ -152,13 +159,6 @@ set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_sw_led set axi_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc] set_property -dict [list CONFIG.C_HAS_FAST {0}] $axi_intc -set sys_concat_aux_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_aux_intc] -set_property -dict [list CONFIG.NUM_PORTS {9}] $sys_concat_aux_intc -set_property -dict [list CONFIG.IN9_WIDTH {5}] $sys_concat_aux_intc - -set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc] -set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc - # hdmi peripherals set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen] @@ -212,8 +212,8 @@ connect_bd_intf_net -intf_net sys_mb_ilmb [get_bd_intf_pins sys_mb/ILMB] [get_bd connect_bd_intf_net -intf_net sys_mb_debug_intf [get_bd_intf_pins sys_mb_debug/MBDEBUG_0] [get_bd_intf_pins sys_mb/DEBUG] connect_bd_intf_net -intf_net sys_mb_interrupt [get_bd_intf_pins axi_intc/interrupt] [get_bd_intf_pins sys_mb/INTERRUPT] -connect_bd_net -net sys_concat_aux_intc_intr [get_bd_pins sys_concat_aux_intc/dout] [get_bd_pins axi_intc/intr] -connect_bd_net -net sys_concat_intc_intr [get_bd_pins sys_concat_intc/dout] [get_bd_pins sys_concat_aux_intc/In8] +connect_bd_net -net sys_concat_intr [get_bd_ports mb_axi_intr] [get_bd_pins axi_intc/intr] +set_property -dict [list CONFIG.PortWidth {32}] [get_bd_ports mb_axi_intr] # defaults (peripherals) @@ -319,19 +319,14 @@ connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S07_ACLK] $sy # defaults (interrupts) -connect_bd_net -net sys_concat_aux_intc_intr_00 [get_bd_pins sys_concat_aux_intc/In0] [get_bd_pins axi_timer/interrupt] -connect_bd_net -net sys_concat_aux_intc_intr_01 [get_bd_pins sys_concat_aux_intc/In1] [get_bd_pins axi_ethernet/ip2intc_irpt] -connect_bd_net -net sys_concat_aux_intc_intr_02 [get_bd_pins sys_concat_aux_intc/In2] [get_bd_ports unc_int0] -connect_bd_net -net sys_concat_aux_intc_intr_03 [get_bd_pins sys_concat_aux_intc/In3] [get_bd_ports unc_int1] -connect_bd_net -net sys_concat_aux_intc_intr_04 [get_bd_pins sys_concat_aux_intc/In4] [get_bd_pins axi_uart/interrupt] -connect_bd_net -net sys_concat_aux_intc_intr_05 [get_bd_pins sys_concat_aux_intc/In5] [get_bd_pins axi_gpio_lcd/ip2intc_irpt] -connect_bd_net -net sys_concat_aux_intc_intr_06 [get_bd_pins sys_concat_aux_intc/In6] [get_bd_pins axi_gpio_sw_led/ip2intc_irpt] -connect_bd_net -net sys_concat_aux_intc_intr_07 [get_bd_pins sys_concat_aux_intc/In7] [get_bd_pins axi_spdif_tx_dma/mm2s_introut] -connect_bd_net -net sys_concat_intc_din_0 [get_bd_pins sys_concat_intc/In0] [get_bd_pins axi_hdmi_dma/mm2s_introut] -connect_bd_net -net sys_concat_intc_din_1 [get_bd_pins sys_concat_intc/In1] [get_bd_pins axi_iic_main/iic2intc_irpt] -connect_bd_net -net sys_concat_intc_din_2 [get_bd_pins sys_concat_intc/In2] [get_bd_ports unc_int2] -connect_bd_net -net sys_concat_intc_din_3 [get_bd_pins sys_concat_intc/In3] [get_bd_ports unc_int3] -connect_bd_net -net sys_concat_intc_din_4 [get_bd_pins sys_concat_intc/In4] [get_bd_ports unc_int4] +connect_bd_net -net sys_base_intr_00 [get_bd_ports timer_irq] [get_bd_pins axi_timer/interrupt] +connect_bd_net -net sys_base_intr_01 [get_bd_ports eth_irq] [get_bd_pins axi_ethernet/ip2intc_irpt] +connect_bd_net -net sys_base_intr_04 [get_bd_ports uart_irq] [get_bd_pins axi_uart/interrupt] +connect_bd_net -net sys_base_intr_05 [get_bd_ports gpio_lcd_irq] [get_bd_pins axi_gpio_lcd/ip2intc_irpt] +connect_bd_net -net sys_base_intr_06 [get_bd_ports gpio_sw_irq] [get_bd_pins axi_gpio_sw_led/ip2intc_irpt] +connect_bd_net -net sys_base_intr_07 [get_bd_ports spdif_dma_irq] [get_bd_pins axi_spdif_tx_dma/mm2s_introut] +connect_bd_net -net sys_base_intr_08 [get_bd_ports iic_irq] [get_bd_pins axi_hdmi_dma/mm2s_introut] +connect_bd_net -net sys_base_intr_09 [get_bd_ports hdmi_dma_irq ] [get_bd_pins axi_iic_main/iic2intc_irpt] # defaults (external interface) diff --git a/projects/common/kcu105/kcu105_system_bd.tcl b/projects/common/kcu105/kcu105_system_bd.tcl index 3b543e0cb..1f6011cfd 100644 --- a/projects/common/kcu105/kcu105_system_bd.tcl +++ b/projects/common/kcu105/kcu105_system_bd.tcl @@ -17,16 +17,11 @@ set gpio_sw [create_bd_intf_port -mode Master -vlnv xilinx.com:interface set gpio_led [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_led] set gpio_lcd [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_lcd] -set iic_rstn [create_bd_port -dir O iic_rstn] set iic_main [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main] set uart_sin [create_bd_port -dir I uart_sin] set uart_sout [create_bd_port -dir O uart_sout] -set unc_int2 [create_bd_port -dir I unc_int2] -set unc_int3 [create_bd_port -dir I unc_int3] -set unc_int4 [create_bd_port -dir I unc_int4] - set hdmi_out_clk [create_bd_port -dir O hdmi_out_clk] set hdmi_hsync [create_bd_port -dir O hdmi_hsync] set hdmi_vsync [create_bd_port -dir O hdmi_vsync] @@ -182,12 +177,8 @@ set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_sw_led set axi_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc] set_property -dict [list CONFIG.C_HAS_FAST {0}] $axi_intc -set sys_concat_aux_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_aux_intc] -set_property -dict [list CONFIG.NUM_PORTS {9}] $sys_concat_aux_intc -set_property -dict [list CONFIG.IN8_WIDTH {5}] $sys_concat_aux_intc - set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc] -set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc +set_property -dict [list CONFIG.NUM_PORTS {32}] $sys_concat_intc # hdmi peripherals @@ -241,66 +232,65 @@ connect_bd_intf_net -intf_net sys_mb_ilmb [get_bd_intf_pins sys_mb/ILMB] [get_bd connect_bd_intf_net -intf_net sys_mb_debug_intf [get_bd_intf_pins sys_mb_debug/MBDEBUG_0] [get_bd_intf_pins sys_mb/DEBUG] connect_bd_intf_net -intf_net sys_mb_interrupt [get_bd_intf_pins axi_intc/interrupt] [get_bd_intf_pins sys_mb/INTERRUPT] -connect_bd_net -net sys_concat_aux_intc_intr [get_bd_pins sys_concat_aux_intc/dout] [get_bd_pins axi_intc/intr] -connect_bd_net -net sys_concat_intc_intr [get_bd_pins sys_concat_intc/dout] [get_bd_pins sys_concat_aux_intc/In8] +connect_bd_net -net sys_concat_intc_intr [get_bd_pins sys_concat_intc/dout] [get_bd_pins axi_intc/intr] # defaults (peripherals) set sys_reset_source [get_bd_pins sys_rstgen/peripheral_reset] -set sys_resetn_source [get_bd_pins sys_rstgen/peripheral_aresetn] +set sys_100m_resetn_source [get_bd_pins sys_rstgen/peripheral_aresetn] set sys_mem_resetn_source [get_bd_pins axi_ddr_cntrl_rstgen/peripheral_aresetn] set sys_mem_clk_source [get_bd_pins axi_ddr_cntrl/c0_ddr4_ui_clk] -set sys_cpu_clk_source [get_bd_pins axi_ddr_cntrl/addn_ui_clkout1] +set sys_100m_clk_source [get_bd_pins axi_ddr_cntrl/addn_ui_clkout1] set sys_200m_clk_source [get_bd_pins axi_ddr_cntrl/addn_ui_clkout2] connect_bd_net -net sys_cpu_rst $sys_reset_source -connect_bd_net -net sys_cpu_rstn $sys_resetn_source +connect_bd_net -net sys_100m_resetn $sys_100m_resetn_source connect_bd_net -net sys_mem_rstn $sys_mem_resetn_source -connect_bd_net -net sys_cpu_clk $sys_cpu_clk_source +connect_bd_net -net sys_100m_clk $sys_100m_clk_source connect_bd_net -net sys_mem_clk $sys_mem_clk_source connect_bd_net -net sys_200m_clk $sys_200m_clk_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M06_ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_aux_interconnect/ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M06_ACLK] $sys_cpu_clk_source -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/ACLK] $sys_cpu_clk_source -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/ACLK] $sys_cpu_clk_source -connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/ACLK] $sys_200m_clk_source -connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_aux_interconnect/ACLK] $sys_200m_clk_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M06_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_aux_interconnect/ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M06_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_aux_interconnect/ACLK] $sys_100m_clk_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins sys_mb_debug/S_AXI_ARESETN] +connect_bd_net -net sys_100m_resetn [get_bd_pins sys_mb_debug/S_AXI_ARESETN] connect_bd_net -net sys_mem_rstn [get_bd_pins axi_ddr_cntrl/c0_ddr4_aresetn] -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_ethernet/s_axi_lite_resetn] $sys_resetn_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_uart/s_axi_aresetn] -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_timer/s_axi_aresetn] -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_intc/s_axi_aresetn] -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_gpio_lcd/s_axi_aresetn] -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_gpio_sw_led/s_axi_aresetn] -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_iic_main/s_axi_aresetn] -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_ethernet_dma/axi_resetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ethernet/s_axi_lite_resetn] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_uart/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_timer/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_intc/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_gpio_lcd/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_gpio_sw_led/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_iic_main/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ethernet_dma/axi_resetn] -connect_bd_net -net sys_cpu_clk [get_bd_pins sys_rstgen/slowest_sync_clk] -connect_bd_net -net sys_cpu_clk [get_bd_pins sys_mb/Clk] -connect_bd_net -net sys_cpu_clk [get_bd_pins sys_mb_debug/S_AXI_ACLK] -connect_bd_net -net sys_cpu_clk [get_bd_pins sys_dlmb/LMB_Clk] -connect_bd_net -net sys_cpu_clk [get_bd_pins sys_ilmb/LMB_Clk] -connect_bd_net -net sys_cpu_clk [get_bd_pins sys_dlmb_cntlr/LMB_Clk] -connect_bd_net -net sys_cpu_clk [get_bd_pins sys_ilmb_cntlr/LMB_Clk] -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ethernet/s_axi_lite_clk] $sys_cpu_clk_source -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ethernet/axis_clk] $sys_cpu_clk_source -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ethernet_dma/m_axi_sg_aclk] -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ethernet_dma/m_axi_mm2s_aclk] -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ethernet_dma/m_axi_s2mm_aclk] -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ethernet_dma/s_axi_lite_aclk] -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_uart/s_axi_aclk] -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_timer/s_axi_aclk] -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_intc/s_axi_aclk] -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_gpio_lcd/s_axi_aclk] -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_gpio_sw_led/s_axi_aclk] -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_iic_main/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins sys_rstgen/slowest_sync_clk] +connect_bd_net -net sys_100m_clk [get_bd_pins sys_mb/Clk] +connect_bd_net -net sys_100m_clk [get_bd_pins sys_mb_debug/S_AXI_ACLK] +connect_bd_net -net sys_100m_clk [get_bd_pins sys_dlmb/LMB_Clk] +connect_bd_net -net sys_100m_clk [get_bd_pins sys_ilmb/LMB_Clk] +connect_bd_net -net sys_100m_clk [get_bd_pins sys_dlmb_cntlr/LMB_Clk] +connect_bd_net -net sys_100m_clk [get_bd_pins sys_ilmb_cntlr/LMB_Clk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet/s_axi_lite_clk] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet/axis_clk] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet_dma/m_axi_sg_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet_dma/m_axi_mm2s_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet_dma/m_axi_s2mm_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet_dma/s_axi_lite_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_uart/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_timer/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_intc/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_gpio_lcd/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_gpio_sw_led/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_iic_main/s_axi_aclk] # defaults (interconnect - processor) @@ -313,76 +303,78 @@ connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m04 [get_bd_intf_pins axi connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m05 [get_bd_intf_pins axi_cpu_aux_interconnect/M05_AXI] [get_bd_intf_pins axi_intc/s_axi] connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m06 [get_bd_intf_pins axi_cpu_aux_interconnect/M06_AXI] [get_bd_intf_pins axi_gpio_lcd/s_axi] connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m07 [get_bd_intf_pins axi_cpu_aux_interconnect/M07_AXI] [get_bd_intf_pins axi_gpio_sw_led/s_axi] -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/S00_ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/M00_ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/M01_ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/M02_ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/M03_ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/M04_ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/M05_ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/M06_ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/M07_ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/S00_ACLK] $sys_cpu_clk_source -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/M00_ACLK] $sys_cpu_clk_source -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/M01_ACLK] $sys_cpu_clk_source -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/M02_ACLK] $sys_cpu_clk_source -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/M03_ACLK] $sys_cpu_clk_source -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/M04_ACLK] $sys_cpu_clk_source -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/M05_ACLK] $sys_cpu_clk_source -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/M06_ACLK] $sys_cpu_clk_source -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/M07_ACLK] $sys_cpu_clk_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/S00_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/M00_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/M01_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/M02_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/M03_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/M04_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/M05_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/M06_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/M07_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/S00_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/M00_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/M01_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/M02_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/M03_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/M04_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/M05_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/M06_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/M07_ACLK] $sys_100m_clk_source connect_bd_intf_net -intf_net axi_cpu_interconnect_s00 [get_bd_intf_pins axi_cpu_interconnect/S00_AXI] [get_bd_intf_pins sys_mb/M_AXI_DP] connect_bd_intf_net -intf_net axi_cpu_interconnect_m00 [get_bd_intf_pins axi_cpu_interconnect/M00_AXI] [get_bd_intf_pins axi_iic_main/s_axi] -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/S00_ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M00_ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/S00_ACLK] $sys_cpu_clk_source -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M00_ACLK] $sys_cpu_clk_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/S00_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M00_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/S00_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M00_ACLK] $sys_100m_clk_source # defaults (interconnect - memory) -connect_bd_intf_net -intf_net axi_mem_aux_interconnect_m00 [get_bd_intf_pins axi_mem_aux_interconnect/M00_AXI] [get_bd_intf_pins axi_ddr_cntrl/C0_DDR4_S_AXI] +connect_bd_intf_net -intf_net axi_mem_aux_interconnect_m00 [get_bd_intf_pins axi_mem_aux_interconnect/M00_AXI] [get_bd_intf_pins axi_ddr_cntrl/C0_DDR4_S_AXI] connect_bd_intf_net -intf_net axi_mem_aux_interconnect_s00 [get_bd_intf_pins axi_mem_aux_interconnect/S00_AXI] [get_bd_intf_pins axi_mem_interconnect/M00_AXI] connect_bd_net -net sys_mem_rstn [get_bd_pins axi_mem_aux_interconnect/M00_ARESETN] $sys_mem_resetn_source connect_bd_net -net sys_mem_clk [get_bd_pins axi_mem_aux_interconnect/M00_ACLK] $sys_mem_clk_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_aux_interconnect/S00_ARESETN] $sys_resetn_source -connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_aux_interconnect/S00_ACLK] $sys_200m_clk_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_aux_interconnect/S01_ARESETN] $sys_resetn_source -connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_aux_interconnect/S01_ACLK] $sys_200m_clk_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/M00_ARESETN] $sys_resetn_source -connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/M00_ACLK] $sys_200m_clk_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_aux_interconnect/S00_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_aux_interconnect/S00_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_aux_interconnect/S01_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_aux_interconnect/S01_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/M00_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/M00_ACLK] $sys_100m_clk_source connect_bd_intf_net -intf_net axi_mem_interconnect_s00 [get_bd_intf_pins axi_mem_interconnect/S00_AXI] [get_bd_intf_pins sys_mb/M_AXI_DC] connect_bd_intf_net -intf_net axi_mem_interconnect_s01 [get_bd_intf_pins axi_mem_interconnect/S01_AXI] [get_bd_intf_pins sys_mb/M_AXI_IC] connect_bd_intf_net -intf_net axi_mem_interconnect_s05 [get_bd_intf_pins axi_mem_interconnect/S05_AXI] [get_bd_intf_pins axi_ethernet_dma/M_AXI_SG] connect_bd_intf_net -intf_net axi_mem_interconnect_s06 [get_bd_intf_pins axi_mem_interconnect/S06_AXI] [get_bd_intf_pins axi_ethernet_dma/M_AXI_MM2S] connect_bd_intf_net -intf_net axi_mem_interconnect_s07 [get_bd_intf_pins axi_mem_interconnect/S07_AXI] [get_bd_intf_pins axi_ethernet_dma/M_AXI_S2MM] -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S00_ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S01_ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S05_ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S06_ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S07_ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S00_ACLK] $sys_cpu_clk_source -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S01_ACLK] $sys_cpu_clk_source -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S05_ACLK] $sys_cpu_clk_source -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S06_ACLK] $sys_cpu_clk_source -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S07_ACLK] $sys_cpu_clk_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S00_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S01_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S05_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S06_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S07_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S00_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S01_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S05_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S06_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S07_ACLK] $sys_100m_clk_source # defaults (interrupts) -connect_bd_net -net sys_concat_aux_intc_intr_00 [get_bd_pins sys_concat_aux_intc/In0] [get_bd_pins axi_timer/interrupt] -connect_bd_net -net sys_concat_aux_intc_intr_01 [get_bd_pins sys_concat_aux_intc/In1] [get_bd_pins axi_ethernet/interrupt] -connect_bd_net -net sys_concat_aux_intc_intr_02 [get_bd_pins sys_concat_aux_intc/In2] [get_bd_pins axi_ethernet_dma/mm2s_introut] -connect_bd_net -net sys_concat_aux_intc_intr_03 [get_bd_pins sys_concat_aux_intc/In3] [get_bd_pins axi_ethernet_dma/s2mm_introut] -connect_bd_net -net sys_concat_aux_intc_intr_04 [get_bd_pins sys_concat_aux_intc/In4] [get_bd_pins axi_uart/interrupt] -connect_bd_net -net sys_concat_aux_intc_intr_05 [get_bd_pins sys_concat_aux_intc/In5] [get_bd_pins axi_gpio_lcd/ip2intc_irpt] -connect_bd_net -net sys_concat_aux_intc_intr_06 [get_bd_pins sys_concat_aux_intc/In6] [get_bd_pins axi_gpio_sw_led/ip2intc_irpt] -connect_bd_net -net sys_concat_aux_intc_intr_07 [get_bd_pins sys_concat_aux_intc/In7] [get_bd_pins axi_spdif_tx_dma/mm2s_introut] -connect_bd_net -net sys_concat_intc_din_0 [get_bd_pins sys_concat_intc/In0] [get_bd_pins axi_hdmi_dma/mm2s_introut] -connect_bd_net -net sys_concat_intc_din_1 [get_bd_pins sys_concat_intc/In1] [get_bd_pins axi_iic_main/iic2intc_irpt] -connect_bd_net -net sys_concat_intc_din_2 [get_bd_pins sys_concat_intc/In2] [get_bd_ports unc_int2] -connect_bd_net -net sys_concat_intc_din_3 [get_bd_pins sys_concat_intc/In3] [get_bd_ports unc_int3] -connect_bd_net -net sys_concat_intc_din_4 [get_bd_pins sys_concat_intc/In4] [get_bd_ports unc_int4] +connect_bd_net [get_bd_pins sys_concat_intc/In0] [get_bd_pins axi_timer/interrupt] +connect_bd_net [get_bd_pins sys_concat_intc/In1] [get_bd_pins axi_ethernet/interrupt] +connect_bd_net [get_bd_pins sys_concat_intc/In2] [get_bd_pins axi_ethernet_dma/mm2s_introut] +connect_bd_net [get_bd_pins sys_concat_intc/In3] [get_bd_pins axi_ethernet_dma/s2mm_introut] +connect_bd_net [get_bd_pins sys_concat_intc/In4] [get_bd_pins axi_uart/interrupt] +connect_bd_net [get_bd_pins sys_concat_intc/In5] [get_bd_pins axi_gpio_lcd/ip2intc_irpt] +connect_bd_net [get_bd_pins sys_concat_intc/In6] [get_bd_pins axi_gpio_sw_led/ip2intc_irpt] +connect_bd_net [get_bd_pins sys_concat_intc/In7] [get_bd_pins axi_spdif_tx_dma/mm2s_introut] +connect_bd_net [get_bd_pins sys_concat_intc/In8] [get_bd_pins axi_hdmi_dma/mm2s_introut] +connect_bd_net [get_bd_pins sys_concat_intc/In9] [get_bd_pins axi_iic_main/iic2intc_irpt] + +for {set intc_index 10} {$intc_index < 32} {incr intc_index} { + set mb_intr_${intc_index} [create_bd_port -dir I mb_intr_${intc_index}] + connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports mb_intr_${intc_index}] +} # defaults (ddr) @@ -393,8 +385,8 @@ connect_bd_net -net sys_rst [get_bd_ports sys_rst] [get_bd_pins connect_bd_net -net axi_ddr_cntrl_rst [get_bd_pins axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst] connect_bd_net -net axi_ddr_cntrl_rst [get_bd_pins sys_rstgen/ext_reset_in] -connect_bd_net -net axi_ddr_cntrl_rst [get_bd_pins axi_ethernet_rstgen/ext_reset_in] -connect_bd_net -net axi_ddr_cntrl_rst [get_bd_pins axi_ddr_cntrl_rstgen/ext_reset_in] +connect_bd_net -net axi_ddr_cntrl_rst [get_bd_pins axi_ethernet_rstgen/ext_reset_in] +connect_bd_net -net axi_ddr_cntrl_rst [get_bd_pins axi_ddr_cntrl_rstgen/ext_reset_in] connect_bd_net -net sys_mem_clk [get_bd_pins axi_ddr_cntrl_rstgen/slowest_sync_clk] # defaults (ethernet) @@ -408,11 +400,11 @@ connect_bd_intf_net -intf_net axi_ethernet_dma_rxd [get_bd_intf_pins axi_et connect_bd_intf_net -intf_net axi_ethernet_dma_rxs [get_bd_intf_pins axi_ethernet/m_axis_rxs] [get_bd_intf_pins axi_ethernet_dma/S_AXIS_STS] connect_bd_net -net phy_sd [get_bd_ports phy_sd] [get_bd_pins axi_ethernet/signal_detect] -connect_bd_net -net sys_cpu_rstn [get_bd_ports phy_rst_n] $sys_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_ports phy_rst_n] $sys_100m_resetn_source connect_bd_net -net axi_ethernet_clkgen_125m_clk [get_bd_pins axi_ethernet_clkgen/clk_out1] [get_bd_pins axi_ethernet/clk125m] -connect_bd_net -net axi_ethernet_clkgen_312m_clk [get_bd_pins axi_ethernet_clkgen/clk_out2] [get_bd_pins axi_ethernet/clk312] -connect_bd_net -net axi_ethernet_clkgen_625m_clk [get_bd_pins axi_ethernet_clkgen/clk_out3] [get_bd_pins axi_ethernet/clk625] -connect_bd_net -net axi_ethernet_clkgen_locked [get_bd_pins axi_ethernet_clkgen/locked] [get_bd_pins axi_ethernet/mmcm_locked] +connect_bd_net -net axi_ethernet_clkgen_312m_clk [get_bd_pins axi_ethernet_clkgen/clk_out2] [get_bd_pins axi_ethernet/clk312] +connect_bd_net -net axi_ethernet_clkgen_625m_clk [get_bd_pins axi_ethernet_clkgen/clk_out3] [get_bd_pins axi_ethernet/clk625] +connect_bd_net -net axi_ethernet_clkgen_locked [get_bd_pins axi_ethernet_clkgen/locked] [get_bd_pins axi_ethernet/mmcm_locked] connect_bd_net -net axi_ethernet_rstgen_rst [get_bd_pins axi_ethernet_rstgen/peripheral_reset] [get_bd_pins axi_ethernet/rst_125] connect_bd_net -net axi_ethernet_dma_txd_rstn [get_bd_pins axi_ethernet/axi_txd_arstn] [get_bd_pins axi_ethernet_dma/mm2s_prmry_reset_out_n] connect_bd_net -net axi_ethernet_dma_txc_rstn [get_bd_pins axi_ethernet/axi_txc_arstn] [get_bd_pins axi_ethernet_dma/mm2s_cntrl_reset_out_n] @@ -428,7 +420,6 @@ connect_bd_intf_net -intf_net gpio_led [get_bd_intf_ports gpio_led] [get_bd_in connect_bd_intf_net -intf_net iic_main [get_bd_intf_ports iic_main] [get_bd_intf_pins axi_iic_main/iic] connect_bd_net -net uart_sin [get_bd_ports uart_sin] [get_bd_pins axi_uart/rx] connect_bd_net -net uart_sout [get_bd_ports uart_sout] [get_bd_pins axi_uart/tx] -connect_bd_net -net iic_rstn [get_bd_ports iic_rstn] [get_bd_pins axi_iic_main/gpo] # hdmi @@ -440,25 +431,25 @@ connect_bd_intf_net -intf_net axi_cpu_interconnect_m03 [get_bd_intf_pins axi_cpu connect_bd_intf_net -intf_net axi_mem_interconnect_s02 [get_bd_intf_pins axi_mem_interconnect/S02_AXI] [get_bd_intf_pins axi_hdmi_dma/M_AXI_MM2S] -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M01_ACLK] $sys_cpu_clk_source -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M02_ACLK] $sys_cpu_clk_source -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M03_ACLK] $sys_cpu_clk_source -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S02_ACLK] $sys_cpu_clk_source -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_hdmi_clkgen/s_axi_aclk] -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_hdmi_clkgen/drp_clk] -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_hdmi_core/s_axi_aclk] -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_hdmi_core/m_axis_mm2s_clk] -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_hdmi_dma/s_axi_lite_aclk] -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_hdmi_dma/m_axi_mm2s_aclk] -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_hdmi_dma/m_axis_mm2s_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M01_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M02_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M03_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S02_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_clkgen/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_clkgen/drp_clk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/m_axis_mm2s_clk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/s_axi_lite_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/m_axi_mm2s_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/m_axis_mm2s_aclk] -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M01_ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M02_ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M03_ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S02_ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_hdmi_clkgen/s_axi_aresetn] -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_hdmi_core/s_axi_aresetn] -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_hdmi_dma/axi_resetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M01_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M02_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M03_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S02_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_clkgen/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_core/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_dma/axi_resetn] connect_bd_net -net axi_hdmi_tx_core_hdmi_clk [get_bd_pins axi_hdmi_core/hdmi_clk] [get_bd_pins axi_hdmi_clkgen/clk_0] connect_bd_net -net axi_hdmi_tx_core_hdmi_out_clk [get_bd_pins axi_hdmi_core/hdmi_out_clk] [get_bd_ports hdmi_out_clk] @@ -478,25 +469,25 @@ connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync [get_bd_pins axi_hdmi_core/m_ connect_bd_intf_net -intf_net axi_cpu_interconnect_m04 [get_bd_intf_pins axi_cpu_interconnect/M04_AXI] [get_bd_intf_pins axi_spdif_tx_core/s_axi] connect_bd_intf_net -intf_net axi_cpu_interconnect_m05 [get_bd_intf_pins axi_cpu_interconnect/M05_AXI] [get_bd_intf_pins axi_spdif_tx_dma/S_AXI_LITE] -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M04_ACLK] $sys_cpu_clk_source -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M05_ACLK] $sys_cpu_clk_source -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_spdif_tx_core/S_AXI_ACLK] -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_spdif_tx_core/S_AXIS_ACLK] -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_spdif_tx_dma/s_axi_lite_aclk] -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_spdif_tx_dma/m_axi_mm2s_aclk] -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_spdif_tx_dma/m_axi_sg_aclk] -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M04_ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M05_ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_spdif_tx_core/S_AXI_ARESETN] -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_spdif_tx_core/S_AXIS_ARESETN] -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_spdif_tx_dma/axi_resetn] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M04_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M05_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/S_AXI_ACLK] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/S_AXIS_ACLK] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_dma/s_axi_lite_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_dma/m_axi_mm2s_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_dma/m_axi_sg_aclk] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M04_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M05_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_core/S_AXI_ARESETN] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_core/S_AXIS_ARESETN] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_dma/axi_resetn] connect_bd_intf_net -intf_net axi_mem_interconnect_s03 [get_bd_intf_pins axi_mem_interconnect/S03_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_SG] connect_bd_intf_net -intf_net axi_mem_interconnect_s04 [get_bd_intf_pins axi_mem_interconnect/S04_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_MM2S] -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S03_ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S04_ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S03_ACLK] $sys_cpu_clk_source -connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S04_ACLK] $sys_cpu_clk_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S03_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S04_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S03_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S04_ACLK] $sys_100m_clk_source connect_bd_net -net axi_spdif_tx_dma_mm2s_valid [get_bd_pins axi_spdif_tx_core/S_AXIS_TVALID] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tvalid] connect_bd_net -net axi_spdif_tx_dma_mm2s_data [get_bd_pins axi_spdif_tx_core/S_AXIS_TDATA] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tdata] @@ -512,6 +503,7 @@ connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/ set sys_zynq 0 set sys_mem_size 0x40000000 set sys_addr_cntrl_space [get_bd_addr_spaces sys_mb/Data] +set sys_addr_mem_seg [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] create_bd_addr_seg -range 0x00020000 -offset 0x00000000 $sys_addr_cntrl_space [get_bd_addr_segs sys_dlmb_cntlr/SLMB/Mem] SEG_data_dlmb_cntlr create_bd_addr_seg -range 0x00001000 -offset 0x41400000 $sys_addr_cntrl_space [get_bd_addr_segs sys_mb_debug/S_AXI/Reg] SEG_data_mb_debug @@ -533,13 +525,13 @@ create_bd_addr_seg -range 0x00010000 -offset 0x41E00000 $sys_addr_cntrl_space [g create_bd_addr_seg -range 0x00020000 -offset 0x00000000 [get_bd_addr_spaces sys_mb/Instruction] [get_bd_addr_segs sys_ilmb_cntlr/SLMB/Mem] SEG_instr_ilmb_cntlr create_bd_addr_seg -range 0x00010000 -offset 0x00000000 [get_bd_addr_spaces axi_ethernet/eth_buf/S_AXI_2TEMAC] [get_bd_addr_segs axi_ethernet/eth_mac/s_axi/Reg] SEG_ethernet_mac -create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl -create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces sys_mb/Instruction] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl -create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_dma/Data_SG] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl -create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl -create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_dma/Data_S2MM] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl -create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl -create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_SG] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl -create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl +create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces sys_mb/Data] $sys_addr_mem_seg SEG_mem_ddr_cntrl +create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces sys_mb/Instruction] $sys_addr_mem_seg SEG_mem_ddr_cntrl +create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_dma/Data_SG] $sys_addr_mem_seg SEG_mem_ddr_cntrl +create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_dma/Data_MM2S] $sys_addr_mem_seg SEG_mem_ddr_cntrl +create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_dma/Data_S2MM] $sys_addr_mem_seg SEG_mem_ddr_cntrl +create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S] $sys_addr_mem_seg SEG_mem_ddr_cntrl +create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_SG] $sys_addr_mem_seg SEG_mem_ddr_cntrl +create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_MM2S] $sys_addr_mem_seg SEG_mem_ddr_cntrl diff --git a/projects/common/kcu105/kcu105_system_constr.xdc b/projects/common/kcu105/kcu105_system_constr.xdc index 29c656121..e5a193fe6 100644 --- a/projects/common/kcu105/kcu105_system_constr.xdc +++ b/projects/common/kcu105/kcu105_system_constr.xdc @@ -56,7 +56,6 @@ set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS18} [get_ports gpio_le # iic -set_property -dict {PACKAGE_PIN AP10 IOSTANDARD LVCMOS18} [get_ports iic_rstn] set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS18} [get_ports iic_scl] set_property -dict {PACKAGE_PIN J25 IOSTANDARD LVCMOS18} [get_ports iic_sda] diff --git a/projects/common/vc707/vc707_system_bd.tcl b/projects/common/vc707/vc707_system_bd.tcl index 90b8ff068..eac56bcfd 100644 --- a/projects/common/vc707/vc707_system_bd.tcl +++ b/projects/common/vc707/vc707_system_bd.tcl @@ -2,11 +2,11 @@ set sys_rst [create_bd_port -dir I -type rst sys_rst] set sys_clk_p [create_bd_port -dir I sys_clk_p] set sys_clk_n [create_bd_port -dir I sys_clk_n] -set fan_pwm [create_bd_port -dir O fan_pwm] set ddr3 [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3] set phy_rstn [create_bd_port -dir O -type rst phy_rstn] +set phy_sd [create_bd_port -dir I phy_sd] set mgt_clk [create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 mgt_clk] set sgmii [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:sgmii_rtl:1.0 sgmii] set mdio [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_io:1.0 mdio] @@ -21,12 +21,6 @@ set iic_main [create_bd_intf_port -mode Master -vlnv xilinx.com:interface set uart_sin [create_bd_port -dir I uart_sin] set uart_sout [create_bd_port -dir O uart_sout] -set unc_int0 [create_bd_port -dir I unc_int0] -set unc_int1 [create_bd_port -dir I unc_int1] -set unc_int2 [create_bd_port -dir I unc_int2] -set unc_int3 [create_bd_port -dir I unc_int3] -set unc_int4 [create_bd_port -dir I unc_int4] - set hdmi_out_clk [create_bd_port -dir O hdmi_out_clk] set hdmi_hsync [create_bd_port -dir O hdmi_hsync] set hdmi_vsync [create_bd_port -dir O hdmi_vsync] @@ -61,7 +55,6 @@ set_property -dict [list CONFIG.C_DCACHE_HIGHADDR {0xBFFFFFFF}] $sys_mb set_property -dict [list CONFIG.C_DCACHE_BASEADDR {0x80000000}] $sys_mb set_property -dict [list CONFIG.G_TEMPLATE_LIST {4}] $sys_mb - # instance: microblaze - local memory & bus set sys_dlmb [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 sys_dlmb] @@ -85,8 +78,6 @@ set_property -dict [list CONFIG.C_USE_UART {1}] $sys_mb_debug set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen] -set sys_const_vcc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 sys_const_vcc] - # instance: ddr (mig) set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.1 axi_ddr_cntrl] @@ -96,6 +87,7 @@ set_property -dict [list CONFIG.XML_INPUT_FILE {vc707_system_mig.prj}] $axi_ddr_ set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {Custom}] $axi_ddr_cntrl # instance: axi interconnect (lite) + set axi_cpu_aux_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_aux_interconnect] set_property -dict [list CONFIG.NUM_MI {8}] $axi_cpu_aux_interconnect set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_aux_interconnect @@ -150,12 +142,8 @@ set_property -dict [list CONFIG.C_ALL_OUTPUTS_2 {1}] $axi_gpio_sw_led set axi_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc] set_property -dict [list CONFIG.C_HAS_FAST {0}] $axi_intc -set sys_concat_aux_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_aux_intc] -set_property -dict [list CONFIG.NUM_PORTS {9}] $sys_concat_aux_intc -set_property -dict [list CONFIG.IN9_WIDTH {5}] $sys_concat_aux_intc - set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc] -set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc +set_property -dict [list CONFIG.NUM_PORTS {32}] $sys_concat_intc # hdmi peripherals @@ -209,9 +197,8 @@ connect_bd_intf_net -intf_net sys_mb_ilmb [get_bd_intf_pins sys_mb/ILMB] [get_bd # microblaze debug & interrupt connect_bd_intf_net -intf_net sys_mb_debug [get_bd_intf_pins sys_mb_debug/MBDEBUG_0] [get_bd_intf_pins sys_mb/DEBUG] -connect_bd_net -net sys_concat_aux_intc_intr [get_bd_pins sys_concat_aux_intc/dout] [get_bd_pins axi_intc/intr] connect_bd_intf_net -intf_net sys_mb_interrupt [get_bd_intf_pins axi_intc/interrupt] [get_bd_intf_pins sys_mb/INTERRUPT] -connect_bd_net -net sys_concat_intc_intr [get_bd_pins sys_concat_intc/dout] [get_bd_pins sys_concat_aux_intc/In8] +connect_bd_net -net sys_concat_intc_intr [get_bd_pins sys_concat_intc/dout] [get_bd_pins axi_intc/intr] # defaults (peripherals) @@ -342,23 +329,25 @@ connect_bd_intf_net -intf_net axi_ethernet_dma_rxs [get_bd_intf_pins axi_etherne # defaults (interrupts) -connect_bd_net -net sys_concat_aux_intc_intr_00 [get_bd_pins sys_concat_aux_intc/In0] [get_bd_pins axi_timer/interrupt] -connect_bd_net -net sys_concat_aux_intc_intr_01 [get_bd_pins sys_concat_aux_intc/In1] [get_bd_pins axi_ethernet/interrupt] -connect_bd_net -net sys_concat_aux_intc_intr_02 [get_bd_pins sys_concat_aux_intc/In2] [get_bd_pins axi_ethernet_dma/mm2s_introut] -connect_bd_net -net sys_concat_aux_intc_intr_03 [get_bd_pins sys_concat_aux_intc/In3] [get_bd_pins axi_ethernet_dma/s2mm_introut] -connect_bd_net -net sys_concat_aux_intc_intr_04 [get_bd_pins sys_concat_aux_intc/In4] [get_bd_pins axi_uart/interrupt] -connect_bd_net -net sys_concat_aux_intc_intr_05 [get_bd_pins sys_concat_aux_intc/In5] [get_bd_pins axi_gpio_lcd/ip2intc_irpt] -connect_bd_net -net sys_concat_aux_intc_intr_06 [get_bd_pins sys_concat_aux_intc/In6] [get_bd_pins axi_gpio_sw_led/ip2intc_irpt] -connect_bd_net -net sys_concat_aux_intc_intr_07 [get_bd_pins sys_concat_aux_intc/In7] [get_bd_pins axi_spdif_tx_dma/mm2s_introut] -connect_bd_net -net sys_concat_intc_din_0 [get_bd_pins sys_concat_intc/In0] [get_bd_pins axi_hdmi_dma/mm2s_introut] -connect_bd_net -net sys_concat_intc_din_1 [get_bd_pins sys_concat_intc/In1] [get_bd_pins axi_iic_main/iic2intc_irpt] -connect_bd_net -net sys_concat_intc_din_2 [get_bd_pins sys_concat_intc/In2] [get_bd_ports unc_int2] -connect_bd_net -net sys_concat_intc_din_3 [get_bd_pins sys_concat_intc/In3] [get_bd_ports unc_int3] -connect_bd_net -net sys_concat_intc_din_4 [get_bd_pins sys_concat_intc/In4] [get_bd_ports unc_int4] +connect_bd_net [get_bd_pins sys_concat_intc/In0] [get_bd_pins axi_timer/interrupt] +connect_bd_net [get_bd_pins sys_concat_intc/In1] [get_bd_pins axi_ethernet/interrupt] +connect_bd_net [get_bd_pins sys_concat_intc/In2] [get_bd_pins axi_ethernet_dma/mm2s_introut] +connect_bd_net [get_bd_pins sys_concat_intc/In3] [get_bd_pins axi_ethernet_dma/s2mm_introut] +connect_bd_net [get_bd_pins sys_concat_intc/In4] [get_bd_pins axi_uart/interrupt] +connect_bd_net [get_bd_pins sys_concat_intc/In5] [get_bd_pins axi_gpio_lcd/ip2intc_irpt] +connect_bd_net [get_bd_pins sys_concat_intc/In6] [get_bd_pins axi_gpio_sw_led/ip2intc_irpt] +connect_bd_net [get_bd_pins sys_concat_intc/In7] [get_bd_pins axi_spdif_tx_dma/mm2s_introut] +connect_bd_net [get_bd_pins sys_concat_intc/In8] [get_bd_pins axi_hdmi_dma/mm2s_introut] +connect_bd_net [get_bd_pins sys_concat_intc/In9] [get_bd_pins axi_iic_main/iic2intc_irpt] + +for {set intc_index 10} {$intc_index < 32} {incr intc_index} { + set mb_intr_${intc_index} [create_bd_port -dir I mb_intr_${intc_index}] + connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports mb_intr_${intc_index}] +} # defaults (external interface) -connect_bd_net -net sys_const_vcc_vcc [get_bd_pins sys_const_vcc/dout] [get_bd_ports fan_pwm] [get_bd_pins axi_ethernet/signal_detect] +connect_bd_net -net phy_sd [get_bd_ports phy_sd] [get_bd_pins axi_ethernet/signal_detect] connect_bd_net -net sys_rst_s [get_bd_ports sys_rst] connect_bd_net -net sys_rst_s [get_bd_pins sys_rstgen/ext_reset_in] connect_bd_net -net sys_rst_s [get_bd_pins axi_ddr_cntrl/sys_rst] diff --git a/projects/common/xilinx/sys_dmafifo.tcl b/projects/common/xilinx/sys_dmafifo.tcl index 23bec9aa0..89c3ac8c9 100644 --- a/projects/common/xilinx/sys_dmafifo.tcl +++ b/projects/common/xilinx/sys_dmafifo.tcl @@ -44,6 +44,7 @@ proc p_sys_dmafifo {p_name m_name m_width} { set wfifo_mem [create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:12.0 wfifo_mem] set_property -dict [list CONFIG.INTERFACE_TYPE {Native}] $wfifo_mem set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM}] $wfifo_mem + set_property -dict [list CONFIG.asymmetric_port_width {true}] $wfifo_mem set_property -dict [list CONFIG.Input_Data_Width $m_width] $wfifo_mem set_property -dict [list CONFIG.Input_Depth {64}] $wfifo_mem set_property -dict [list CONFIG.Output_Data_Width {512}] $wfifo_mem @@ -52,6 +53,7 @@ proc p_sys_dmafifo {p_name m_name m_width} { set rfifo_mem [create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:12.0 rfifo_mem] set_property -dict [list CONFIG.INTERFACE_TYPE {Native}] $rfifo_mem set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM}] $rfifo_mem + set_property -dict [list CONFIG.asymmetric_port_width {true}] $rfifo_mem set_property -dict [list CONFIG.Input_Data_Width {512}] $rfifo_mem set_property -dict [list CONFIG.Input_Depth {64}] $rfifo_mem set_property -dict [list CONFIG.Output_Data_Width {64}] $rfifo_mem @@ -62,7 +64,7 @@ proc p_sys_dmafifo {p_name m_name m_width} { set axi_fifo2s [create_bd_cell -type ip -vlnv analog.com:user:axi_fifo2s:1.0 axi_fifo2s] set_property -dict [list CONFIG.AXI_ADDRESS {0xc0000000}] $axi_fifo2s - set_property -dict [list CONFIG.AXI_ADDRLIMIT {0xc01fff00}] $axi_fifo2s + set_property -dict [list CONFIG.AXI_ADDRLIMIT {0xc00fff00}] $axi_fifo2s set_property -dict [list CONFIG.AXI_LENGTH {4}] $axi_fifo2s set_property -dict [list CONFIG.AXI_SIZE {6}] $axi_fifo2s set_property -dict [list CONFIG.DATA_WIDTH {512}] $axi_fifo2s diff --git a/projects/common/zc702/zc702_system_bd.tcl b/projects/common/zc702/zc702_system_bd.tcl index 52fab9fee..de49eb695 100644 --- a/projects/common/zc702/zc702_system_bd.tcl +++ b/projects/common/zc702/zc702_system_bd.tcl @@ -22,6 +22,12 @@ set hdmi_data [create_bd_port -dir O -from 15 -to 0 hdmi_data] set spdif [create_bd_port -dir O spdif] +# interrupts + +set iic_irq [create_bd_port -dir O iic_irq] +set hdmi_dma_irq [create_bd_port -dir O hdmi_dma_irq] +set ps7_irq_f2p [create_bd_port -dir I -from 15 -to 0 -type intr ps7_irq_f2p] + # instance: sys_ps7 set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.4 sys_ps7] @@ -41,9 +47,6 @@ set_property -dict [list CONFIG.PCW_USE_DMA0 {1}] $sys_ps7 set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main] set_property -dict [list CONFIG.USE_BOARD_FLOW {true} CONFIG.IIC_BOARD_INTERFACE {IIC_MAIN}] $axi_iic_main -set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc] -set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc - set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect] set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_interconnect @@ -113,9 +116,7 @@ connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M00_ACLK] $sy connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M00_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_clk [get_bd_pins axi_iic_main/s_axi_aclk] connect_bd_net -net sys_100m_resetn [get_bd_pins axi_iic_main/s_axi_aresetn] -connect_bd_net -net sys_concat_intc_din_1 [get_bd_pins sys_concat_intc/In1] [get_bd_pins axi_iic_main/iic2intc_irpt] - -connect_bd_net -net sys_ps7_interrupt [get_bd_pins sys_concat_intc/dout] [get_bd_pins sys_ps7/IRQ_F2P] +connect_bd_net -net sys_concat_intc_din_1 [get_bd_ports iic_irq] [get_bd_pins axi_iic_main/iic2intc_irpt] # hdmi @@ -167,7 +168,9 @@ connect_bd_net -net axi_hdmi_tx_core_mm2s_tready [get_bd_pins axi_hdmi_core/m_ connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync] [get_bd_pins axi_hdmi_dma/mm2s_fsync] connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync_ret] -connect_bd_net -net sys_concat_intc_din_0 [get_bd_pins sys_concat_intc/In0] [get_bd_pins axi_hdmi_dma/mm2s_introut] +connect_bd_net -net sys_concat_intc_din_0 [get_bd_ports hdmi_dma_irq] [get_bd_pins axi_hdmi_dma/mm2s_introut] +connect_bd_net -net sys_ps7_interrupt [get_bd_ports ps7_irq_f2p] [get_bd_pins sys_ps7/IRQ_F2P] +set_property -dict [list CONFIG.PortWidth {16}] [get_bd_ports ps7_irq_f2p] # spdif audio diff --git a/projects/common/zc706/zc706_system_bd.tcl b/projects/common/zc706/zc706_system_bd.tcl index c2c17a12e..4c2d7918b 100644 --- a/projects/common/zc706/zc706_system_bd.tcl +++ b/projects/common/zc706/zc706_system_bd.tcl @@ -22,6 +22,12 @@ set hdmi_data [create_bd_port -dir O -from 23 -to 0 hdmi_data] set spdif [create_bd_port -dir O spdif] +# interrupts + +set iic_irq [create_bd_port -dir O iic_irq] +set hdmi_dma_irq [create_bd_port -dir O hdmi_dma_irq] +set ps7_irq_f2p [create_bd_port -dir I -from 15 -to 0 -type intr ps7_irq_f2p] + # instance: sys_ps7 set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.4 sys_ps7] @@ -42,9 +48,6 @@ set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7 set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main] set_property -dict [list CONFIG.USE_BOARD_FLOW {true} CONFIG.IIC_BOARD_INTERFACE {IIC_MAIN}] $axi_iic_main -set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc] -set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc - set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect] set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_interconnect @@ -115,9 +118,8 @@ connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M00_ACLK] $sy connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M00_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_clk [get_bd_pins axi_iic_main/s_axi_aclk] connect_bd_net -net sys_100m_resetn [get_bd_pins axi_iic_main/s_axi_aresetn] -connect_bd_net -net sys_concat_intc_din_1 [get_bd_pins sys_concat_intc/In14] [get_bd_pins axi_iic_main/iic2intc_irpt] +connect_bd_net -net iic_irq_net [get_bd_pins axi_iic_main/iic2intc_irpt] [get_bd_ports iic_irq] -connect_bd_net -net sys_ps7_interrupt [get_bd_pins sys_concat_intc/dout] [get_bd_pins sys_ps7/IRQ_F2P] # hdmi @@ -169,7 +171,10 @@ connect_bd_net -net axi_hdmi_tx_core_mm2s_tready [get_bd_pins axi_hdmi_core/m_ connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync] [get_bd_pins axi_hdmi_dma/mm2s_fsync] connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync_ret] -connect_bd_net -net sys_concat_intc_din_0 [get_bd_pins sys_concat_intc/In15] [get_bd_pins axi_hdmi_dma/mm2s_introut] +connect_bd_net -net hdmi_dma_irq_net [get_bd_pins axi_hdmi_dma/mm2s_introut] [get_bd_ports hdmi_dma_irq] + +connect_bd_net -net sys_ps7_interrupt [get_bd_pins sys_ps7/IRQ_F2P] [get_bd_ports ps7_irq_f2p] +set_property -dict [list CONFIG.PortWidth {16}] [get_bd_ports ps7_irq_f2p] # spdif audio diff --git a/projects/common/zed/zed_system_bd.tcl b/projects/common/zed/zed_system_bd.tcl index 2a01bb914..5733b6483 100644 --- a/projects/common/zed/zed_system_bd.tcl +++ b/projects/common/zed/zed_system_bd.tcl @@ -58,6 +58,7 @@ set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {32}] $sys_ps7 set_property -dict [list CONFIG.PCW_USE_DMA0 {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_USE_DMA1 {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_USE_DMA2 {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7 set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main] set_property -dict [list CONFIG.USE_BOARD_FLOW {true} CONFIG.IIC_BOARD_INTERFACE {IIC_MAIN}] $axi_iic_main @@ -65,7 +66,7 @@ set_property -dict [list CONFIG.USE_BOARD_FLOW {true} CONFIG.IIC_BOARD_INTERFACE set sys_i2c_mixer [create_bd_cell -type ip -vlnv analog.com:user:util_i2c_mixer:1.0 sys_i2c_mixer] set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc] -set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc +set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect] set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect @@ -148,7 +149,7 @@ connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M00_ACLK] $sy connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M00_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_clk [get_bd_pins axi_iic_main/s_axi_aclk] connect_bd_net -net sys_100m_resetn [get_bd_pins axi_iic_main/s_axi_aresetn] -connect_bd_net -net sys_concat_intc_din_1 [get_bd_pins sys_concat_intc/In1] [get_bd_pins axi_iic_main/iic2intc_irpt] +connect_bd_net -net sys_concat_intc_din_1 [get_bd_pins sys_concat_intc/In14] [get_bd_pins axi_iic_main/iic2intc_irpt] connect_bd_net -net axi_iic_main_scl_i [get_bd_pins axi_iic_main/scl_i] [get_bd_pins sys_i2c_mixer/upstream_scl_O] connect_bd_net -net axi_iic_main_scl_o [get_bd_pins axi_iic_main/scl_o] [get_bd_pins sys_i2c_mixer/upstream_scl_I] @@ -219,7 +220,7 @@ connect_bd_net -net axi_hdmi_tx_core_mm2s_tready [get_bd_pins axi_hdmi_core/m_ connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync] [get_bd_pins axi_hdmi_dma/mm2s_fsync] connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync_ret] -connect_bd_net -net sys_concat_intc_din_0 [get_bd_pins sys_concat_intc/In0] [get_bd_pins axi_hdmi_dma/mm2s_introut] +connect_bd_net -net sys_concat_intc_din_0 [get_bd_pins sys_concat_intc/In15] [get_bd_pins axi_hdmi_dma/mm2s_introut] # spdif audio @@ -277,7 +278,7 @@ connect_bd_net -net sys_100m_resetn [get_bd_pins axi_iic_fmc/s_axi_aresetn] connect_bd_intf_net -intf_net axi_iic_fmc_iic [get_bd_intf_ports IIC_FMC] [get_bd_intf_pins axi_iic_fmc/iic] -connect_bd_net -net sys_concat_intc_din_4 [get_bd_pins sys_concat_intc/In4] [get_bd_pins axi_iic_fmc/iic2intc_irpt] +connect_bd_net -net sys_concat_intc_din_4 [get_bd_pins sys_concat_intc/In11] [get_bd_pins axi_iic_fmc/iic2intc_irpt] # address map diff --git a/projects/daq2/common/daq2_bd.tcl b/projects/daq2/common/daq2_bd.tcl index 0ce74ff49..f01f34fb5 100644 --- a/projects/daq2/common/daq2_bd.tcl +++ b/projects/daq2/common/daq2_bd.tcl @@ -1,515 +1,540 @@ - - # daq2 - -if {$sys_zynq == 1} { - - set spi_csn_2_o [create_bd_port -dir O spi_csn_2_o] - set spi_csn_1_o [create_bd_port -dir O spi_csn_1_o] - set spi_csn_0_o [create_bd_port -dir O spi_csn_0_o] - set spi_csn_i [create_bd_port -dir I spi_csn_i] - -} else { - - set spi_csn_o [create_bd_port -dir O -from 2 -to 0 spi_csn_o] - set spi_csn_i [create_bd_port -dir I -from 2 -to 0 spi_csn_i] -} - - set spi_clk_i [create_bd_port -dir I spi_clk_i] - set spi_clk_o [create_bd_port -dir O spi_clk_o] - set spi_sdo_i [create_bd_port -dir I spi_sdo_i] - set spi_sdo_o [create_bd_port -dir O spi_sdo_o] - set spi_sdi_i [create_bd_port -dir I spi_sdi_i] - - set rx_ref_clk [create_bd_port -dir I rx_ref_clk] - set rx_sync [create_bd_port -dir O rx_sync] - set rx_sysref [create_bd_port -dir I rx_sysref] - set rx_data_p [create_bd_port -dir I -from 3 -to 0 rx_data_p] - set rx_data_n [create_bd_port -dir I -from 3 -to 0 rx_data_n] - - set tx_ref_clk [create_bd_port -dir I tx_ref_clk] - set tx_sync [create_bd_port -dir I tx_sync] - set tx_sysref [create_bd_port -dir I tx_sysref] - set tx_data_p [create_bd_port -dir O -from 3 -to 0 tx_data_p] - set tx_data_n [create_bd_port -dir O -from 3 -to 0 tx_data_n] - -if {$sys_zynq == 0} { - - set gpio_ctl_i [create_bd_port -dir I -from 5 -to 0 gpio_ctl_i] - set gpio_ctl_o [create_bd_port -dir O -from 5 -to 0 gpio_ctl_o] - set gpio_ctl_t [create_bd_port -dir O -from 5 -to 0 gpio_ctl_t] - set gpio_status_i [create_bd_port -dir I -from 4 -to 0 gpio_status_i] - set gpio_status_o [create_bd_port -dir O -from 4 -to 0 gpio_status_o] - set gpio_status_t [create_bd_port -dir O -from 4 -to 0 gpio_status_t] -} - - set dac_clk [create_bd_port -dir O dac_clk] - set dac_valid_0 [create_bd_port -dir O dac_valid_0] - set dac_enable_0 [create_bd_port -dir O dac_enable_0] - set dac_ddata_0 [create_bd_port -dir I -from 63 -to 0 dac_ddata_0] - set dac_valid_1 [create_bd_port -dir O dac_valid_1] - set dac_enable_1 [create_bd_port -dir O dac_enable_1] - set dac_ddata_1 [create_bd_port -dir I -from 63 -to 0 dac_ddata_1] - set dac_valid_2 [create_bd_port -dir O dac_valid_2] - set dac_enable_2 [create_bd_port -dir O dac_enable_2] - set dac_ddata_2 [create_bd_port -dir I -from 63 -to 0 dac_ddata_2] - set dac_valid_3 [create_bd_port -dir O dac_valid_3] - set dac_enable_3 [create_bd_port -dir O dac_enable_3] - set dac_ddata_3 [create_bd_port -dir I -from 63 -to 0 dac_ddata_3] - set dac_drd [create_bd_port -dir I dac_drd] - set dac_ddata [create_bd_port -dir O -from 127 -to 0 dac_ddata] - - set adc_clk [create_bd_port -dir O adc_clk] - set adc_enable_0 [create_bd_port -dir O adc_enable_0] - set adc_valid_0 [create_bd_port -dir O adc_valid_0] - set adc_data_0 [create_bd_port -dir O -from 63 -to 0 adc_data_0] - set adc_enable_1 [create_bd_port -dir O adc_enable_1] - set adc_valid_1 [create_bd_port -dir O adc_valid_1] - set adc_data_1 [create_bd_port -dir O -from 63 -to 0 adc_data_1] - set adc_dwr [create_bd_port -dir I adc_dwr] - set adc_dsync [create_bd_port -dir I adc_dsync] - set adc_ddata [create_bd_port -dir I -from 127 -to 0 adc_ddata] - - # dac peripherals - - set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core] - set_property -dict [list CONFIG.PCORE_QUAD_DUAL_N {0}] $axi_ad9144_core - - set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.2 axi_ad9144_jesd] - set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd - set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9144_jesd - - set axi_ad9144_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9144_dma] - set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9144_dma - set_property -dict [list CONFIG.PCORE_ID {1}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9144_dma - -if {$sys_zynq == 1} { - - set axi_ad9144_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9144_dma_interconnect] - set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9144_dma_interconnect -} - - # adc peripherals - - set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core] - - set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.2 axi_ad9680_jesd] - set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd - set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd - - set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma] - set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9680_dma - set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9680_dma - -if {$sys_zynq == 1} { - - set axi_ad9680_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9680_dma_interconnect] - set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9680_dma_interconnect -} - - # dac/adc common gt/gpio - - set axi_daq2_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq2_gt] - set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {4}] $axi_daq2_gt - -if {$sys_zynq == 1} { - - set axi_daq2_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_daq2_gt_interconnect] - set_property -dict [list CONFIG.NUM_MI {1}] $axi_daq2_gt_interconnect -} - - # gpio and spi - -if {$sys_zynq == 0} { - - set axi_daq2_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_daq2_spi] - set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_daq2_spi - set_property -dict [list CONFIG.C_NUM_SS_BITS {3}] $axi_daq2_spi - set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_daq2_spi - - set axi_daq2_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_daq2_gpio] - set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_daq2_gpio - set_property -dict [list CONFIG.C_GPIO_WIDTH {5}] $axi_daq2_gpio - set_property -dict [list CONFIG.C_GPIO2_WIDTH {6}] $axi_daq2_gpio - set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_daq2_gpio -} - - # additions to default configuration - -if {$sys_zynq == 0} { - - set_property -dict [list CONFIG.NUM_MI {16}] $axi_cpu_interconnect - -} else { - - set_property -dict [list CONFIG.NUM_MI {14}] $axi_cpu_interconnect -} - -if {$sys_zynq == 0} { - - set_property -dict [list CONFIG.NUM_SI {11}] $axi_mem_interconnect - set_property -dict [list CONFIG.NUM_PORTS {7}] $sys_concat_intc -} - -if {$sys_zynq == 1} { - - set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7 - set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7 - set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $sys_ps7 - set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7 - set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7 - set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7 - set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {43}] $sys_ps7 - set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7 - set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7 - - set_property LEFT 42 [get_bd_ports GPIO_I] - set_property LEFT 42 [get_bd_ports GPIO_O] - set_property LEFT 42 [get_bd_ports GPIO_T] -} - - # connections (spi and gpio) - -if {$sys_zynq == 0} { - - connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_daq2_spi/ss_i] - connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_daq2_spi/ss_o] - connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_daq2_spi/sck_i] - connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_daq2_spi/sck_o] - connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_daq2_spi/io0_i] - connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_daq2_spi/io0_o] - connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_daq2_spi/io1_i] - -} else { - - connect_bd_net -net spi_csn_2_o [get_bd_ports spi_csn_2_o] [get_bd_pins sys_ps7/SPI0_SS2_O] - connect_bd_net -net spi_csn_1_o [get_bd_ports spi_csn_1_o] [get_bd_pins sys_ps7/SPI0_SS1_O] - connect_bd_net -net spi_csn_0_o [get_bd_ports spi_csn_0_o] [get_bd_pins sys_ps7/SPI0_SS_O] - connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I] - connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I] - connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O] - connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I] - connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O] - connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I] -} - -if {$sys_zynq == 0} { - - connect_bd_net -net gpio_status_i [get_bd_ports gpio_status_i] [get_bd_pins axi_daq2_gpio/gpio_io_i] - connect_bd_net -net gpio_status_o [get_bd_ports gpio_status_o] [get_bd_pins axi_daq2_gpio/gpio_io_o] - connect_bd_net -net gpio_status_t [get_bd_ports gpio_status_t] [get_bd_pins axi_daq2_gpio/gpio_io_t] - connect_bd_net -net gpio_ctl_i [get_bd_ports gpio_ctl_i] [get_bd_pins axi_daq2_gpio/gpio2_io_i] - connect_bd_net -net gpio_ctl_o [get_bd_ports gpio_ctl_o] [get_bd_pins axi_daq2_gpio/gpio2_io_o] - connect_bd_net -net gpio_ctl_t [get_bd_ports gpio_ctl_t] [get_bd_pins axi_daq2_gpio/gpio2_io_t] -} - -if {$sys_zynq == 0} { - - delete_bd_objs [get_bd_nets sys_concat_intc_din_2] [get_bd_ports unc_int2] - delete_bd_objs [get_bd_nets sys_concat_intc_din_3] [get_bd_ports unc_int3] -} - - # connections (gt) - - connect_bd_net -net axi_daq2_gt_ref_clk_q [get_bd_pins axi_daq2_gt/ref_clk_q] [get_bd_ports rx_ref_clk] - connect_bd_net -net axi_daq2_gt_ref_clk_c [get_bd_pins axi_daq2_gt/ref_clk_c] [get_bd_ports tx_ref_clk] - connect_bd_net -net axi_daq2_gt_rx_data_p [get_bd_pins axi_daq2_gt/rx_data_p] [get_bd_ports rx_data_p] - connect_bd_net -net axi_daq2_gt_rx_data_n [get_bd_pins axi_daq2_gt/rx_data_n] [get_bd_ports rx_data_n] - connect_bd_net -net axi_daq2_gt_rx_sync [get_bd_pins axi_daq2_gt/rx_sync] [get_bd_ports rx_sync] - connect_bd_net -net axi_daq2_gt_rx_ext_sysref [get_bd_pins axi_daq2_gt/rx_ext_sysref] [get_bd_ports rx_sysref] - connect_bd_net -net axi_daq2_gt_tx_data_p [get_bd_pins axi_daq2_gt/tx_data_p] [get_bd_ports tx_data_p] - connect_bd_net -net axi_daq2_gt_tx_data_n [get_bd_pins axi_daq2_gt/tx_data_n] [get_bd_ports tx_data_n] - connect_bd_net -net axi_daq2_gt_tx_sync [get_bd_pins axi_daq2_gt/tx_sync] [get_bd_ports tx_sync] - connect_bd_net -net axi_daq2_gt_tx_ext_sysref [get_bd_pins axi_daq2_gt/tx_ext_sysref] [get_bd_ports tx_sysref] - - # connections (dac) - - connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_daq2_gt/tx_clk_g] - connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_daq2_gt/tx_clk] - connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_ad9144_core/tx_clk] - connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_ad9144_jesd/tx_core_clk] - - connect_bd_net -net axi_daq2_gt_tx_rst [get_bd_pins axi_daq2_gt/tx_rst] [get_bd_pins axi_ad9144_jesd/tx_reset] - connect_bd_net -net axi_daq2_gt_tx_sysref [get_bd_pins axi_daq2_gt/tx_sysref] [get_bd_pins axi_ad9144_jesd/tx_sysref] - connect_bd_net -net axi_daq2_gt_tx_gt_charisk [get_bd_pins axi_daq2_gt/tx_gt_charisk] [get_bd_pins axi_ad9144_jesd/gt_txcharisk_out] - connect_bd_net -net axi_daq2_gt_tx_gt_data [get_bd_pins axi_daq2_gt/tx_gt_data] [get_bd_pins axi_ad9144_jesd/gt_txdata_out] - connect_bd_net -net axi_daq2_gt_tx_rst_done [get_bd_pins axi_daq2_gt/tx_rst_done] [get_bd_pins axi_ad9144_jesd/tx_reset_done] - connect_bd_net -net axi_daq2_gt_tx_ip_sync [get_bd_pins axi_daq2_gt/tx_ip_sync] [get_bd_pins axi_ad9144_jesd/tx_sync] - connect_bd_net -net axi_daq2_gt_tx_ip_sof [get_bd_pins axi_daq2_gt/tx_ip_sof] [get_bd_pins axi_ad9144_jesd/tx_start_of_frame] - connect_bd_net -net axi_daq2_gt_tx_ip_data [get_bd_pins axi_daq2_gt/tx_ip_data] [get_bd_pins axi_ad9144_jesd/tx_tdata] - connect_bd_net -net axi_daq2_gt_tx_data [get_bd_pins axi_daq2_gt/tx_data] [get_bd_pins axi_ad9144_core/tx_data] - connect_bd_net -net axi_ad9144_dac_clk [get_bd_pins axi_ad9144_core/dac_clk] [get_bd_pins axi_ad9144_dma/fifo_rd_clk] - connect_bd_net -net axi_ad9144_dac_valid_0 [get_bd_pins axi_ad9144_core/dac_valid_0] [get_bd_ports dac_valid_0] - connect_bd_net -net axi_ad9144_dac_enable_0 [get_bd_pins axi_ad9144_core/dac_enable_0] [get_bd_ports dac_enable_0] - connect_bd_net -net axi_ad9144_dac_ddata_0 [get_bd_pins axi_ad9144_core/dac_ddata_0] [get_bd_ports dac_ddata_0] - connect_bd_net -net axi_ad9144_dac_valid_1 [get_bd_pins axi_ad9144_core/dac_valid_1] [get_bd_ports dac_valid_1] - connect_bd_net -net axi_ad9144_dac_enable_1 [get_bd_pins axi_ad9144_core/dac_enable_1] [get_bd_ports dac_enable_1] - connect_bd_net -net axi_ad9144_dac_ddata_1 [get_bd_pins axi_ad9144_core/dac_ddata_1] [get_bd_ports dac_ddata_1] - connect_bd_net -net axi_ad9144_dac_valid_2 [get_bd_pins axi_ad9144_core/dac_valid_2] [get_bd_ports dac_valid_2] - connect_bd_net -net axi_ad9144_dac_enable_2 [get_bd_pins axi_ad9144_core/dac_enable_2] [get_bd_ports dac_enable_2] - connect_bd_net -net axi_ad9144_dac_ddata_2 [get_bd_pins axi_ad9144_core/dac_ddata_2] [get_bd_ports dac_ddata_2] - connect_bd_net -net axi_ad9144_dac_valid_3 [get_bd_pins axi_ad9144_core/dac_valid_3] [get_bd_ports dac_valid_3] - connect_bd_net -net axi_ad9144_dac_enable_3 [get_bd_pins axi_ad9144_core/dac_enable_3] [get_bd_ports dac_enable_3] - connect_bd_net -net axi_ad9144_dac_ddata_3 [get_bd_pins axi_ad9144_core/dac_ddata_3] [get_bd_ports dac_ddata_3] - connect_bd_net -net axi_ad9144_dac_drd [get_bd_ports dac_drd] [get_bd_pins axi_ad9144_dma/fifo_rd_en] - connect_bd_net -net axi_ad9144_dac_ddata [get_bd_ports dac_ddata] [get_bd_pins axi_ad9144_dma/fifo_rd_dout] - connect_bd_net -net axi_ad9144_dac_dunf [get_bd_pins axi_ad9144_core/dac_dunf] [get_bd_pins axi_ad9144_dma/fifo_rd_underflow] - connect_bd_net -net axi_ad9144_dma_irq [get_bd_pins axi_ad9144_dma/irq] [get_bd_pins sys_concat_intc/In12] - - # connections (adc) - - connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_daq2_gt/rx_clk_g] - connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_daq2_gt/rx_clk] - connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_ad9680_core/rx_clk] - connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_ad9680_jesd/rx_core_clk] - - connect_bd_net -net axi_daq2_gt_rx_rst [get_bd_pins axi_daq2_gt/rx_rst] [get_bd_pins axi_ad9680_jesd/rx_reset] - connect_bd_net -net axi_daq2_gt_rx_sysref [get_bd_pins axi_daq2_gt/rx_sysref] [get_bd_pins axi_ad9680_jesd/rx_sysref] - connect_bd_net -net axi_daq2_gt_rx_gt_charisk [get_bd_pins axi_daq2_gt/rx_gt_charisk] [get_bd_pins axi_ad9680_jesd/gt_rxcharisk_in] - connect_bd_net -net axi_daq2_gt_rx_gt_disperr [get_bd_pins axi_daq2_gt/rx_gt_disperr] [get_bd_pins axi_ad9680_jesd/gt_rxdisperr_in] - connect_bd_net -net axi_daq2_gt_rx_gt_notintable [get_bd_pins axi_daq2_gt/rx_gt_notintable] [get_bd_pins axi_ad9680_jesd/gt_rxnotintable_in] - connect_bd_net -net axi_daq2_gt_rx_gt_data [get_bd_pins axi_daq2_gt/rx_gt_data] [get_bd_pins axi_ad9680_jesd/gt_rxdata_in] - connect_bd_net -net axi_daq2_gt_rx_rst_done [get_bd_pins axi_daq2_gt/rx_rst_done] [get_bd_pins axi_ad9680_jesd/rx_reset_done] - connect_bd_net -net axi_daq2_gt_rx_ip_comma_align [get_bd_pins axi_daq2_gt/rx_ip_comma_align] [get_bd_pins axi_ad9680_jesd/rxencommaalign_out] - connect_bd_net -net axi_daq2_gt_rx_ip_sync [get_bd_pins axi_daq2_gt/rx_ip_sync] [get_bd_pins axi_ad9680_jesd/rx_sync] - connect_bd_net -net axi_daq2_gt_rx_ip_sof [get_bd_pins axi_daq2_gt/rx_ip_sof] [get_bd_pins axi_ad9680_jesd/rx_start_of_frame] - connect_bd_net -net axi_daq2_gt_rx_ip_data [get_bd_pins axi_daq2_gt/rx_ip_data] [get_bd_pins axi_ad9680_jesd/rx_tdata] - connect_bd_net -net axi_daq2_gt_rx_data [get_bd_pins axi_daq2_gt/rx_data] [get_bd_pins axi_ad9680_core/rx_data] - connect_bd_net -net axi_ad9680_adc_clk [get_bd_pins axi_ad9680_core/adc_clk] [get_bd_pins axi_ad9680_dma/fifo_wr_clk] - connect_bd_net -net axi_ad9680_adc_enable_0 [get_bd_pins axi_ad9680_core/adc_enable_0] [get_bd_ports adc_enable_0] - connect_bd_net -net axi_ad9680_adc_valid_0 [get_bd_pins axi_ad9680_core/adc_valid_0] [get_bd_ports adc_valid_0] - connect_bd_net -net axi_ad9680_adc_data_0 [get_bd_pins axi_ad9680_core/adc_data_0] [get_bd_ports adc_data_0] - connect_bd_net -net axi_ad9680_adc_enable_1 [get_bd_pins axi_ad9680_core/adc_enable_1] [get_bd_ports adc_enable_1] - connect_bd_net -net axi_ad9680_adc_valid_1 [get_bd_pins axi_ad9680_core/adc_valid_1] [get_bd_ports adc_valid_1] - connect_bd_net -net axi_ad9680_adc_data_1 [get_bd_pins axi_ad9680_core/adc_data_1] [get_bd_ports adc_data_1] - connect_bd_net -net axi_ad9680_adc_dwr [get_bd_ports adc_dwr] [get_bd_pins axi_ad9680_dma/fifo_wr_en] - connect_bd_net -net axi_ad9680_adc_dsync [get_bd_ports adc_dsync] [get_bd_pins axi_ad9680_dma/fifo_wr_sync] - connect_bd_net -net axi_ad9680_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins axi_ad9680_dma/fifo_wr_din] - connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins axi_ad9680_dma/fifo_wr_overflow] - connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In13] - - # dac/adc clocks - - connect_bd_net -net axi_ad9144_dac_clk [get_bd_ports dac_clk] - connect_bd_net -net axi_ad9680_adc_clk [get_bd_ports adc_clk] - - # interconnect (cpu) - - connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9144_dma/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9144_core/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9144_jesd/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9680_dma/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_ad9680_core/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_ad9680_jesd/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_daq2_gt/s_axi] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/s_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_core/s_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_jesd/s_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_dma/s_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_core/s_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_jesd/s_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma/s_axi_aclk] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt/s_axi_aresetn] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_core/s_axi_aresetn] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_jesd/s_axi_aresetn] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_dma/s_axi_aresetn] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_core/s_axi_aresetn] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_jesd/s_axi_aresetn] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma/s_axi_aresetn] - -if {$sys_zynq == 0} { - - connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_daq2_spi/axi_lite] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m15_axi [get_bd_intf_pins axi_cpu_interconnect/M15_AXI] [get_bd_intf_pins axi_daq2_gpio/s_axi] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M15_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_spi/s_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_spi/ext_spi_clk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gpio/s_axi_aclk] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M15_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_spi/s_axi_aresetn] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gpio/s_axi_aresetn] - - connect_bd_net -net axi_daq2_spi_irq [get_bd_pins axi_daq2_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5] - connect_bd_net -net axi_daq2_gpio_irq [get_bd_pins axi_daq2_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In6] -} - - # gt uses hp3, and 100MHz clock for both DRP and AXI4 - -if {$sys_zynq == 0} { - - connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_daq2_gt/m_axi] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/m_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/drp_clk] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt/m_axi_aresetn] - -} else { - - connect_bd_intf_net -intf_net axi_daq2_gt_interconnect_m00_axi [get_bd_intf_pins axi_daq2_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3] - connect_bd_intf_net -intf_net axi_daq2_gt_interconnect_s00_axi [get_bd_intf_pins axi_daq2_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_daq2_gt/m_axi] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt_interconnect/ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt_interconnect/M00_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt_interconnect/S00_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP3_ACLK] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/m_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/drp_clk] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt_interconnect/ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt/m_axi_aresetn] -} - - # memory interconnects share the same clock (fclk2) - -if {$sys_zynq == 1} { - set sys_fmc_dma_sync_reset [create_bd_cell -type ip -vlnv analog.com:user:util_sync_reset:1.0 sys_fmc_dma_sync_reset] - - set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2] - set sys_fmc_dma_resetn_source [get_bd_pins sys_fmc_dma_sync_reset/sync_resetn] - - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_fmc_dma_sync_reset/clk] - connect_bd_net -net sys_fmc_dma_async_reset \ - [get_bd_pins sys_fmc_dma_sync_reset/async_resetn] \ - [get_bd_pins sys_ps7/FCLK_RESET2_N] - - connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source -} - - # interconnect (mem/dac) - -if {$sys_zynq == 0} { - - connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9144_dma/m_src_axi] - connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_200m_clk_source - connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9144_dma/m_src_axi_aclk] - connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_200m_resetn_source - connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9144_dma/m_src_axi_aresetn] - - connect_bd_intf_net -intf_net axi_mem_interconnect_s10_axi [get_bd_intf_pins axi_mem_interconnect/S10_AXI] [get_bd_intf_pins axi_ad9680_dma/m_dest_axi] - connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S10_ACLK] $sys_200m_clk_source - connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk] - connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S10_ARESETN] $sys_200m_resetn_source - connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn] - -} else { - - connect_bd_intf_net -intf_net axi_ad9144_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9144_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1] - connect_bd_intf_net -intf_net axi_ad9144_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9144_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9144_dma/m_src_axi] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma_interconnect/ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma/m_src_axi_aclk] - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma/m_src_axi_aresetn] - - connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2] - connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9680_dma/m_dest_axi] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk] - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn] -} - - # ila - - set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_rx_mon] - set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_PROBE0_WIDTH {334}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_PROBE2_WIDTH {128}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_PROBE3_WIDTH {128}] $ila_jesd_rx_mon - - connect_bd_net -net axi_daq2_gt_rx_mon_data [get_bd_pins axi_daq2_gt/rx_mon_data] - connect_bd_net -net axi_daq2_gt_rx_mon_trigger [get_bd_pins axi_daq2_gt/rx_mon_trigger] - connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK] - connect_bd_net -net axi_daq2_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0] - connect_bd_net -net axi_daq2_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1] - connect_bd_net -net axi_daq2_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2] - connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3] - - set ila_jesd_tx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_tx_mon] - set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_tx_mon - set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_jesd_tx_mon - set_property -dict [list CONFIG.C_PROBE0_WIDTH {150}] $ila_jesd_tx_mon - set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_tx_mon - - connect_bd_net -net axi_daq2_gt_tx_mon_data [get_bd_pins axi_daq2_gt/tx_mon_data] - connect_bd_net -net axi_daq2_gt_tx_mon_trigger [get_bd_pins axi_daq2_gt/tx_mon_trigger] - connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins ila_jesd_tx_mon/CLK] - connect_bd_net -net axi_daq2_gt_tx_mon_data [get_bd_pins ila_jesd_tx_mon/PROBE0] - connect_bd_net -net axi_daq2_gt_tx_mon_trigger [get_bd_pins ila_jesd_tx_mon/PROBE1] - - # address map - - create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_core/s_axi/axi_lite] SEG_data_ad9144_core - create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_core/s_axi/axi_lite] SEG_data_ad9680_core - create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_gt/s_axi/axi_lite] SEG_data_daq2_gt - create_bd_addr_seg -range 0x00001000 -offset 0x44A90000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_jesd/s_axi/Reg] SEG_data_ad9144_jesd - create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_jesd/s_axi/Reg] SEG_data_ad9680_jesd - create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_dma/s_axi/axi_lite] SEG_data_ad9680_dma - create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_dma/s_axi/axi_lite] SEG_data_ad9144_dma - -if {$sys_zynq == 0} { - - create_bd_addr_seg -range 0x00010000 -offset 0x40000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_gpio/S_AXI/Reg] SEG_data_daq2_gpio - create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_spi/axi_lite/Reg] SEG_data_daq2_spi -} - -if {$sys_zynq == 0} { - - create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9144_dma/m_src_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl - create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl - create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_daq2_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl - -} else { - - create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9144_dma/m_src_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm - create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm - create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_daq2_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm -} - + + # daq2 + +if {$sys_zynq == 1} { + + set spi_csn_2_o [create_bd_port -dir O spi_csn_2_o] + set spi_csn_1_o [create_bd_port -dir O spi_csn_1_o] + set spi_csn_0_o [create_bd_port -dir O spi_csn_0_o] + set spi_csn_i [create_bd_port -dir I spi_csn_i] + +} else { + + set spi_csn_o [create_bd_port -dir O -from 2 -to 0 spi_csn_o] + set spi_csn_i [create_bd_port -dir I -from 2 -to 0 spi_csn_i] +} + + set spi_clk_i [create_bd_port -dir I spi_clk_i] + set spi_clk_o [create_bd_port -dir O spi_clk_o] + set spi_sdo_i [create_bd_port -dir I spi_sdo_i] + set spi_sdo_o [create_bd_port -dir O spi_sdo_o] + set spi_sdi_i [create_bd_port -dir I spi_sdi_i] + + set rx_ref_clk [create_bd_port -dir I rx_ref_clk] + set rx_sync [create_bd_port -dir O rx_sync] + set rx_sysref [create_bd_port -dir I rx_sysref] + set rx_data_p [create_bd_port -dir I -from 3 -to 0 rx_data_p] + set rx_data_n [create_bd_port -dir I -from 3 -to 0 rx_data_n] + + set tx_ref_clk [create_bd_port -dir I tx_ref_clk] + set tx_sync [create_bd_port -dir I tx_sync] + set tx_sysref [create_bd_port -dir I tx_sysref] + set tx_data_p [create_bd_port -dir O -from 3 -to 0 tx_data_p] + set tx_data_n [create_bd_port -dir O -from 3 -to 0 tx_data_n] + +if {$sys_zynq == 0} { + + set gpio_ctl_i [create_bd_port -dir I -from 5 -to 0 gpio_ctl_i] + set gpio_ctl_o [create_bd_port -dir O -from 5 -to 0 gpio_ctl_o] + set gpio_ctl_t [create_bd_port -dir O -from 5 -to 0 gpio_ctl_t] + set gpio_status_i [create_bd_port -dir I -from 4 -to 0 gpio_status_i] + set gpio_status_o [create_bd_port -dir O -from 4 -to 0 gpio_status_o] + set gpio_status_t [create_bd_port -dir O -from 4 -to 0 gpio_status_t] +} + + set dac_clk [create_bd_port -dir O dac_clk] + set dac_valid_0 [create_bd_port -dir O dac_valid_0] + set dac_enable_0 [create_bd_port -dir O dac_enable_0] + set dac_ddata_0 [create_bd_port -dir I -from 63 -to 0 dac_ddata_0] + set dac_valid_1 [create_bd_port -dir O dac_valid_1] + set dac_enable_1 [create_bd_port -dir O dac_enable_1] + set dac_ddata_1 [create_bd_port -dir I -from 63 -to 0 dac_ddata_1] + set dac_valid_2 [create_bd_port -dir O dac_valid_2] + set dac_enable_2 [create_bd_port -dir O dac_enable_2] + set dac_ddata_2 [create_bd_port -dir I -from 63 -to 0 dac_ddata_2] + set dac_valid_3 [create_bd_port -dir O dac_valid_3] + set dac_enable_3 [create_bd_port -dir O dac_enable_3] + set dac_ddata_3 [create_bd_port -dir I -from 63 -to 0 dac_ddata_3] + set dac_drd [create_bd_port -dir I dac_drd] + set dac_ddata [create_bd_port -dir O -from 127 -to 0 dac_ddata] + + set adc_clk [create_bd_port -dir O adc_clk] + set adc_enable_0 [create_bd_port -dir O adc_enable_0] + set adc_valid_0 [create_bd_port -dir O adc_valid_0] + set adc_data_0 [create_bd_port -dir O -from 63 -to 0 adc_data_0] + set adc_enable_1 [create_bd_port -dir O adc_enable_1] + set adc_valid_1 [create_bd_port -dir O adc_valid_1] + set adc_data_1 [create_bd_port -dir O -from 63 -to 0 adc_data_1] + set adc_dwr [create_bd_port -dir I adc_dwr] + set adc_dsync [create_bd_port -dir I adc_dsync] + set adc_ddata [create_bd_port -dir I -from 127 -to 0 adc_ddata] + +if {$sys_zynq == 1} { + + set DDR3 [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3] + set sys_clk [create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk] +} + + set axi_ad9144_dma_intr [create_bd_port -dir O axi_ad9144_dma_intr] + set axi_ad9680_dma_intr [create_bd_port -dir O axi_ad9680_dma_intr] + set axi_daq2_spi_intr [create_bd_port -dir O axi_daq2_spi_intr ] + set axi_daq2_gpio_intr [create_bd_port -dir O axi_daq2_gpio_intr ] + + # dac peripherals + + set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core] + set_property -dict [list CONFIG.PCORE_QUAD_DUAL_N {0}] $axi_ad9144_core + + set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.2 axi_ad9144_jesd] + set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd + set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9144_jesd + + set axi_ad9144_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9144_dma] + set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9144_dma + set_property -dict [list CONFIG.PCORE_ID {1}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9144_dma + +if {$sys_zynq == 1} { + + set axi_ad9144_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9144_dma_interconnect] + set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9144_dma_interconnect +} + + # adc peripherals + + set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core] + + set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.2 axi_ad9680_jesd] + set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd + set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd + + set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma] + set_property -dict [list CONFIG.C_DMA_TYPE_SRC {1}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma + +if {$sys_zynq == 1} { + + p_plddr3_fifo [current_bd_instance .] axi_ad9680_fifo 128 + +} else { + + p_sys_dmafifo [current_bd_instance .] axi_ad9680_fifo 128 +} + +if {$sys_zynq == 1} { + + set axi_ad9680_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9680_dma_interconnect] + set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9680_dma_interconnect +} + + # dac/adc common gt/gpio + + set axi_daq2_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq2_gt] + set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {4}] $axi_daq2_gt + set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_0 {0}] $axi_daq2_gt + set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_1 {3}] $axi_daq2_gt + set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_2 {1}] $axi_daq2_gt + set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_3 {2}] $axi_daq2_gt + +if {$sys_zynq == 1} { + + set axi_daq2_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_daq2_gt_interconnect] + set_property -dict [list CONFIG.NUM_MI {1}] $axi_daq2_gt_interconnect +} + + # gpio and spi + +if {$sys_zynq == 0} { + + set axi_daq2_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_daq2_spi] + set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_daq2_spi + set_property -dict [list CONFIG.C_NUM_SS_BITS {3}] $axi_daq2_spi + set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_daq2_spi + + set axi_daq2_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_daq2_gpio] + set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_daq2_gpio + set_property -dict [list CONFIG.C_GPIO_WIDTH {5}] $axi_daq2_gpio + set_property -dict [list CONFIG.C_GPIO2_WIDTH {6}] $axi_daq2_gpio + set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_daq2_gpio +} + + # additions to default configuration + +if {$sys_zynq == 0} { + + set_property -dict [list CONFIG.NUM_MI {16}] $axi_cpu_interconnect + +} else { + + set_property -dict [list CONFIG.NUM_MI {14}] $axi_cpu_interconnect +} + +if {$sys_zynq == 0} { + + set_property -dict [list CONFIG.NUM_SI {11}] $axi_mem_interconnect +} + +if {$sys_zynq == 1} { + + set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7 + set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {44}] $sys_ps7 + set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7 + + set_property LEFT 43 [get_bd_ports GPIO_I] + set_property LEFT 43 [get_bd_ports GPIO_O] + set_property LEFT 43 [get_bd_ports GPIO_T] +} + + # connections (pl ddr3) + +if {$sys_zynq == 1} { + + connect_bd_intf_net -intf_net DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins axi_ad9680_fifo/DDR3] + connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins axi_ad9680_fifo/sys_clk] +} + + # connections (spi and gpio) + +if {$sys_zynq == 0} { + + connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_daq2_spi/ss_i] + connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_daq2_spi/ss_o] + connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_daq2_spi/sck_i] + connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_daq2_spi/sck_o] + connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_daq2_spi/io0_i] + connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_daq2_spi/io0_o] + connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_daq2_spi/io1_i] + +} else { + + connect_bd_net -net spi_csn_2_o [get_bd_ports spi_csn_2_o] [get_bd_pins sys_ps7/SPI0_SS2_O] + connect_bd_net -net spi_csn_1_o [get_bd_ports spi_csn_1_o] [get_bd_pins sys_ps7/SPI0_SS1_O] + connect_bd_net -net spi_csn_0_o [get_bd_ports spi_csn_0_o] [get_bd_pins sys_ps7/SPI0_SS_O] + connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I] + connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I] + connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O] + connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I] + connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O] + connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I] +} + +if {$sys_zynq == 0} { + + connect_bd_net -net gpio_status_i [get_bd_ports gpio_status_i] [get_bd_pins axi_daq2_gpio/gpio_io_i] + connect_bd_net -net gpio_status_o [get_bd_ports gpio_status_o] [get_bd_pins axi_daq2_gpio/gpio_io_o] + connect_bd_net -net gpio_status_t [get_bd_ports gpio_status_t] [get_bd_pins axi_daq2_gpio/gpio_io_t] + connect_bd_net -net gpio_ctl_i [get_bd_ports gpio_ctl_i] [get_bd_pins axi_daq2_gpio/gpio2_io_i] + connect_bd_net -net gpio_ctl_o [get_bd_ports gpio_ctl_o] [get_bd_pins axi_daq2_gpio/gpio2_io_o] + connect_bd_net -net gpio_ctl_t [get_bd_ports gpio_ctl_t] [get_bd_pins axi_daq2_gpio/gpio2_io_t] +} + + # connections (gt) + + connect_bd_net -net axi_daq2_gt_ref_clk_q [get_bd_pins axi_daq2_gt/ref_clk_q] [get_bd_ports rx_ref_clk] + connect_bd_net -net axi_daq2_gt_ref_clk_c [get_bd_pins axi_daq2_gt/ref_clk_c] [get_bd_ports tx_ref_clk] + connect_bd_net -net axi_daq2_gt_rx_data_p [get_bd_pins axi_daq2_gt/rx_data_p] [get_bd_ports rx_data_p] + connect_bd_net -net axi_daq2_gt_rx_data_n [get_bd_pins axi_daq2_gt/rx_data_n] [get_bd_ports rx_data_n] + connect_bd_net -net axi_daq2_gt_rx_sync [get_bd_pins axi_daq2_gt/rx_sync] [get_bd_ports rx_sync] + connect_bd_net -net axi_daq2_gt_rx_ext_sysref [get_bd_pins axi_daq2_gt/rx_ext_sysref] [get_bd_ports rx_sysref] + connect_bd_net -net axi_daq2_gt_tx_data_p [get_bd_pins axi_daq2_gt/tx_data_p] [get_bd_ports tx_data_p] + connect_bd_net -net axi_daq2_gt_tx_data_n [get_bd_pins axi_daq2_gt/tx_data_n] [get_bd_ports tx_data_n] + connect_bd_net -net axi_daq2_gt_tx_sync [get_bd_pins axi_daq2_gt/tx_sync] [get_bd_ports tx_sync] + connect_bd_net -net axi_daq2_gt_tx_ext_sysref [get_bd_pins axi_daq2_gt/tx_ext_sysref] [get_bd_ports tx_sysref] + + # connections (dac) + + connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_daq2_gt/tx_clk_g] + connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_daq2_gt/tx_clk] + connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_ad9144_core/tx_clk] + connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_ad9144_jesd/tx_core_clk] + + connect_bd_net -net axi_daq2_gt_tx_rst [get_bd_pins axi_daq2_gt/tx_rst] [get_bd_pins axi_ad9144_jesd/tx_reset] + connect_bd_net -net axi_daq2_gt_tx_sysref [get_bd_pins axi_daq2_gt/tx_sysref] [get_bd_pins axi_ad9144_jesd/tx_sysref] + connect_bd_net -net axi_daq2_gt_tx_gt_charisk [get_bd_pins axi_daq2_gt/tx_gt_charisk] [get_bd_pins axi_ad9144_jesd/gt_txcharisk_out] + connect_bd_net -net axi_daq2_gt_tx_gt_data [get_bd_pins axi_daq2_gt/tx_gt_data] [get_bd_pins axi_ad9144_jesd/gt_txdata_out] + connect_bd_net -net axi_daq2_gt_tx_rst_done [get_bd_pins axi_daq2_gt/tx_rst_done] [get_bd_pins axi_ad9144_jesd/tx_reset_done] + connect_bd_net -net axi_daq2_gt_tx_ip_sync [get_bd_pins axi_daq2_gt/tx_ip_sync] [get_bd_pins axi_ad9144_jesd/tx_sync] + connect_bd_net -net axi_daq2_gt_tx_ip_sof [get_bd_pins axi_daq2_gt/tx_ip_sof] [get_bd_pins axi_ad9144_jesd/tx_start_of_frame] + connect_bd_net -net axi_daq2_gt_tx_ip_data [get_bd_pins axi_daq2_gt/tx_ip_data] [get_bd_pins axi_ad9144_jesd/tx_tdata] + connect_bd_net -net axi_daq2_gt_tx_data [get_bd_pins axi_daq2_gt/tx_data] [get_bd_pins axi_ad9144_core/tx_data] + connect_bd_net -net axi_ad9144_dac_clk [get_bd_pins axi_ad9144_core/dac_clk] [get_bd_pins axi_ad9144_dma/fifo_rd_clk] + connect_bd_net -net axi_ad9144_dac_valid_0 [get_bd_pins axi_ad9144_core/dac_valid_0] [get_bd_ports dac_valid_0] + connect_bd_net -net axi_ad9144_dac_enable_0 [get_bd_pins axi_ad9144_core/dac_enable_0] [get_bd_ports dac_enable_0] + connect_bd_net -net axi_ad9144_dac_ddata_0 [get_bd_pins axi_ad9144_core/dac_ddata_0] [get_bd_ports dac_ddata_0] + connect_bd_net -net axi_ad9144_dac_valid_1 [get_bd_pins axi_ad9144_core/dac_valid_1] [get_bd_ports dac_valid_1] + connect_bd_net -net axi_ad9144_dac_enable_1 [get_bd_pins axi_ad9144_core/dac_enable_1] [get_bd_ports dac_enable_1] + connect_bd_net -net axi_ad9144_dac_ddata_1 [get_bd_pins axi_ad9144_core/dac_ddata_1] [get_bd_ports dac_ddata_1] + connect_bd_net -net axi_ad9144_dac_valid_2 [get_bd_pins axi_ad9144_core/dac_valid_2] [get_bd_ports dac_valid_2] + connect_bd_net -net axi_ad9144_dac_enable_2 [get_bd_pins axi_ad9144_core/dac_enable_2] [get_bd_ports dac_enable_2] + connect_bd_net -net axi_ad9144_dac_ddata_2 [get_bd_pins axi_ad9144_core/dac_ddata_2] [get_bd_ports dac_ddata_2] + connect_bd_net -net axi_ad9144_dac_valid_3 [get_bd_pins axi_ad9144_core/dac_valid_3] [get_bd_ports dac_valid_3] + connect_bd_net -net axi_ad9144_dac_enable_3 [get_bd_pins axi_ad9144_core/dac_enable_3] [get_bd_ports dac_enable_3] + connect_bd_net -net axi_ad9144_dac_ddata_3 [get_bd_pins axi_ad9144_core/dac_ddata_3] [get_bd_ports dac_ddata_3] + connect_bd_net -net axi_ad9144_dac_drd [get_bd_ports dac_drd] [get_bd_pins axi_ad9144_dma/fifo_rd_en] + connect_bd_net -net axi_ad9144_dac_ddata [get_bd_ports dac_ddata] [get_bd_pins axi_ad9144_dma/fifo_rd_dout] + connect_bd_net -net axi_ad9144_dac_dunf [get_bd_pins axi_ad9144_core/dac_dunf] [get_bd_pins axi_ad9144_dma/fifo_rd_underflow] + connect_bd_net -net axi_ad9144_dma_intr [get_bd_pins axi_ad9144_dma/irq] [get_bd_ports axi_ad9144_dma_intr] + + # connections (adc) + + connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_daq2_gt/rx_clk_g] + connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_daq2_gt/rx_clk] + connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_ad9680_core/rx_clk] + connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_ad9680_jesd/rx_core_clk] + + connect_bd_net -net axi_daq2_gt_rx_rst [get_bd_pins axi_daq2_gt/rx_rst] [get_bd_pins axi_ad9680_jesd/rx_reset] + connect_bd_net -net axi_daq2_gt_rx_sysref [get_bd_pins axi_daq2_gt/rx_sysref] [get_bd_pins axi_ad9680_jesd/rx_sysref] + connect_bd_net -net axi_daq2_gt_rx_gt_charisk [get_bd_pins axi_daq2_gt/rx_gt_charisk] [get_bd_pins axi_ad9680_jesd/gt_rxcharisk_in] + connect_bd_net -net axi_daq2_gt_rx_gt_disperr [get_bd_pins axi_daq2_gt/rx_gt_disperr] [get_bd_pins axi_ad9680_jesd/gt_rxdisperr_in] + connect_bd_net -net axi_daq2_gt_rx_gt_notintable [get_bd_pins axi_daq2_gt/rx_gt_notintable] [get_bd_pins axi_ad9680_jesd/gt_rxnotintable_in] + connect_bd_net -net axi_daq2_gt_rx_gt_data [get_bd_pins axi_daq2_gt/rx_gt_data] [get_bd_pins axi_ad9680_jesd/gt_rxdata_in] + connect_bd_net -net axi_daq2_gt_rx_rst_done [get_bd_pins axi_daq2_gt/rx_rst_done] [get_bd_pins axi_ad9680_jesd/rx_reset_done] + connect_bd_net -net axi_daq2_gt_rx_ip_comma_align [get_bd_pins axi_daq2_gt/rx_ip_comma_align] [get_bd_pins axi_ad9680_jesd/rxencommaalign_out] + connect_bd_net -net axi_daq2_gt_rx_ip_sync [get_bd_pins axi_daq2_gt/rx_ip_sync] [get_bd_pins axi_ad9680_jesd/rx_sync] + connect_bd_net -net axi_daq2_gt_rx_ip_sof [get_bd_pins axi_daq2_gt/rx_ip_sof] [get_bd_pins axi_ad9680_jesd/rx_start_of_frame] + connect_bd_net -net axi_daq2_gt_rx_ip_data [get_bd_pins axi_daq2_gt/rx_ip_data] [get_bd_pins axi_ad9680_jesd/rx_tdata] + connect_bd_net -net axi_daq2_gt_rx_data [get_bd_pins axi_daq2_gt/rx_data] [get_bd_pins axi_ad9680_core/rx_data] + + connect_bd_net -net axi_daq2_gt_rx_rst [get_bd_pins axi_ad9680_fifo/adc_rst] [get_bd_pins axi_daq2_gt/rx_rst] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_fifo/dma_rstn] $sys_100m_resetn_source + + connect_bd_net -net axi_ad9680_adc_clk [get_bd_pins axi_ad9680_core/adc_clk] [get_bd_pins axi_ad9680_fifo/adc_clk] + connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins axi_ad9680_fifo/adc_wovf] + connect_bd_net -net axi_ad9680_adc_enable_0 [get_bd_pins axi_ad9680_core/adc_enable_0] [get_bd_ports adc_enable_0] + connect_bd_net -net axi_ad9680_adc_valid_0 [get_bd_pins axi_ad9680_core/adc_valid_0] [get_bd_ports adc_valid_0] + connect_bd_net -net axi_ad9680_adc_data_0 [get_bd_pins axi_ad9680_core/adc_data_0] [get_bd_ports adc_data_0] + connect_bd_net -net axi_ad9680_adc_enable_1 [get_bd_pins axi_ad9680_core/adc_enable_1] [get_bd_ports adc_enable_1] + connect_bd_net -net axi_ad9680_adc_valid_1 [get_bd_pins axi_ad9680_core/adc_valid_1] [get_bd_ports adc_valid_1] + connect_bd_net -net axi_ad9680_adc_data_1 [get_bd_pins axi_ad9680_core/adc_data_1] [get_bd_ports adc_data_1] + connect_bd_net -net axi_ad9680_adc_dwr [get_bd_ports adc_dwr] [get_bd_pins axi_ad9680_fifo/adc_wr] + connect_bd_net -net axi_ad9680_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins axi_ad9680_fifo/adc_wdata] + + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_fifo/dma_clk] [get_bd_pins axi_ad9680_dma/s_axis_aclk] + connect_bd_net -net axi_ad9680_dma_dvalid [get_bd_pins axi_ad9680_fifo/dma_wvalid] [get_bd_pins axi_ad9680_dma/s_axis_valid] + connect_bd_net -net axi_ad9680_dma_dready [get_bd_pins axi_ad9680_fifo/dma_wready] [get_bd_pins axi_ad9680_dma/s_axis_ready] + connect_bd_net -net axi_ad9680_dma_ddata [get_bd_pins axi_ad9680_fifo/dma_wdata] [get_bd_pins axi_ad9680_dma/s_axis_data] + connect_bd_net -net axi_ad9680_dma_intr [get_bd_pins axi_ad9680_dma/irq] [get_bd_ports axi_ad9680_dma_intr] + + # dac/adc clocks + + connect_bd_net -net axi_ad9144_dac_clk [get_bd_ports dac_clk] + connect_bd_net -net axi_ad9680_adc_clk [get_bd_ports adc_clk] + +if {$sys_zynq == 0} { + + connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9680_fifo/axi_clk] $sys_200m_clk_source +} + + # interconnect (cpu) + + connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9144_dma/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9144_core/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9144_jesd/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9680_dma/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_ad9680_core/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_ad9680_jesd/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_daq2_gt/s_axi] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_core/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_jesd/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_dma/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_core/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_jesd/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma/s_axi_aclk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_core/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_jesd/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_dma/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_core/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_jesd/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma/s_axi_aresetn] + +if {$sys_zynq == 0} { + + connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_daq2_spi/axi_lite] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m15_axi [get_bd_intf_pins axi_cpu_interconnect/M15_AXI] [get_bd_intf_pins axi_daq2_gpio/s_axi] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M15_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_spi/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_spi/ext_spi_clk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gpio/s_axi_aclk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M15_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_spi/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gpio/s_axi_aresetn] + + connect_bd_net -net axi_daq2_spi_intr [get_bd_pins axi_daq2_spi/ip2intc_irpt] [get_bd_ports axi_daq2_spi_intr] + connect_bd_net -net axi_daq2_gpio_intr [get_bd_pins axi_daq2_gpio/ip2intc_irpt] [get_bd_ports axi_daq2_gpio_intr] +} + + # gt uses hp3, and 100MHz clock for both DRP and AXI4 + +if {$sys_zynq == 0} { + + connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_daq2_gt/m_axi] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/m_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/drp_clk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt/m_axi_aresetn] + +} else { + + connect_bd_intf_net -intf_net axi_daq2_gt_interconnect_m00_axi [get_bd_intf_pins axi_daq2_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3] + connect_bd_intf_net -intf_net axi_daq2_gt_interconnect_s00_axi [get_bd_intf_pins axi_daq2_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_daq2_gt/m_axi] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt_interconnect/ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt_interconnect/M00_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt_interconnect/S00_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP3_ACLK] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/m_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/drp_clk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt_interconnect/ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt/m_axi_aresetn] +} + + # memory interconnects share the same clock (fclk2) + + # interconnect (mem/dac) + +if {$sys_zynq == 0} { + + connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9144_dma/m_src_axi] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_dma/m_src_axi_aclk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_dma/m_src_axi_aresetn] + + connect_bd_intf_net -intf_net axi_mem_interconnect_s10_axi [get_bd_intf_pins axi_mem_interconnect/S10_AXI] [get_bd_intf_pins axi_ad9680_dma/m_dest_axi] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S10_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S10_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn] + +} else { + + connect_bd_intf_net -intf_net axi_ad9144_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9144_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1] + connect_bd_intf_net -intf_net axi_ad9144_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9144_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9144_dma/m_src_axi] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_dma_interconnect/ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_dma_interconnect/M00_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_dma_interconnect/S00_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_dma/m_src_axi_aclk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_dma_interconnect/ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_dma_interconnect/M00_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_dma_interconnect/S00_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_dma/m_src_axi_aresetn] + + connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2] + connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9680_dma/m_dest_axi] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma_interconnect/ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma_interconnect/M00_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma_interconnect/S00_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma_interconnect/ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma_interconnect/M00_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma_interconnect/S00_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn] +} + + # ila + + set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_rx_mon] + set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_NUM_OF_PROBES {3}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_PROBE0_WIDTH {334}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_PROBE2_WIDTH {128}] $ila_jesd_rx_mon + + connect_bd_net -net axi_daq2_gt_rx_mon_data [get_bd_pins axi_daq2_gt/rx_mon_data] + connect_bd_net -net axi_daq2_gt_rx_mon_trigger [get_bd_pins axi_daq2_gt/rx_mon_trigger] + connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK] + connect_bd_net -net axi_daq2_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0] + connect_bd_net -net axi_daq2_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1] + connect_bd_net -net axi_daq2_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2] + + set ila_jesd_tx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_tx_mon] + set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_tx_mon + set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_jesd_tx_mon + set_property -dict [list CONFIG.C_PROBE0_WIDTH {150}] $ila_jesd_tx_mon + set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_tx_mon + + connect_bd_net -net axi_daq2_gt_tx_mon_data [get_bd_pins axi_daq2_gt/tx_mon_data] + connect_bd_net -net axi_daq2_gt_tx_mon_trigger [get_bd_pins axi_daq2_gt/tx_mon_trigger] + connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins ila_jesd_tx_mon/CLK] + connect_bd_net -net axi_daq2_gt_tx_mon_data [get_bd_pins ila_jesd_tx_mon/PROBE0] + connect_bd_net -net axi_daq2_gt_tx_mon_trigger [get_bd_pins ila_jesd_tx_mon/PROBE1] + + # address map + + create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_core/s_axi/axi_lite] SEG_data_ad9144_core + create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_core/s_axi/axi_lite] SEG_data_ad9680_core + create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_gt/s_axi/axi_lite] SEG_data_daq2_gt + create_bd_addr_seg -range 0x00001000 -offset 0x44A90000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_jesd/s_axi/Reg] SEG_data_ad9144_jesd + create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_jesd/s_axi/Reg] SEG_data_ad9680_jesd + create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_dma/s_axi/axi_lite] SEG_data_ad9680_dma + create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_dma/s_axi/axi_lite] SEG_data_ad9144_dma + +if {$sys_zynq == 0} { + + create_bd_addr_seg -range 0x00010000 -offset 0x40000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_gpio/S_AXI/Reg] SEG_data_daq2_gpio + create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_spi/axi_lite/Reg] SEG_data_daq2_spi +} + +if {$sys_zynq == 0} { + + create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9144_dma/m_src_axi] $sys_addr_mem_seg SEG_axi_ddr_cntrl + create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] $sys_addr_mem_seg SEG_axi_ddr_cntrl + create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_daq2_gt/m_axi] $sys_addr_mem_seg SEG_axi_ddr_cntrl + + create_bd_addr_seg -range 0x00100000 -offset 0xc0000000 [get_bd_addr_spaces axi_ad9680_fifo/axi_fifo2s/axi] [get_bd_addr_segs axi_ad9680_fifo/axi_bram_ctl/S_AXI/Mem0] SEG_axi_bram_ctl_mem + +} else { + + create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9144_dma/m_src_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm + create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm + create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_daq2_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm + + create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ad9680_fifo/axi_fifo2s/axi] [get_bd_addr_segs axi_ad9680_fifo/axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl_memaddr +} + diff --git a/projects/daq2/kc705/system_bd.tcl b/projects/daq2/kc705/system_bd.tcl index 2e2b96ae9..ad00363e9 100644 --- a/projects/daq2/kc705/system_bd.tcl +++ b/projects/daq2/kc705/system_bd.tcl @@ -1,4 +1,5 @@ source $ad_hdl_dir/projects/common/kc705/kc705_system_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl source ../common/daq2_bd.tcl diff --git a/projects/daq2/kc705/system_constr.xdc b/projects/daq2/kc705/system_constr.xdc index 5a810e137..56ffb0499 100644 --- a/projects/daq2/kc705/system_constr.xdc +++ b/projects/daq2/kc705/system_constr.xdc @@ -3,14 +3,14 @@ set_property -dict {PACKAGE_PIN E8} [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P set_property -dict {PACKAGE_PIN E7} [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N -set_property -dict {PACKAGE_PIN E4} [get_ports rx_data_p[0]] ; ## C06 FMC_HPC_DP0_M2C_P -set_property -dict {PACKAGE_PIN E3} [get_ports rx_data_n[0]] ; ## C07 FMC_HPC_DP0_M2C_N -set_property -dict {PACKAGE_PIN D6} [get_ports rx_data_p[1]] ; ## A02 FMC_HPC_DP1_M2C_P -set_property -dict {PACKAGE_PIN D5} [get_ports rx_data_n[1]] ; ## A03 FMC_HPC_DP1_M2C_N +set_property -dict {PACKAGE_PIN A8} [get_ports rx_data_p[0]] ; ## A10 FMC_HPC_DP3_M2C_P +set_property -dict {PACKAGE_PIN A7} [get_ports rx_data_n[0]] ; ## A11 FMC_HPC_DP3_M2C_N +set_property -dict {PACKAGE_PIN E4} [get_ports rx_data_p[1]] ; ## C06 FMC_HPC_DP0_M2C_P +set_property -dict {PACKAGE_PIN E3} [get_ports rx_data_n[1]] ; ## C07 FMC_HPC_DP0_M2C_N set_property -dict {PACKAGE_PIN B6} [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P set_property -dict {PACKAGE_PIN B5} [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N -set_property -dict {PACKAGE_PIN A8} [get_ports rx_data_p[3]] ; ## A10 FMC_HPC_DP3_M2C_P -set_property -dict {PACKAGE_PIN A7} [get_ports rx_data_n[3]] ; ## A11 FMC_HPC_DP3_M2C_N +set_property -dict {PACKAGE_PIN D6} [get_ports rx_data_p[3]] ; ## A02 FMC_HPC_DP1_M2C_P +set_property -dict {PACKAGE_PIN D5} [get_ports rx_data_n[3]] ; ## A03 FMC_HPC_DP1_M2C_N set_property -dict {PACKAGE_PIN D26 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P set_property -dict {PACKAGE_PIN C26 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N set_property -dict {PACKAGE_PIN H26 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G09 FMC_HPC_LA03_P @@ -18,14 +18,14 @@ set_property -dict {PACKAGE_PIN H27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_po set_property -dict {PACKAGE_PIN C8} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P set_property -dict {PACKAGE_PIN C7} [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N -set_property -dict {PACKAGE_PIN D2} [get_ports tx_data_p[0]] ; ## C02 FMC_HPC_DP0_C2M_P -set_property -dict {PACKAGE_PIN D1} [get_ports tx_data_n[0]] ; ## C03 FMC_HPC_DP0_C2M_N -set_property -dict {PACKAGE_PIN C4} [get_ports tx_data_p[1]] ; ## A22 FMC_HPC_DP1_C2M_P -set_property -dict {PACKAGE_PIN C3} [get_ports tx_data_n[1]] ; ## A23 FMC_HPC_DP1_C2M_N -set_property -dict {PACKAGE_PIN B2} [get_ports tx_data_p[2]] ; ## A26 FMC_HPC_DP2_C2M_P -set_property -dict {PACKAGE_PIN B1} [get_ports tx_data_n[2]] ; ## A27 FMC_HPC_DP2_C2M_N -set_property -dict {PACKAGE_PIN A4} [get_ports tx_data_p[3]] ; ## A30 FMC_HPC_DP3_C2M_P -set_property -dict {PACKAGE_PIN A3} [get_ports tx_data_n[3]] ; ## A31 FMC_HPC_DP3_C2M_N +set_property -dict {PACKAGE_PIN A4} [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[0]) +set_property -dict {PACKAGE_PIN A3} [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[0]) +set_property -dict {PACKAGE_PIN D2} [get_ports tx_data_p[1]] ; ## C02 FMC_HPC_DP0_C2M_P (tx_data_p[3]) +set_property -dict {PACKAGE_PIN D1} [get_ports tx_data_n[1]] ; ## C03 FMC_HPC_DP0_C2M_N (tx_data_n[3]) +set_property -dict {PACKAGE_PIN B2} [get_ports tx_data_p[2]] ; ## A26 FMC_HPC_DP2_C2M_P (tx_data_p[1]) +set_property -dict {PACKAGE_PIN B1} [get_ports tx_data_n[2]] ; ## A27 FMC_HPC_DP2_C2M_N (tx_data_n[1]) +set_property -dict {PACKAGE_PIN C4} [get_ports tx_data_p[3]] ; ## A22 FMC_HPC_DP1_C2M_P (tx_data_p[2]) +set_property -dict {PACKAGE_PIN C3} [get_ports tx_data_n[3]] ; ## A23 FMC_HPC_DP1_C2M_N (tx_data_n[2]) set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P set_property -dict {PACKAGE_PIN H25 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N set_property -dict {PACKAGE_PIN G28 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_p] ; ## H10 FMC_HPC_LA04_P @@ -36,20 +36,22 @@ set_property -dict {PACKAGE_PIN D29 IOSTANDARD LVCMOS25} [get_ports spi_csn_da set_property -dict {PACKAGE_PIN A30 IOSTANDARD LVCMOS25} [get_ports spi_csn_adc] ; ## D15 FMC_HPC_LA09_N set_property -dict {PACKAGE_PIN F30 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D12 FMC_HPC_LA05_N set_property -dict {PACKAGE_PIN B30 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## D14 FMC_HPC_LA09_P +set_property -dict {PACKAGE_PIN E30 IOSTANDARD LVCMOS25} [get_ports spi_dir] ; ## G13 FMC_HPC_LA08_N -set_property -dict {PACKAGE_PIN G30 IOSTANDARD LVCMOS25} [get_ports clkd_reset] ; ## C11 FMC_HPC_LA06_N set_property -dict {PACKAGE_PIN E29 IOSTANDARD LVCMOS25} [get_ports clkd_sync] ; ## G12 FMC_HPC_LA08_P -set_property -dict {PACKAGE_PIN E30 IOSTANDARD LVCMOS25} [get_ports clkd_pd] ; ## G13 FMC_HPC_LA08_N set_property -dict {PACKAGE_PIN C30 IOSTANDARD LVCMOS25} [get_ports dac_reset] ; ## C15 FMC_HPC_LA10_N set_property -dict {PACKAGE_PIN B29 IOSTANDARD LVCMOS25} [get_ports dac_txen] ; ## G16 FMC_HPC_LA12_N set_property -dict {PACKAGE_PIN H30 IOSTANDARD LVCMOS25} [get_ports adc_pd] ; ## C10 FMC_HPC_LA06_P -set_property -dict {PACKAGE_PIN C25 IOSTANDARD LVCMOS25} [get_ports clkd_status[0]] ; ## G06 FMC_HPC_LA00_CC_P -set_property -dict {PACKAGE_PIN B25 IOSTANDARD LVCMOS25} [get_ports clkd_status[1]] ; ## G07 FMC_HPC_LA00_CC_N +set_property -dict {PACKAGE_PIN A25 IOSTANDARD LVCMOS25} [get_ports clkd_status[0]] ; ## D17 FMC_HPC_LA13_P +set_property -dict {PACKAGE_PIN A26 IOSTANDARD LVCMOS25} [get_ports clkd_status[1]] ; ## D18 FMC_HPC_LA13_N set_property -dict {PACKAGE_PIN C29 IOSTANDARD LVCMOS25} [get_ports dac_irq] ; ## G15 FMC_HPC_LA12_P set_property -dict {PACKAGE_PIN G27 IOSTANDARD LVCMOS25} [get_ports adc_fda] ; ## H16 FMC_HPC_LA11_P set_property -dict {PACKAGE_PIN F27 IOSTANDARD LVCMOS25} [get_ports adc_fdb] ; ## H17 FMC_HPC_LA11_N +set_property -dict {PACKAGE_PIN E28 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports trig_p] ; ## H13 FMC_HPC_LA07_P +set_property -dict {PACKAGE_PIN D28 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports trig_n] ; ## H14 FMC_HPC_LA07_N + # clocks create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p] @@ -57,12 +59,4 @@ create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] create_clock -name tx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_tx_clk] create_clock -name rx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_rx_clk] -set_clock_groups -asynchronous -group {tx_div_clk} -set_clock_groups -asynchronous -group {rx_div_clk} -set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE] diff --git a/projects/daq2/kc705/system_project.tcl b/projects/daq2/kc705/system_project.tcl index f296237f7..0a7a2d624 100644 --- a/projects/daq2/kc705/system_project.tcl +++ b/projects/daq2/kc705/system_project.tcl @@ -9,8 +9,12 @@ adi_project_files daq2_kc705 [list \ "../common/daq2_spi.v" \ "system_top.v" \ "system_constr.xdc"\ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc" ] +set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc] +set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] + adi_project_run daq2_kc705 diff --git a/projects/daq2/kc705/system_top.v b/projects/daq2/kc705/system_top.v index 18ade969c..7fbf014a8 100644 --- a/projects/daq2/kc705/system_top.v +++ b/projects/daq2/kc705/system_top.v @@ -115,6 +115,9 @@ module system_top ( tx_data_p, tx_data_n, + trig_p, + trig_n, + adc_fdb, adc_fda, dac_irq, @@ -123,15 +126,14 @@ module system_top ( adc_pd, dac_txen, dac_reset, - clkd_pd, clkd_sync, - clkd_reset, spi_csn_clk, spi_csn_dac, spi_csn_adc, spi_clk, - spi_sdio); + spi_sdio, + spi_dir); input sys_rst; input sys_clk_p; @@ -207,6 +209,9 @@ module system_top ( output [ 3:0] tx_data_p; output [ 3:0] tx_data_n; + input trig_p; + input trig_n; + inout adc_fdb; inout adc_fda; inout dac_irq; @@ -215,18 +220,29 @@ module system_top ( inout adc_pd; inout dac_txen; inout dac_reset; - inout clkd_pd; inout clkd_sync; - inout clkd_reset; output spi_csn_clk; output spi_csn_dac; output spi_csn_adc; output spi_clk; inout spi_sdio; + output spi_dir; + // internal registers + + reg dac_drd = 'd0; + reg [63:0] dac_ddata_0 = 'd0; + reg [63:0] dac_ddata_1 = 'd0; + reg [63:0] dac_ddata_2 = 'd0; + reg [63:0] dac_ddata_3 = 'd0; + reg adc_dsync = 'd0; + reg adc_dwr = 'd0; + reg [127:0] adc_ddata = 'd0; + // internal signals + wire trig; wire rx_ref_clk; wire rx_sysref; wire rx_sync; @@ -236,6 +252,23 @@ module system_top ( wire [ 2:0] spi_csn; wire spi_mosi; wire spi_miso; + wire dac_clk; + wire [127:0] dac_ddata; + wire dac_enable_0; + wire dac_enable_1; + wire dac_enable_2; + wire dac_enable_3; + wire dac_valid_0; + wire dac_valid_1; + wire dac_valid_2; + wire dac_valid_3; + wire adc_clk; + wire [63:0] adc_data_0; + wire [63:0] adc_data_1; + wire adc_enable_0; + wire adc_enable_1; + wire adc_valid_0; + wire adc_valid_1; wire [ 5:0] gpio_ctl_i; wire [ 5:0] gpio_ctl_o; wire [ 5:0] gpio_ctl_t; @@ -243,12 +276,123 @@ module system_top ( wire [ 4:0] gpio_status_o; wire [ 4:0] gpio_status_t; - // assignments + // adc-dac data + + always @(posedge dac_clk) begin + case ({dac_enable_1, dac_enable_0}) + 2'b11: begin + dac_drd <= dac_valid_0 & dac_valid_1; + dac_ddata_0[63:48] <= dac_ddata[111: 96]; + dac_ddata_0[47:32] <= dac_ddata[ 79: 64]; + dac_ddata_0[31:16] <= dac_ddata[ 47: 32]; + dac_ddata_0[15: 0] <= dac_ddata[ 15: 0]; + dac_ddata_1[63:48] <= dac_ddata[127:112]; + dac_ddata_1[47:32] <= dac_ddata[ 95: 80]; + dac_ddata_1[31:16] <= dac_ddata[ 63: 48]; + dac_ddata_1[15: 0] <= dac_ddata[ 31: 16]; + dac_ddata_2 <= 64'd0; + dac_ddata_3 <= 64'd0; + end + 2'b10: begin + dac_drd <= dac_valid_1 & ~dac_drd; + dac_ddata_0 <= 64'd0; + if (dac_drd == 1'b1) begin + dac_ddata_1[63:48] <= dac_ddata[127:112]; + dac_ddata_1[47:32] <= dac_ddata[111: 96]; + dac_ddata_1[31:16] <= dac_ddata[ 95: 80]; + dac_ddata_1[15: 0] <= dac_ddata[ 79: 64]; + end else begin + dac_ddata_1[63:48] <= dac_ddata[ 63: 48]; + dac_ddata_1[47:32] <= dac_ddata[ 47: 32]; + dac_ddata_1[31:16] <= dac_ddata[ 31: 16]; + dac_ddata_1[15: 0] <= dac_ddata[ 15: 0]; + end + dac_ddata_2 <= 64'd0; + dac_ddata_3 <= 64'd0; + end + 2'b01: begin + dac_drd <= dac_valid_0 & ~dac_drd; + if (dac_drd == 1'b1) begin + dac_ddata_0[63:48] <= dac_ddata[127:112]; + dac_ddata_0[47:32] <= dac_ddata[111: 96]; + dac_ddata_0[31:16] <= dac_ddata[ 95: 80]; + dac_ddata_0[15: 0] <= dac_ddata[ 79: 64]; + end else begin + dac_ddata_0[63:48] <= dac_ddata[ 63: 48]; + dac_ddata_0[47:32] <= dac_ddata[ 47: 32]; + dac_ddata_0[31:16] <= dac_ddata[ 31: 16]; + dac_ddata_0[15: 0] <= dac_ddata[ 15: 0]; + end + dac_ddata_1 <= 64'd0; + dac_ddata_2 <= 64'd0; + dac_ddata_3 <= 64'd0; + end + default: begin + dac_drd <= 1'b0; + dac_ddata_0 <= 64'd0; + dac_ddata_1 <= 64'd0; + dac_ddata_2 <= 64'd0; + dac_ddata_3 <= 64'd0; + end + endcase + end + + always @(posedge adc_clk) begin + case ({adc_enable_1, adc_enable_0}) + 2'b11: begin + adc_dsync <= 1'b1; + adc_dwr <= adc_valid_1 & adc_valid_0; + adc_ddata[127:112] <= adc_data_1[63:48]; + adc_ddata[111: 96] <= adc_data_0[63:48]; + adc_ddata[ 95: 80] <= adc_data_1[47:32]; + adc_ddata[ 79: 64] <= adc_data_0[47:32]; + adc_ddata[ 63: 48] <= adc_data_1[31:16]; + adc_ddata[ 47: 32] <= adc_data_0[31:16]; + adc_ddata[ 31: 16] <= adc_data_1[15: 0]; + adc_ddata[ 15: 0] <= adc_data_0[15: 0]; + end + 2'b10: begin + adc_dsync <= 1'b1; + adc_dwr <= adc_valid_1 & ~adc_dwr; + adc_ddata[127:112] <= adc_data_1[63:48]; + adc_ddata[111: 96] <= adc_data_1[47:32]; + adc_ddata[ 95: 80] <= adc_data_1[31:16]; + adc_ddata[ 79: 64] <= adc_data_1[15: 0]; + adc_ddata[ 63: 48] <= adc_ddata[127:112]; + adc_ddata[ 47: 32] <= adc_ddata[111: 96]; + adc_ddata[ 31: 16] <= adc_ddata[ 95: 80]; + adc_ddata[ 15: 0] <= adc_ddata[ 79: 64]; + end + 2'b01: begin + adc_dsync <= 1'b1; + adc_dwr <= adc_valid_0 & ~adc_dwr; + adc_ddata[127:112] <= adc_data_0[63:48]; + adc_ddata[111: 96] <= adc_data_0[47:32]; + adc_ddata[ 95: 80] <= adc_data_0[31:16]; + adc_ddata[ 79: 64] <= adc_data_0[15: 0]; + adc_ddata[ 63: 48] <= adc_ddata[127:112]; + adc_ddata[ 47: 32] <= adc_ddata[111: 96]; + adc_ddata[ 31: 16] <= adc_ddata[ 95: 80]; + adc_ddata[ 15: 0] <= adc_ddata[ 79: 64]; + end + default: begin + adc_dsync <= 1'b0; + adc_dwr <= 1'b0; + adc_ddata <= 128'd0; + end + endcase + end + + // spi assign spi_csn_adc = spi_csn[2]; assign spi_csn_dac = spi_csn[1]; assign spi_csn_clk = spi_csn[0]; + // default logic + + assign fan_pwm = 1'b1; + // instantiations IBUFDS_GTE2 i_ibufds_rx_ref_clk ( @@ -290,75 +434,40 @@ module system_top ( .spi_clk (spi_clk), .spi_mosi (spi_mosi), .spi_miso (spi_miso), - .spi_sdio (spi_sdio)); + .spi_sdio (spi_sdio), + .spi_dir (spi_dir)); - IOBUF i_iobuf_gpio_adc_pd ( - .I (gpio_ctl_o[5]), - .O (gpio_ctl_i[5]), - .T (gpio_ctl_t[5]), - .IO (adc_pd)); + IBUFDS i_ibufds_trig ( + .I (trig_p), + .IB (trig_n), + .O (trig)); - IOBUF i_iobuf_gpio_dac_txen ( - .I (gpio_ctl_o[4]), - .O (gpio_ctl_i[4]), - .T (gpio_ctl_t[4]), - .IO (dac_txen)); + assign gpio_ctl_i[0] = trig; - IOBUF i_iobuf_gpio_dac_reset ( - .I (gpio_ctl_o[3]), - .O (gpio_ctl_i[3]), - .T (gpio_ctl_t[3]), - .IO (dac_reset)); - - IOBUF i_iobuf_gpio_clkd_pd ( - .I (gpio_ctl_o[2]), - .O (gpio_ctl_i[2]), - .T (gpio_ctl_t[2]), - .IO (clkd_pd)); - - IOBUF i_iobuf_gpio_clkd_sync ( - .I (gpio_ctl_o[1]), - .O (gpio_ctl_i[1]), - .T (gpio_ctl_t[1]), - .IO (clkd_sync)); - - IOBUF i_iobuf_gpio_clkd_reset ( - .I (gpio_ctl_o[0]), - .O (gpio_ctl_i[0]), - .T (gpio_ctl_t[0]), - .IO (clkd_reset)); - - IOBUF i_iobuf_gpio_adc_fdb ( - .I (gpio_status_o[4]), - .O (gpio_status_i[4]), - .T (gpio_status_t[4]), - .IO (adc_fdb)); - - IOBUF i_iobuf_gpio_adc_fda ( - .I (gpio_status_o[3]), - .O (gpio_status_i[3]), - .T (gpio_status_t[3]), - .IO (adc_fda)); - - IOBUF i_iobuf_gpio_dac_irq ( - .I (gpio_status_o[2]), - .O (gpio_status_i[2]), - .T (gpio_status_t[2]), - .IO (dac_irq)); - - IOBUF i_iobuf_gpio_clkd_status_1 ( - .I (gpio_status_o[1]), - .O (gpio_status_i[1]), - .T (gpio_status_t[1]), - .IO (clkd_status[1])); - - IOBUF i_iobuf_gpio_clkd_status_0 ( - .I (gpio_status_o[0]), - .O (gpio_status_i[0]), - .T (gpio_status_t[0]), - .IO (clkd_status[0])); + ad_iobuf #(.DATA_WIDTH(9)) i_iobuf ( + .dt ({gpio_ctl_t[5:3], gpio_ctl_t[1], gpio_status_t[4:0]}), + .di ({gpio_ctl_o[5:3], gpio_ctl_o[1], gpio_status_o[4:0]}), + .do ({gpio_ctl_i[5:3], gpio_ctl_i[1], gpio_status_i[4:0]}), + .dio ({ adc_pd, // 10 + dac_txen, // 9 + dac_reset, // 8 + clkd_sync, // 6 + adc_fdb, // 4 + adc_fda, // 3 + dac_irq, // 2 + clkd_status})); // 0 system_wrapper i_system_wrapper ( + .adc_clk (adc_clk), + .adc_data_0 (adc_data_0), + .adc_data_1 (adc_data_1), + .adc_ddata (adc_ddata), + .adc_dsync (adc_dsync), + .adc_dwr (adc_dwr), + .adc_enable_0 (adc_enable_0), + .adc_enable_1 (adc_enable_1), + .adc_valid_0 (adc_valid_0), + .adc_valid_1 (adc_valid_1), .ddr3_1_n (ddr3_1_n), .ddr3_1_p (ddr3_1_p), .ddr3_addr (ddr3_addr), @@ -376,7 +485,21 @@ module system_top ( .ddr3_ras_n (ddr3_ras_n), .ddr3_reset_n (ddr3_reset_n), .ddr3_we_n (ddr3_we_n), - .fan_pwm (fan_pwm), + .dac_clk (dac_clk), + .dac_ddata (dac_ddata), + .dac_ddata_0 (dac_ddata_0), + .dac_ddata_1 (dac_ddata_1), + .dac_ddata_2 (dac_ddata_2), + .dac_ddata_3 (dac_ddata_3), + .dac_drd (dac_drd), + .dac_enable_0 (dac_enable_0), + .dac_enable_1 (dac_enable_1), + .dac_enable_2 (dac_enable_2), + .dac_enable_3 (dac_enable_3), + .dac_valid_0 (dac_valid_0), + .dac_valid_1 (dac_valid_1), + .dac_valid_2 (dac_valid_2), + .dac_valid_3 (dac_valid_3), .gpio_ctl_i (gpio_ctl_i), .gpio_ctl_o (gpio_ctl_o), .gpio_ctl_t (gpio_ctl_t), diff --git a/projects/daq2/kcu105/system_bd.tcl b/projects/daq2/kcu105/system_bd.tcl index d7a8388de..f30f9e5f6 100644 --- a/projects/daq2/kcu105/system_bd.tcl +++ b/projects/daq2/kcu105/system_bd.tcl @@ -1,536 +1,10 @@ source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl +source ../common/daq2_bd.tcl - # daq2 - - set spi_csn_i [create_bd_port -dir I -from 2 -to 0 spi_csn_i] - set spi_csn_o [create_bd_port -dir O -from 2 -to 0 spi_csn_o] - set spi_clk_i [create_bd_port -dir I spi_clk_i] - set spi_clk_o [create_bd_port -dir O spi_clk_o] - set spi_sdo_i [create_bd_port -dir I spi_sdo_i] - set spi_sdo_o [create_bd_port -dir O spi_sdo_o] - set spi_sdi_i [create_bd_port -dir I spi_sdi_i] - - set rx_ref_clk [create_bd_port -dir I rx_ref_clk] - set rx_sync [create_bd_port -dir O rx_sync] - set rx_sysref [create_bd_port -dir I rx_sysref] - set rx_data_p [create_bd_port -dir I -from 3 -to 0 rx_data_p] - set rx_data_n [create_bd_port -dir I -from 3 -to 0 rx_data_n] - - set tx_ref_clk [create_bd_port -dir I tx_ref_clk] - set tx_sync [create_bd_port -dir I tx_sync] - set tx_sysref [create_bd_port -dir I tx_sysref] - set tx_data_p [create_bd_port -dir O -from 3 -to 0 tx_data_p] - set tx_data_n [create_bd_port -dir O -from 3 -to 0 tx_data_n] - -if {$sys_zynq == 0} { - - set gpio_ctl_i [create_bd_port -dir I -from 5 -to 0 gpio_ctl_i] - set gpio_ctl_o [create_bd_port -dir O -from 5 -to 0 gpio_ctl_o] - set gpio_ctl_t [create_bd_port -dir O -from 5 -to 0 gpio_ctl_t] - set gpio_status_i [create_bd_port -dir I -from 4 -to 0 gpio_status_i] - set gpio_status_o [create_bd_port -dir O -from 4 -to 0 gpio_status_o] - set gpio_status_t [create_bd_port -dir O -from 4 -to 0 gpio_status_t] -} - - set dac_clk [create_bd_port -dir O dac_clk] - set dac_valid_0 [create_bd_port -dir O dac_valid_0] - set dac_enable_0 [create_bd_port -dir O dac_enable_0] - set dac_ddata_0 [create_bd_port -dir I -from 63 -to 0 dac_ddata_0] - set dac_valid_1 [create_bd_port -dir O dac_valid_1] - set dac_enable_1 [create_bd_port -dir O dac_enable_1] - set dac_ddata_1 [create_bd_port -dir I -from 63 -to 0 dac_ddata_1] - set dac_valid_2 [create_bd_port -dir O dac_valid_2] - set dac_enable_2 [create_bd_port -dir O dac_enable_2] - set dac_ddata_2 [create_bd_port -dir I -from 63 -to 0 dac_ddata_2] - set dac_valid_3 [create_bd_port -dir O dac_valid_3] - set dac_enable_3 [create_bd_port -dir O dac_enable_3] - set dac_ddata_3 [create_bd_port -dir I -from 63 -to 0 dac_ddata_3] - set dac_drd [create_bd_port -dir I dac_drd] - set dac_ddata [create_bd_port -dir O -from 127 -to 0 dac_ddata] - - set adc_clk [create_bd_port -dir O adc_clk] - set adc_enable_0 [create_bd_port -dir O adc_enable_0] - set adc_valid_0 [create_bd_port -dir O adc_valid_0] - set adc_data_0 [create_bd_port -dir O -from 63 -to 0 adc_data_0] - set adc_enable_1 [create_bd_port -dir O adc_enable_1] - set adc_valid_1 [create_bd_port -dir O adc_valid_1] - set adc_data_1 [create_bd_port -dir O -from 63 -to 0 adc_data_1] - set adc_dwr [create_bd_port -dir I adc_dwr] - set adc_dsync [create_bd_port -dir I adc_dsync] - set adc_ddata [create_bd_port -dir I -from 127 -to 0 adc_ddata] - - # dac peripherals - - set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core] - set_property -dict [list CONFIG.PCORE_QUAD_DUAL_N {0}] $axi_ad9144_core - - set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.2 axi_ad9144_jesd] - set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd - set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9144_jesd - - set axi_ad9144_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9144_dma] - set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9144_dma - set_property -dict [list CONFIG.PCORE_ID {1}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9144_dma - -if {$sys_zynq == 1} { - - set axi_ad9144_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9144_dma_interconnect] - set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9144_dma_interconnect -} - - # adc peripherals - - set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core] - - set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.2 axi_ad9680_jesd] - set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd - set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd - - set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma] - set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9680_dma - set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9680_dma - -if {$sys_zynq == 1} { - - set axi_ad9680_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9680_dma_interconnect] - set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9680_dma_interconnect -} - - # dac/adc common gt/gpio - - set axi_daq2_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq2_gt] - set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {4}] $axi_daq2_gt - set_property -dict [list CONFIG.PCORE_DEVICE_TYPE {1}] $axi_daq2_gt - set_property -dict [list CONFIG.PCORE_QPLL_FBDIV {20}] $axi_daq2_gt - set_property -dict [list CONFIG.PCORE_QPLL_REFCLK_DIV {1}] $axi_daq2_gt - - -if {$sys_zynq == 1} { - - set axi_daq2_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_daq2_gt_interconnect] - set_property -dict [list CONFIG.NUM_MI {1}] $axi_daq2_gt_interconnect -} - - # gpio and spi - -if {$sys_zynq == 0} { - - set axi_daq2_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_daq2_spi] - set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_daq2_spi - set_property -dict [list CONFIG.C_NUM_SS_BITS {3}] $axi_daq2_spi - set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_daq2_spi - - set axi_daq2_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_daq2_gpio] - set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_daq2_gpio - set_property -dict [list CONFIG.C_GPIO_WIDTH {5}] $axi_daq2_gpio - set_property -dict [list CONFIG.C_GPIO2_WIDTH {6}] $axi_daq2_gpio - set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_daq2_gpio -} - - # additions to default configuration - -if {$sys_zynq == 0} { - - set_property -dict [list CONFIG.NUM_MI {16}] $axi_cpu_interconnect - -} else { - - set_property -dict [list CONFIG.NUM_MI {14}] $axi_cpu_interconnect -} - -if {$sys_zynq == 0} { - - set_property -dict [list CONFIG.NUM_SI {11}] $axi_mem_interconnect - set_property -dict [list CONFIG.S09_HAS_REGSLICE {3}] $axi_mem_interconnect - set_property -dict [list CONFIG.S10_HAS_REGSLICE {3}] $axi_mem_interconnect - set_property -dict [list CONFIG.NUM_PORTS {7}] $sys_concat_intc -} - -if {$sys_zynq == 1} { - - set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7 - set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7 - set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $sys_ps7 - set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7 - set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7 - set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7 - set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {43}] $sys_ps7 - set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7 - set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7 - - set_property LEFT 42 [get_bd_ports GPIO_I] - set_property LEFT 42 [get_bd_ports GPIO_O] - set_property LEFT 42 [get_bd_ports GPIO_T] -} - - # connections (spi and gpio) - -if {$sys_zynq == 0} { - - connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_daq2_spi/ss_i] - connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_daq2_spi/ss_o] - connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_daq2_spi/sck_i] - connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_daq2_spi/sck_o] - connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_daq2_spi/io0_i] - connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_daq2_spi/io0_o] - connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_daq2_spi/io1_i] - -} else { - set sys_spi_csn_concat [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 sys_spi_csn_concat] - set_property -dict [list CONFIG.NUM_PORTS {3}] $sys_spi_csn_concat - - set sys_const_vcc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 sys_const_vcc] - set_property -dict [list CONFIG.CONST_WIDTH {1} CONFIG.CONST_VAL {1}] $sys_const_vcc - - connect_bd_net -net spi_csn0 [get_bd_pins sys_spi_csn_concat/In2] [get_bd_pins sys_ps7/SPI0_SS_O] - connect_bd_net -net spi_csn1 [get_bd_pins sys_spi_csn_concat/In1] [get_bd_pins sys_ps7/SPI0_SS1_O] - connect_bd_net -net spi_csn2 [get_bd_pins sys_spi_csn_concat/In0] [get_bd_pins sys_ps7/SPI0_SS2_O] - connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins sys_spi_csn_concat/dout] - connect_bd_net -net spi_csn_i [get_bd_pins sys_const_vcc/const] [get_bd_pins sys_ps7/SPI0_SS_I] - connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I] - connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O] - connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I] - connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O] - connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I] -} - -if {$sys_zynq == 0} { - - connect_bd_net -net gpio_status_i [get_bd_ports gpio_status_i] [get_bd_pins axi_daq2_gpio/gpio_io_i] - connect_bd_net -net gpio_status_o [get_bd_ports gpio_status_o] [get_bd_pins axi_daq2_gpio/gpio_io_o] - connect_bd_net -net gpio_status_t [get_bd_ports gpio_status_t] [get_bd_pins axi_daq2_gpio/gpio_io_t] - connect_bd_net -net gpio_ctl_i [get_bd_ports gpio_ctl_i] [get_bd_pins axi_daq2_gpio/gpio2_io_i] - connect_bd_net -net gpio_ctl_o [get_bd_ports gpio_ctl_o] [get_bd_pins axi_daq2_gpio/gpio2_io_o] - connect_bd_net -net gpio_ctl_t [get_bd_ports gpio_ctl_t] [get_bd_pins axi_daq2_gpio/gpio2_io_t] -} - -if {$sys_zynq == 0} { - - delete_bd_objs [get_bd_nets sys_concat_intc_din_2] [get_bd_ports unc_int2] - delete_bd_objs [get_bd_nets sys_concat_intc_din_3] [get_bd_ports unc_int3] -} - - # connections (gt) - - connect_bd_net -net axi_daq2_gt_ref_clk_q [get_bd_pins axi_daq2_gt/ref_clk_q] [get_bd_ports rx_ref_clk] - connect_bd_net -net axi_daq2_gt_ref_clk_c [get_bd_pins axi_daq2_gt/ref_clk_c] [get_bd_ports tx_ref_clk] - connect_bd_net -net axi_daq2_gt_rx_data_p [get_bd_pins axi_daq2_gt/rx_data_p] [get_bd_ports rx_data_p] - connect_bd_net -net axi_daq2_gt_rx_data_n [get_bd_pins axi_daq2_gt/rx_data_n] [get_bd_ports rx_data_n] - connect_bd_net -net axi_daq2_gt_rx_sync [get_bd_pins axi_daq2_gt/rx_sync] [get_bd_ports rx_sync] - connect_bd_net -net axi_daq2_gt_rx_ext_sysref [get_bd_pins axi_daq2_gt/rx_ext_sysref] [get_bd_ports rx_sysref] - connect_bd_net -net axi_daq2_gt_tx_data_p [get_bd_pins axi_daq2_gt/tx_data_p] [get_bd_ports tx_data_p] - connect_bd_net -net axi_daq2_gt_tx_data_n [get_bd_pins axi_daq2_gt/tx_data_n] [get_bd_ports tx_data_n] - connect_bd_net -net axi_daq2_gt_tx_sync [get_bd_pins axi_daq2_gt/tx_sync] [get_bd_ports tx_sync] - connect_bd_net -net axi_daq2_gt_tx_ext_sysref [get_bd_pins axi_daq2_gt/tx_ext_sysref] [get_bd_ports tx_sysref] - - # connections (dac) - - connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_daq2_gt/tx_clk_g] - connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_daq2_gt/tx_clk] - connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_ad9144_core/tx_clk] - connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_ad9144_jesd/tx_core_clk] - - connect_bd_net -net axi_daq2_gt_tx_rst [get_bd_pins axi_daq2_gt/tx_rst] [get_bd_pins axi_ad9144_jesd/tx_reset] - connect_bd_net -net axi_daq2_gt_tx_sysref [get_bd_pins axi_daq2_gt/tx_sysref] [get_bd_pins axi_ad9144_jesd/tx_sysref] - connect_bd_net -net axi_daq2_gt_tx_gt_charisk [get_bd_pins axi_daq2_gt/tx_gt_charisk] [get_bd_pins axi_ad9144_jesd/gt_txcharisk_out] - connect_bd_net -net axi_daq2_gt_tx_gt_data [get_bd_pins axi_daq2_gt/tx_gt_data] [get_bd_pins axi_ad9144_jesd/gt_txdata_out] - connect_bd_net -net axi_daq2_gt_tx_rst_done [get_bd_pins axi_daq2_gt/tx_rst_done] [get_bd_pins axi_ad9144_jesd/tx_reset_done] - connect_bd_net -net axi_daq2_gt_tx_ip_sync [get_bd_pins axi_daq2_gt/tx_ip_sync] [get_bd_pins axi_ad9144_jesd/tx_sync] - connect_bd_net -net axi_daq2_gt_tx_ip_sof [get_bd_pins axi_daq2_gt/tx_ip_sof] [get_bd_pins axi_ad9144_jesd/tx_start_of_frame] - connect_bd_net -net axi_daq2_gt_tx_ip_data [get_bd_pins axi_daq2_gt/tx_ip_data] [get_bd_pins axi_ad9144_jesd/tx_tdata] - connect_bd_net -net axi_daq2_gt_tx_data [get_bd_pins axi_daq2_gt/tx_data] [get_bd_pins axi_ad9144_core/tx_data] - connect_bd_net -net axi_ad9144_dac_clk [get_bd_pins axi_ad9144_core/dac_clk] [get_bd_pins axi_ad9144_dma/fifo_rd_clk] - connect_bd_net -net axi_ad9144_dac_valid_0 [get_bd_pins axi_ad9144_core/dac_valid_0] [get_bd_ports dac_valid_0] - connect_bd_net -net axi_ad9144_dac_enable_0 [get_bd_pins axi_ad9144_core/dac_enable_0] [get_bd_ports dac_enable_0] - connect_bd_net -net axi_ad9144_dac_ddata_0 [get_bd_pins axi_ad9144_core/dac_ddata_0] [get_bd_ports dac_ddata_0] - connect_bd_net -net axi_ad9144_dac_valid_1 [get_bd_pins axi_ad9144_core/dac_valid_1] [get_bd_ports dac_valid_1] - connect_bd_net -net axi_ad9144_dac_enable_1 [get_bd_pins axi_ad9144_core/dac_enable_1] [get_bd_ports dac_enable_1] - connect_bd_net -net axi_ad9144_dac_ddata_1 [get_bd_pins axi_ad9144_core/dac_ddata_1] [get_bd_ports dac_ddata_1] - connect_bd_net -net axi_ad9144_dac_valid_2 [get_bd_pins axi_ad9144_core/dac_valid_2] [get_bd_ports dac_valid_2] - connect_bd_net -net axi_ad9144_dac_enable_2 [get_bd_pins axi_ad9144_core/dac_enable_2] [get_bd_ports dac_enable_2] - connect_bd_net -net axi_ad9144_dac_ddata_2 [get_bd_pins axi_ad9144_core/dac_ddata_2] [get_bd_ports dac_ddata_2] - connect_bd_net -net axi_ad9144_dac_valid_3 [get_bd_pins axi_ad9144_core/dac_valid_3] [get_bd_ports dac_valid_3] - connect_bd_net -net axi_ad9144_dac_enable_3 [get_bd_pins axi_ad9144_core/dac_enable_3] [get_bd_ports dac_enable_3] - connect_bd_net -net axi_ad9144_dac_ddata_3 [get_bd_pins axi_ad9144_core/dac_ddata_3] [get_bd_ports dac_ddata_3] - connect_bd_net -net axi_ad9144_dac_drd [get_bd_ports dac_drd] [get_bd_pins axi_ad9144_dma/fifo_rd_en] - connect_bd_net -net axi_ad9144_dac_ddata [get_bd_ports dac_ddata] [get_bd_pins axi_ad9144_dma/fifo_rd_dout] - connect_bd_net -net axi_ad9144_dac_dunf [get_bd_pins axi_ad9144_core/dac_dunf] [get_bd_pins axi_ad9144_dma/fifo_rd_underflow] - connect_bd_net -net axi_ad9144_dma_irq [get_bd_pins axi_ad9144_dma/irq] [get_bd_pins sys_concat_intc/In3] - - # connections (adc) - - connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_daq2_gt/rx_clk_g] - connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_daq2_gt/rx_clk] - connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_ad9680_core/rx_clk] - connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_ad9680_jesd/rx_core_clk] - - connect_bd_net -net axi_daq2_gt_rx_rst [get_bd_pins axi_daq2_gt/rx_rst] [get_bd_pins axi_ad9680_jesd/rx_reset] - connect_bd_net -net axi_daq2_gt_rx_sysref [get_bd_pins axi_daq2_gt/rx_sysref] [get_bd_pins axi_ad9680_jesd/rx_sysref] - connect_bd_net -net axi_daq2_gt_rx_gt_charisk [get_bd_pins axi_daq2_gt/rx_gt_charisk] [get_bd_pins axi_ad9680_jesd/gt_rxcharisk_in] - connect_bd_net -net axi_daq2_gt_rx_gt_disperr [get_bd_pins axi_daq2_gt/rx_gt_disperr] [get_bd_pins axi_ad9680_jesd/gt_rxdisperr_in] - connect_bd_net -net axi_daq2_gt_rx_gt_notintable [get_bd_pins axi_daq2_gt/rx_gt_notintable] [get_bd_pins axi_ad9680_jesd/gt_rxnotintable_in] - connect_bd_net -net axi_daq2_gt_rx_gt_data [get_bd_pins axi_daq2_gt/rx_gt_data] [get_bd_pins axi_ad9680_jesd/gt_rxdata_in] - connect_bd_net -net axi_daq2_gt_rx_rst_done [get_bd_pins axi_daq2_gt/rx_rst_done] [get_bd_pins axi_ad9680_jesd/rx_reset_done] - connect_bd_net -net axi_daq2_gt_rx_ip_comma_align [get_bd_pins axi_daq2_gt/rx_ip_comma_align] [get_bd_pins axi_ad9680_jesd/rxencommaalign_out] - connect_bd_net -net axi_daq2_gt_rx_ip_sync [get_bd_pins axi_daq2_gt/rx_ip_sync] [get_bd_pins axi_ad9680_jesd/rx_sync] - connect_bd_net -net axi_daq2_gt_rx_ip_sof [get_bd_pins axi_daq2_gt/rx_ip_sof] [get_bd_pins axi_ad9680_jesd/rx_start_of_frame] - connect_bd_net -net axi_daq2_gt_rx_ip_data [get_bd_pins axi_daq2_gt/rx_ip_data] [get_bd_pins axi_ad9680_jesd/rx_tdata] - connect_bd_net -net axi_daq2_gt_rx_data [get_bd_pins axi_daq2_gt/rx_data] [get_bd_pins axi_ad9680_core/rx_data] - connect_bd_net -net axi_ad9680_adc_clk [get_bd_pins axi_ad9680_core/adc_clk] [get_bd_pins axi_ad9680_dma/fifo_wr_clk] - connect_bd_net -net axi_ad9680_adc_enable_0 [get_bd_pins axi_ad9680_core/adc_enable_0] [get_bd_ports adc_enable_0] - connect_bd_net -net axi_ad9680_adc_valid_0 [get_bd_pins axi_ad9680_core/adc_valid_0] [get_bd_ports adc_valid_0] - connect_bd_net -net axi_ad9680_adc_data_0 [get_bd_pins axi_ad9680_core/adc_data_0] [get_bd_ports adc_data_0] - connect_bd_net -net axi_ad9680_adc_enable_1 [get_bd_pins axi_ad9680_core/adc_enable_1] [get_bd_ports adc_enable_1] - connect_bd_net -net axi_ad9680_adc_valid_1 [get_bd_pins axi_ad9680_core/adc_valid_1] [get_bd_ports adc_valid_1] - connect_bd_net -net axi_ad9680_adc_data_1 [get_bd_pins axi_ad9680_core/adc_data_1] [get_bd_ports adc_data_1] - connect_bd_net -net axi_ad9680_adc_dwr [get_bd_ports adc_dwr] [get_bd_pins axi_ad9680_dma/fifo_wr_en] - connect_bd_net -net axi_ad9680_adc_dsync [get_bd_ports adc_dsync] [get_bd_pins axi_ad9680_dma/fifo_wr_sync] - connect_bd_net -net axi_ad9680_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins axi_ad9680_dma/fifo_wr_din] - connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins axi_ad9680_dma/fifo_wr_overflow] - connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In2] - - # dac/adc clocks - - connect_bd_net -net axi_ad9144_dac_clk [get_bd_ports dac_clk] - connect_bd_net -net axi_ad9680_adc_clk [get_bd_ports adc_clk] - - # interconnect (cpu) - - connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9144_dma/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9144_core/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9144_jesd/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9680_dma/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_ad9680_core/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_ad9680_jesd/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_daq2_gt/s_axi] - connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_cpu_clk_source - connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_cpu_clk_source - connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_cpu_clk_source - connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_cpu_clk_source - connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_cpu_clk_source - connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_cpu_clk_source - connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_cpu_clk_source - connect_bd_net -net sys_cpu_clk [get_bd_pins axi_daq2_gt/s_axi_aclk] - connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ad9144_core/s_axi_aclk] - connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ad9144_jesd/s_axi_aclk] - connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ad9144_dma/s_axi_aclk] - connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ad9680_core/s_axi_aclk] - connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ad9680_jesd/s_axi_aclk] - connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ad9680_dma/s_axi_aclk] - connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_resetn_source - connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_resetn_source - connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_resetn_source - connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_resetn_source - connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_resetn_source - connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_resetn_source - connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_resetn_source - connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_daq2_gt/s_axi_aresetn] - connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_ad9144_core/s_axi_aresetn] - connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_ad9144_jesd/s_axi_aresetn] - connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_ad9144_dma/s_axi_aresetn] - connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_ad9680_core/s_axi_aresetn] - connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_ad9680_jesd/s_axi_aresetn] - connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_ad9680_dma/s_axi_aresetn] - -if {$sys_zynq == 0} { - - connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_daq2_spi/axi_lite] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m15_axi [get_bd_intf_pins axi_cpu_interconnect/M15_AXI] [get_bd_intf_pins axi_daq2_gpio/s_axi] - connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_cpu_clk_source - connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M15_ACLK] $sys_cpu_clk_source - connect_bd_net -net sys_cpu_clk [get_bd_pins axi_daq2_spi/s_axi_aclk] - connect_bd_net -net sys_cpu_clk [get_bd_pins axi_daq2_spi/ext_spi_clk] - connect_bd_net -net sys_cpu_clk [get_bd_pins axi_daq2_gpio/s_axi_aclk] - connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_resetn_source - connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M15_ARESETN] $sys_resetn_source - connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_daq2_spi/s_axi_aresetn] - connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_daq2_gpio/s_axi_aresetn] - - connect_bd_net -net axi_daq2_spi_irq [get_bd_pins axi_daq2_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5] - connect_bd_net -net axi_daq2_gpio_irq [get_bd_pins axi_daq2_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In6] -} - - # gt uses hp3, and 100MHz clock for both DRP and AXI4 - -if {$sys_zynq == 0} { - - connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_daq2_gt/m_axi] - connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_cpu_clk_source - connect_bd_net -net sys_cpu_clk [get_bd_pins axi_daq2_gt/m_axi_aclk] - connect_bd_net -net sys_cpu_clk [get_bd_pins axi_daq2_gt/drp_clk] - connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_resetn_source - connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_daq2_gt/m_axi_aresetn] - -} else { - - connect_bd_intf_net -intf_net axi_daq2_gt_interconnect_m00_axi [get_bd_intf_pins axi_daq2_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3] - connect_bd_intf_net -intf_net axi_daq2_gt_interconnect_s00_axi [get_bd_intf_pins axi_daq2_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_daq2_gt/m_axi] - connect_bd_net -net sys_cpu_clk [get_bd_pins axi_daq2_gt_interconnect/ACLK] $sys_cpu_clk_source - connect_bd_net -net sys_cpu_clk [get_bd_pins axi_daq2_gt_interconnect/M00_ACLK] $sys_cpu_clk_source - connect_bd_net -net sys_cpu_clk [get_bd_pins axi_daq2_gt_interconnect/S00_ACLK] $sys_cpu_clk_source - connect_bd_net -net sys_cpu_clk [get_bd_pins sys_ps7/S_AXI_HP3_ACLK] - connect_bd_net -net sys_cpu_clk [get_bd_pins axi_daq2_gt/m_axi_aclk] - connect_bd_net -net sys_cpu_clk [get_bd_pins axi_daq2_gt/drp_clk] - connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_daq2_gt_interconnect/ARESETN] $sys_resetn_source - connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_daq2_gt_interconnect/M00_ARESETN] $sys_resetn_source - connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_daq2_gt_interconnect/S00_ARESETN] $sys_resetn_source - connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_daq2_gt/m_axi_aresetn] -} - - # memory interconnects share the same clock (fclk2) - -if {$sys_zynq == 1} { - set sys_fmc_dma_sync_reset [create_bd_cell -type ip -vlnv analog.com:user:util_sync_reset:1.0 sys_fmc_dma_sync_reset] - - set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2] - set sys_fmc_dma_resetn_source [get_bd_pins sys_fmc_dma_sync_reset/sync_resetn] - - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_fmc_dma_sync_reset/clk] - connect_bd_net -net sys_fmc_dma_async_reset \ - [get_bd_pins sys_fmc_dma_sync_reset/async_resetn] \ - [get_bd_pins sys_ps7/FCLK_RESET2_N] - - connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source -} - - # interconnect (mem/dac) - -if {$sys_zynq == 0} { - - connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9144_dma/m_src_axi] - connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_200m_clk_source - connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9144_dma/m_src_axi_aclk] - connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_resetn_source - connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_ad9144_dma/m_src_axi_aresetn] - - connect_bd_intf_net -intf_net axi_mem_interconnect_s10_axi [get_bd_intf_pins axi_mem_interconnect/S10_AXI] [get_bd_intf_pins axi_ad9680_dma/m_dest_axi] - connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S10_ACLK] $sys_200m_clk_source - connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk] - connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S10_ARESETN] $sys_resetn_source - connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn] - -} else { - - connect_bd_intf_net -intf_net axi_ad9144_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9144_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1] - connect_bd_intf_net -intf_net axi_ad9144_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9144_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9144_dma/m_src_axi] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma_interconnect/ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma/m_src_axi_aclk] - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma/m_src_axi_aresetn] - - connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2] - connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9680_dma/m_dest_axi] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk] - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn] -} - - # ila - -set ila_gt_enabled 0 - -if {$ila_gt_enabled == 1} { - - set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_rx_mon] - set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_PROBE0_WIDTH {334}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_PROBE2_WIDTH {128}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_PROBE3_WIDTH {128}] $ila_jesd_rx_mon - - connect_bd_net -net axi_daq2_gt_rx_mon_data [get_bd_pins axi_daq2_gt/rx_mon_data] - connect_bd_net -net axi_daq2_gt_rx_mon_trigger [get_bd_pins axi_daq2_gt/rx_mon_trigger] - connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK] - connect_bd_net -net axi_daq2_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0] - connect_bd_net -net axi_daq2_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1] - connect_bd_net -net axi_daq2_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2] - connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3] - - set ila_jesd_tx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_tx_mon] - set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_tx_mon - set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_jesd_tx_mon - set_property -dict [list CONFIG.C_PROBE0_WIDTH {150}] $ila_jesd_tx_mon - set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_tx_mon - - connect_bd_net -net axi_daq2_gt_tx_mon_data [get_bd_pins axi_daq2_gt/tx_mon_data] - connect_bd_net -net axi_daq2_gt_tx_mon_trigger [get_bd_pins axi_daq2_gt/tx_mon_trigger] - connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins ila_jesd_tx_mon/CLK] - connect_bd_net -net axi_daq2_gt_tx_mon_data [get_bd_pins ila_jesd_tx_mon/PROBE0] - connect_bd_net -net axi_daq2_gt_tx_mon_trigger [get_bd_pins ila_jesd_tx_mon/PROBE1] - -} else { - - set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_rx_mon] - set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_NUM_OF_PROBES {1}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_PROBE0_WIDTH {128}] $ila_jesd_rx_mon - - connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK] - connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE0] -} - - # address map - - create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_core/s_axi/axi_lite] SEG_data_ad9144_core - create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_core/s_axi/axi_lite] SEG_data_ad9680_core - create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_gt/s_axi/axi_lite] SEG_data_daq2_gt - create_bd_addr_seg -range 0x00010000 -offset 0x44A90000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_jesd/s_axi/Reg] SEG_data_ad9144_jesd - create_bd_addr_seg -range 0x00010000 -offset 0x44A80000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_jesd/s_axi/Reg] SEG_data_ad9680_jesd - create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_dma/s_axi/axi_lite] SEG_data_ad9680_dma - create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_dma/s_axi/axi_lite] SEG_data_ad9144_dma - -if {$sys_zynq == 0} { - - create_bd_addr_seg -range 0x00010000 -offset 0x40000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_gpio/S_AXI/Reg] SEG_data_daq2_gpio - create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_spi/axi_lite/Reg] SEG_data_daq2_spi -} - -if {$sys_zynq == 0} { - - create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9144_dma/m_src_axi] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl - create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl - create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_daq2_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl - -} else { - - create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9144_dma/m_src_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm - create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm - create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_daq2_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm -} - - +set_property -dict [list CONFIG.PCORE_DEVICE_TYPE {1}] $axi_daq2_gt +set_property -dict [list CONFIG.PCORE_QPLL_FBDIV {20}] $axi_daq2_gt +set_property -dict [list CONFIG.PCORE_QPLL_REFCLK_DIV {1}] $axi_daq2_gt diff --git a/projects/daq2/kcu105/system_constr.xdc b/projects/daq2/kcu105/system_constr.xdc index 71bf90f32..1586d7c6f 100644 --- a/projects/daq2/kcu105/system_constr.xdc +++ b/projects/daq2/kcu105/system_constr.xdc @@ -19,14 +19,14 @@ set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports set_property -dict {PACKAGE_PIN K6} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P set_property -dict {PACKAGE_PIN K5} [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N -set_property -dict {PACKAGE_PIN B6} [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P -set_property -dict {PACKAGE_PIN B5} [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N -set_property -dict {PACKAGE_PIN C4} [get_ports tx_data_p[1]] ; ## A26 FMC_HPC_DP2_C2M_P -set_property -dict {PACKAGE_PIN C3} [get_ports tx_data_n[1]] ; ## A27 FMC_HPC_DP2_C2M_N -set_property -dict {PACKAGE_PIN D6} [get_ports tx_data_p[2]] ; ## A22 FMC_HPC_DP1_C2M_P -set_property -dict {PACKAGE_PIN D5} [get_ports tx_data_n[2]] ; ## A23 FMC_HPC_DP1_C2M_N -set_property -dict {PACKAGE_PIN F6} [get_ports tx_data_p[3]] ; ## C02 FMC_HPC_DP0_C2M_P -set_property -dict {PACKAGE_PIN F5} [get_ports tx_data_n[3]] ; ## C03 FMC_HPC_DP0_C2M_N +set_property -dict {PACKAGE_PIN B6} [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[0]) +set_property -dict {PACKAGE_PIN B5} [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[0]) +set_property -dict {PACKAGE_PIN F6} [get_ports tx_data_p[1]] ; ## C02 FMC_HPC_DP0_C2M_P (tx_data_p[3]) +set_property -dict {PACKAGE_PIN F5} [get_ports tx_data_n[1]] ; ## C03 FMC_HPC_DP0_C2M_N (tx_data_n[3]) +set_property -dict {PACKAGE_PIN C4} [get_ports tx_data_p[2]] ; ## A26 FMC_HPC_DP2_C2M_P (tx_data_p[1]) +set_property -dict {PACKAGE_PIN C3} [get_ports tx_data_n[2]] ; ## A27 FMC_HPC_DP2_C2M_N (tx_data_n[1]) +set_property -dict {PACKAGE_PIN D6} [get_ports tx_data_p[3]] ; ## A22 FMC_HPC_DP1_C2M_P (tx_data_p[2]) +set_property -dict {PACKAGE_PIN D5} [get_ports tx_data_n[3]] ; ## A23 FMC_HPC_DP1_C2M_N (tx_data_n[2]) set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sysref_p] ; ## H10 FMC_HPC_LA04_P @@ -37,10 +37,9 @@ set_property -dict {PACKAGE_PIN L8 IOSTANDARD LVCMOS18} [get_ports spi_csn_da set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVCMOS18} [get_ports spi_csn_adc] ; ## D15 FMC_HPC_LA09_N set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## D12 FMC_HPC_LA05_N set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports spi_sdio] ; ## D14 FMC_HPC_LA09_P +set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS18} [get_ports spi_dir] ; ## G13 FMC_HPC_LA08_N -set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS18} [get_ports clkd_reset] ; ## C11 FMC_HPC_LA06_N set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS18} [get_ports clkd_sync] ; ## G12 FMC_HPC_LA08_P -set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS18} [get_ports clkd_pd] ; ## G13 FMC_HPC_LA08_N set_property -dict {PACKAGE_PIN K8 IOSTANDARD LVCMOS18} [get_ports dac_reset] ; ## C15 FMC_HPC_LA10_N set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS18} [get_ports dac_txen] ; ## G16 FMC_HPC_LA12_N set_property -dict {PACKAGE_PIN D13 IOSTANDARD LVCMOS18} [get_ports adc_pd] ; ## C10 FMC_HPC_LA06_P @@ -51,6 +50,9 @@ set_property -dict {PACKAGE_PIN E10 IOSTANDARD LVCMOS18} [get_ports dac_irq] set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports adc_fda] ; ## H16 FMC_HPC_LA11_P set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports adc_fdb] ; ## H17 FMC_HPC_LA11_N +set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports trig_p] ; ## H13 FMC_HPC_LA07_P +set_property -dict {PACKAGE_PIN E8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports trig_n] ; ## H14 FMC_HPC_LA07_N + # clocks create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p] diff --git a/projects/daq2/kcu105/system_project.tcl b/projects/daq2/kcu105/system_project.tcl index 8e3431cdd..223a63de8 100644 --- a/projects/daq2/kcu105/system_project.tcl +++ b/projects/daq2/kcu105/system_project.tcl @@ -1,4 +1,6 @@ + + source ../../scripts/adi_env.tcl source $ad_hdl_dir/projects/scripts/adi_project.tcl diff --git a/projects/daq2/kcu105/system_top.v b/projects/daq2/kcu105/system_top.v index a659e6ae6..c26c3c347 100644 --- a/projects/daq2/kcu105/system_top.v +++ b/projects/daq2/kcu105/system_top.v @@ -79,7 +79,6 @@ module system_top ( gpio_led, gpio_sw, - iic_rstn, iic_scl, iic_sda, @@ -109,6 +108,9 @@ module system_top ( tx_data_p, tx_data_n, + trig_p, + trig_n, + adc_fdb, adc_fda, dac_irq, @@ -117,15 +119,14 @@ module system_top ( adc_pd, dac_txen, dac_reset, - clkd_pd, clkd_sync, - clkd_reset, spi_csn_clk, spi_csn_dac, spi_csn_adc, spi_clk, - spi_sdio); + spi_sdio, + spi_dir); input sys_rst; input sys_clk_p; @@ -165,7 +166,6 @@ module system_top ( inout [ 7:0] gpio_led; inout [ 8:0] gpio_sw; - output iic_rstn; inout iic_scl; inout iic_sda; @@ -195,6 +195,9 @@ module system_top ( output [ 3:0] tx_data_p; output [ 3:0] tx_data_n; + input trig_p; + input trig_n; + inout adc_fdb; inout adc_fda; inout dac_irq; @@ -203,15 +206,14 @@ module system_top ( inout adc_pd; inout dac_txen; inout dac_reset; - inout clkd_pd; inout clkd_sync; - inout clkd_reset; output spi_csn_clk; output spi_csn_dac; output spi_csn_adc; output spi_clk; inout spi_sdio; + output spi_dir; // internal registers @@ -226,6 +228,7 @@ module system_top ( // internal signals + wire trig; wire rx_ref_clk; wire rx_sysref; wire rx_sync; @@ -258,6 +261,7 @@ module system_top ( wire [ 4:0] gpio_status_i; wire [ 4:0] gpio_status_o; wire [ 4:0] gpio_status_t; + wire [31:0] mb_intrs; // adc-dac data @@ -417,18 +421,24 @@ module system_top ( .spi_clk (spi_clk), .spi_mosi (spi_mosi), .spi_miso (spi_miso), - .spi_sdio (spi_sdio)); + .spi_sdio (spi_sdio), + .spi_dir (spi_dir)); - ad_iobuf #(.DATA_WIDTH(26)) i_iobuf ( - .dt ({gpio_ctl_t[5:0], gpio_status_t[4:0]}), - .di ({gpio_ctl_o[5:0], gpio_status_o[4:0]}), - .do ({gpio_ctl_i[5:0], gpio_status_i[4:0]}), + IBUFDS i_ibufds_trig ( + .I (trig_p), + .IB (trig_n), + .O (trig)); + + assign gpio_ctl_i[0] = trig; + + ad_iobuf #(.DATA_WIDTH(9)) i_iobuf ( + .dt ({gpio_ctl_t[5:3], gpio_ctl_t[1], gpio_status_t[4:0]}), + .di ({gpio_ctl_o[5:3], gpio_ctl_o[1], gpio_status_o[4:0]}), + .do ({gpio_ctl_i[5:3], gpio_ctl_i[1], gpio_status_i[4:0]}), .dio ({ adc_pd, // 10 dac_txen, // 9 dac_reset, // 8 - clkd_pd, // 7 clkd_sync, // 6 - clkd_reset, // 5 adc_fdb, // 4 adc_fda, // 3 dac_irq, // 2 @@ -445,6 +455,10 @@ module system_top ( .adc_enable_1 (adc_enable_1), .adc_valid_0 (adc_valid_0), .adc_valid_1 (adc_valid_1), + .axi_ad9144_dma_intr (mb_intrs[13]), + .axi_ad9680_dma_intr (mb_intrs[12]), + .axi_daq2_gpio_intr (mb_intrs[11]), + .axi_daq2_spi_intr (mb_intrs[10]), .c0_ddr4_act_n (ddr4_act_n), .c0_ddr4_adr (ddr4_addr), .c0_ddr4_ba (ddr4_ba), @@ -491,7 +505,28 @@ module system_top ( .hdmi_vsync (hdmi_vsync), .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), - .iic_rstn (iic_rstn), + .mb_intr_10 (mb_intrs[10]), + .mb_intr_11 (mb_intrs[11]), + .mb_intr_12 (mb_intrs[12]), + .mb_intr_13 (mb_intrs[13]), + .mb_intr_14 (mb_intrs[14]), + .mb_intr_15 (mb_intrs[15]), + .mb_intr_16 (mb_intrs[16]), + .mb_intr_17 (mb_intrs[17]), + .mb_intr_18 (mb_intrs[18]), + .mb_intr_19 (mb_intrs[19]), + .mb_intr_20 (mb_intrs[20]), + .mb_intr_21 (mb_intrs[21]), + .mb_intr_22 (mb_intrs[22]), + .mb_intr_23 (mb_intrs[23]), + .mb_intr_24 (mb_intrs[24]), + .mb_intr_25 (mb_intrs[25]), + .mb_intr_26 (mb_intrs[26]), + .mb_intr_27 (mb_intrs[27]), + .mb_intr_28 (mb_intrs[28]), + .mb_intr_29 (mb_intrs[29]), + .mb_intr_30 (mb_intrs[30]), + .mb_intr_31 (mb_intrs[31]), .mdio_mdc (mdio_mdc), .mdio_mdio_io (mdio_mdio), .phy_clk_clk_n (phy_clk_n), @@ -524,8 +559,7 @@ module system_top ( .tx_sync (tx_sync), .tx_sysref (tx_sysref), .uart_sin (uart_sin), - .uart_sout (uart_sout), - .unc_int4 (1'b0)); + .uart_sout (uart_sout)); endmodule diff --git a/projects/daq2/zc706/system_bd.tcl b/projects/daq2/zc706/system_bd.tcl index 453f8f3e1..d9beadd1b 100644 --- a/projects/daq2/zc706/system_bd.tcl +++ b/projects/daq2/zc706/system_bd.tcl @@ -3,55 +3,3 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl source ../common/daq2_bd.tcl -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9144_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9144_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma - -p_plddr3_fifo [current_bd_instance .] plddr3_fifo 128 - -set DDR3 [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3] -set sys_clk [create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk] - -connect_bd_intf_net -intf_net DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins plddr3_fifo/DDR3] -connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins plddr3_fifo/sys_clk] - -delete_bd_objs [get_bd_nets axi_ad9680_adc_clk] -delete_bd_objs [get_bd_nets axi_ad9680_adc_dwr] -delete_bd_objs [get_bd_nets axi_ad9680_adc_ddata] -delete_bd_objs [get_bd_nets axi_ad9680_adc_dsync] -delete_bd_objs [get_bd_nets axi_ad9680_adc_dovf] - -connect_bd_net -net [get_bd_nets axi_daq2_gt_rx_rst] [get_bd_pins plddr3_fifo/adc_rst] [get_bd_pins axi_daq2_gt/rx_rst] -connect_bd_net -net [get_bd_nets sys_fmc_dma_resetn] [get_bd_pins plddr3_fifo/dma_rstn] [get_bd_pins sys_fmc_dma_sync_reset/sync_resetn] -connect_bd_net -net axi_ad9680_dma_xfer_req [get_bd_pins axi_ad9680_dma/fifo_wr_xfer_req] [get_bd_pins plddr3_fifo/axi_xfer_req] - -connect_bd_net -net axi_ad9680_adc_clk [get_bd_pins axi_ad9680_core/adc_clk] [get_bd_pins plddr3_fifo/adc_clk] -connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins plddr3_fifo/adc_wovf] -connect_bd_net -net axi_ad9680_adc_dwr [get_bd_ports adc_dwr] [get_bd_pins plddr3_fifo/adc_wr] -connect_bd_net -net axi_ad9680_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins plddr3_fifo/adc_wdata] - -connect_bd_net -net axi_ad9680_dma_clk [get_bd_pins plddr3_fifo/dma_clk] [get_bd_pins axi_ad9680_dma/fifo_wr_clk] -connect_bd_net -net axi_ad9680_dma_dwr [get_bd_pins plddr3_fifo/dma_wr] [get_bd_pins axi_ad9680_dma/fifo_wr_en] -connect_bd_net -net axi_ad9680_dma_ddata [get_bd_pins plddr3_fifo/dma_wdata] [get_bd_pins axi_ad9680_dma/fifo_wr_din] -connect_bd_net -net axi_ad9680_dma_dovf [get_bd_pins plddr3_fifo/dma_wovf] [get_bd_pins axi_ad9680_dma/fifo_wr_overflow] -connect_bd_net -net axi_ad9680_adc_dsync [get_bd_ports adc_dsync] [get_bd_pins axi_ad9680_dma/fifo_wr_sync] - -connect_bd_net -net axi_ad9680_adc_clk [get_bd_ports adc_clk] -connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3] - -set ila_dma_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_dma_mon] -set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_dma_mon -set_property -dict [list CONFIG.C_NUM_OF_PROBES {3}] $ila_dma_mon -set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_dma_mon -set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_dma_mon -set_property -dict [list CONFIG.C_PROBE2_WIDTH {64}] $ila_dma_mon - -connect_bd_net -net axi_ad9680_dma_clk [get_bd_pins ila_dma_mon/clk] -connect_bd_net -net axi_ad9680_dma_dwr [get_bd_pins ila_dma_mon/probe0] -connect_bd_net -net axi_ad9680_dma_xfer_req [get_bd_pins ila_dma_mon/probe1] -connect_bd_net -net axi_ad9680_dma_ddata [get_bd_pins ila_dma_mon/probe2] - - -create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces plddr3_fifo/axi_fifo2s/axi] [get_bd_addr_segs plddr3_fifo/axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl_memaddr - diff --git a/projects/daq2/zc706/system_constr.xdc b/projects/daq2/zc706/system_constr.xdc index 8057c4245..ee9aeae89 100644 --- a/projects/daq2/zc706/system_constr.xdc +++ b/projects/daq2/zc706/system_constr.xdc @@ -18,14 +18,14 @@ set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ set_property -dict {PACKAGE_PIN AD10} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P set_property -dict {PACKAGE_PIN AD9 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N -set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P -set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N -set_property -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[1]] ; ## A26 FMC_HPC_DP2_C2M_P -set_property -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[1]] ; ## A27 FMC_HPC_DP2_C2M_N -set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[2]] ; ## A22 FMC_HPC_DP1_C2M_P -set_property -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[2]] ; ## A23 FMC_HPC_DP1_C2M_N -set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[3]] ; ## C02 FMC_HPC_DP0_C2M_P -set_property -dict {PACKAGE_PIN AK9 } [get_ports tx_data_n[3]] ; ## C03 FMC_HPC_DP0_C2M_N +set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[0]) +set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[0]) +set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[1]] ; ## C02 FMC_HPC_DP0_C2M_P (tx_data_p[3]) +set_property -dict {PACKAGE_PIN AK9 } [get_ports tx_data_n[1]] ; ## C03 FMC_HPC_DP0_C2M_N (tx_data_n[3]) +set_property -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[2]] ; ## A26 FMC_HPC_DP2_C2M_P (tx_data_p[1]) +set_property -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[2]] ; ## A27 FMC_HPC_DP2_C2M_N (tx_data_n[1]) +set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[3]] ; ## A22 FMC_HPC_DP1_C2M_P (tx_data_p[2]) +set_property -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[3]] ; ## A23 FMC_HPC_DP1_C2M_N (tx_data_n[2]) set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_p] ; ## H10 FMC_HPC_LA04_P @@ -58,19 +58,4 @@ create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p] create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] create_clock -name tx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_tx_clk] create_clock -name rx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_rx_clk] -create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2] -create_clock -name pl_ddr_clk -period 5.00 [get_pins i_system_wrapper/system_i/plddr3_fifo/axi_ddr_cntrl/ui_clk] -create_clock -name pl_dma_clk -period 15.62 [get_pins i_system_wrapper/system_i/plddr3_fifo/axi_ddr_cntrl/ui_addn_clk_0] -set_clock_groups -asynchronous -group {tx_div_clk} -set_clock_groups -asynchronous -group {rx_div_clk} -set_clock_groups -asynchronous -group {fmc_dma_clk} -set_clock_groups -asynchronous -group {pl_ddr_clk} -set_clock_groups -asynchronous -group {pl_dma_clk} - -set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE] diff --git a/projects/daq2/zc706/system_project.tcl b/projects/daq2/zc706/system_project.tcl index 73e0af659..3714ab0ab 100644 --- a/projects/daq2/zc706/system_project.tcl +++ b/projects/daq2/zc706/system_project.tcl @@ -12,6 +12,9 @@ adi_project_files daq2_zc706 [list \ "$ad_hdl_dir/library/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] +set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc] +set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] + adi_project_run daq2_zc706 diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl index ce30eac92..a70d73041 100644 --- a/projects/fmcomms2/common/fmcomms2_bd.tcl +++ b/projects/fmcomms2/common/fmcomms2_bd.tcl @@ -68,11 +68,6 @@ if {$sys_zynq == 1} { set util_dac_unpack [create_bd_cell -type ip -vlnv analog.com:user:util_dac_unpack:1.0 util_dac_unpack] set_property -dict [list CONFIG.CHANNELS {4}] $util_dac_unpack - # constant 0 - - set constant_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 constant_0] - set_property -dict [list CONFIG.CONST_VAL {0}] $constant_0 - if {$sys_zynq == 1} { set_property -dict [list CONFIG.C_DMA_AXI_PROTOCOL_SRC {1}] $axi_ad9361_dac_dma } @@ -323,6 +318,7 @@ if {$sys_zynq == 0} { # ila (adc) set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_adc] + set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc set_property -dict [list CONFIG.C_NUM_OF_PROBES {8}] $ila_adc set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_adc diff --git a/projects/fmcomms2/zc706/system_constr.xdc b/projects/fmcomms2/zc706/system_constr.xdc index 452f6bbec..d24e70ce1 100644 --- a/projects/fmcomms2/zc706/system_constr.xdc +++ b/projects/fmcomms2/zc706/system_constr.xdc @@ -69,7 +69,3 @@ set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS25} [get_ports sp create_clock -name rx_clk -period 4.00 [get_ports rx_clk_in_p] create_clock -name ad9361_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_ad9361/clk] - -set_clock_groups -asynchronous -group {ad9361_clk} -set_clock_groups -asynchronous -group {rx_clk} - diff --git a/projects/fmcomms6/common/fmcomms6_bd.tcl b/projects/fmcomms6/common/fmcomms6_bd.tcl index 623ab83cd..3752d557d 100644 --- a/projects/fmcomms6/common/fmcomms6_bd.tcl +++ b/projects/fmcomms6/common/fmcomms6_bd.tcl @@ -229,7 +229,7 @@ if {$sys_zynq == 0} { # ila (adc) -set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_adc] +set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_adc] set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_adc set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc set_property -dict [list CONFIG.C_PROBE1_WIDTH {64}] $ila_adc diff --git a/projects/fmcomms6/zc706/system_constr.xdc b/projects/fmcomms6/zc706/system_constr.xdc index a650a93ee..01ec445cf 100644 --- a/projects/fmcomms6/zc706/system_constr.xdc +++ b/projects/fmcomms6/zc706/system_constr.xdc @@ -55,8 +55,5 @@ set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVCMOS25} [get_ports adf4351_ create_clock -name adc_clk_in -period 3.22 [get_ports adc_clk_in_p] create_clock -name adc_clk -period 3.22 [get_pins i_system_wrapper/system_i/axi_ad9652/adc_clk] -create_clock -name fmc_dma_clk -period 8.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2] set_clock_groups -asynchronous -group {adc_clk} -set_clock_groups -asynchronous -group {fmc_dma_clk} - diff --git a/projects/pmods/ad7175_zed/system_bd.tcl b/projects/pmods/ad7175_zed/system_bd.tcl new file mode 100644 index 000000000..84e3ebf9f --- /dev/null +++ b/projects/pmods/ad7175_zed/system_bd.tcl @@ -0,0 +1,97 @@ + +source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl +set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {32}] $sys_ps7 +set_property -dict [list CONFIG.NUM_MI {9}] $axi_cpu_interconnect + +set_property LEFT 31 [get_bd_ports GPIO_I] +set_property LEFT 31 [get_bd_ports GPIO_O] +set_property LEFT 31 [get_bd_ports GPIO_T] + +set adc_sdo_i [create_bd_port -dir I adc_sdo_i] +set adc_sdi_o [create_bd_port -dir O adc_sdi_o] +set adc_cs_o [create_bd_port -dir O adc_cs_o] +set adc_sclk_o [create_bd_port -dir O adc_sclk_o] +set led_clk_o [create_bd_port -dir O led_clk_o] +set dma_data [create_bd_port -dir I -from 127 -to 0 dma_data] +set adc_data_0 [create_bd_port -dir O -from 31 -to 0 adc_data_0] +set adc_data_1 [create_bd_port -dir O -from 31 -to 0 adc_data_1] +set adc_data_2 [create_bd_port -dir O -from 31 -to 0 adc_data_2] +set adc_data_3 [create_bd_port -dir O -from 31 -to 0 adc_data_3] + +set axi_ad7175 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad7175:1.0 axi_ad7175] + +set axi_ad7175_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad7175_dma] +set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad7175_dma +set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad7175_dma +set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad7175_dma +set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $axi_ad7175_dma +set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad7175_dma +set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad7175_dma +set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad7175_dma +set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad7175_dma +set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad7175_dma +set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad7175_dma +set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad7175_dma +set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad7175_dma + +set axi_ad7175_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad7175_dma_interconnect] +set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad7175_dma_interconnect + +set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {10.0}] $sys_ps7 + +set sys_adc_clk_source [get_bd_pins sys_ps7/FCLK_CLK2] + +connect_bd_net -net axi_ad7175_adc_sdo_i [get_bd_ports adc_sdo_i] [get_bd_pins axi_ad7175/adc_sdo_i] +connect_bd_net -net axi_ad7175_adc_sdi_o [get_bd_ports adc_sdi_o] [get_bd_pins axi_ad7175/adc_sdi_o] +connect_bd_net -net axi_ad7175_adc_cs_o [get_bd_ports adc_cs_o] [get_bd_pins axi_ad7175/adc_cs_o] +connect_bd_net -net axi_ad7175_adc_sclk_o [get_bd_ports adc_sclk_o] [get_bd_pins axi_ad7175/adc_sclk_o] +connect_bd_net -net axi_ad7175_led_clk_o [get_bd_ports led_clk_o] [get_bd_pins axi_ad7175/led_clk_o] + +connect_bd_net -net axi_ad7175_dma_valid [get_bd_pins axi_ad7175/adc_valid_o] [get_bd_pins axi_ad7175_dma/fifo_wr_en] + +connect_bd_net -net axi_ad7175_dma_data_0 [get_bd_pins axi_ad7175/adc_data_0] [get_bd_ports adc_data_0] +connect_bd_net -net axi_ad7175_dma_data_1 [get_bd_pins axi_ad7175/adc_data_1] [get_bd_ports adc_data_1] +connect_bd_net -net axi_ad7175_dma_data_2 [get_bd_pins axi_ad7175/adc_data_2] [get_bd_ports adc_data_2] +connect_bd_net -net axi_ad7175_dma_data_3 [get_bd_pins axi_ad7175/adc_data_3] [get_bd_ports adc_data_3] +connect_bd_net -net axi_ad7175_dma_data [get_bd_ports dma_data] [get_bd_pins axi_ad7175_dma/fifo_wr_din] + +connect_bd_net -net axi_ad7175_dma_dovf [get_bd_pins axi_ad7175/adc_dovf] [get_bd_pins axi_ad7175_dma/fifo_wr_overflow] +connect_bd_net -net axi_ad7175_dma_irq [get_bd_pins axi_ad7175_dma/irq] [get_bd_pins sys_concat_intc/In13] + +connect_bd_net -net sys_adc_clk_source [get_bd_pins axi_ad7175/adc_clk_i] $sys_adc_clk_source +connect_bd_net -net sys_adc_dma_clk [get_bd_pins axi_ad7175_dma/fifo_wr_clk] [get_bd_pins axi_ad7175/adc_clk] + +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad7175/s_axi_aclk] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad7175_dma/s_axi_aclk] $sys_100m_clk_source + +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad7175/s_axi_aresetn] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad7175_dma/s_axi_aresetn] $sys_100m_resetn_source + +connect_bd_intf_net -intf_net axi_cpu_interconnect_m07 [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad7175_dma/s_axi] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m08 [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad7175/s_axi] + +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source + +connect_bd_intf_net -intf_net axi_ad7175_dma_interconnect_s0 [get_bd_intf_pins axi_ad7175_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad7175_dma/m_dest_axi] +connect_bd_intf_net -intf_net axi_ad7175_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad7175_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2] + +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad7175_dma_interconnect/S00_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad7175_dma/m_dest_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad7175_dma_interconnect/ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad7175_dma_interconnect/M00_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad7175_dma_interconnect/ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad7175_dma_interconnect/M00_ARESETN] $sys_100m_resetn_source + +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad7175_dma/m_dest_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad7175_dma_interconnect/S00_ARESETN] $sys_100m_resetn_source + +create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad7175/s_axi/axi_lite] SEG_data_ad7175_core +create_bd_addr_seg -range 0x00010000 -offset 0x44A30000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad7175_dma/s_axi/axi_lite] SEG_data_ad7175_dma + +create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad7175_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm \ No newline at end of file diff --git a/projects/pmods/ad7175_zed/system_constr.xdc b/projects/pmods/ad7175_zed/system_constr.xdc new file mode 100644 index 000000000..664e7216e --- /dev/null +++ b/projects/pmods/ad7175_zed/system_constr.xdc @@ -0,0 +1,12 @@ + +# PMOD JA + +#set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_port gain_o]; +set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS33} [get_ports led_clk_o]; +#set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS33} [get_ports ad_sync_nc]; +#set_property -dict {PACKAGE_PIN AA9 IOSTANDARD LVCMOS33} [get_ports ad_clkio_nc]; + +set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS33} [get_ports adc_cs_o]; +set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS33} [get_ports adc_sdi_o]; +set_property -dict {PACKAGE_PIN AB9 IOSTANDARD LVCMOS33} [get_ports adc_sdo_i]; +set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS33} [get_ports adc_sclk_o]; diff --git a/projects/pmods/ad7175_zed/system_project.tcl b/projects/pmods/ad7175_zed/system_project.tcl new file mode 100644 index 000000000..a4def392d --- /dev/null +++ b/projects/pmods/ad7175_zed/system_project.tcl @@ -0,0 +1,15 @@ + + + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl + +adi_project_create adv7511_zed +adi_project_files adv7511_zed [list \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ] + +adi_project_run adv7511_zed + + diff --git a/projects/pmods/ad7175_zed/system_top.v b/projects/pmods/ad7175_zed/system_top.v new file mode 100644 index 000000000..24e76022d --- /dev/null +++ b/projects/pmods/ad7175_zed/system_top.v @@ -0,0 +1,243 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + DDR_addr, + DDR_ba, + DDR_cas_n, + DDR_ck_n, + DDR_ck_p, + DDR_cke, + DDR_cs_n, + DDR_dm, + DDR_dq, + DDR_dqs_n, + DDR_dqs_p, + DDR_odt, + DDR_ras_n, + DDR_reset_n, + DDR_we_n, + + FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp, + FIXED_IO_mio, + FIXED_IO_ps_clk, + FIXED_IO_ps_porb, + FIXED_IO_ps_srstb, + + gpio_bd, + + hdmi_out_clk, + hdmi_vsync, + hdmi_hsync, + hdmi_data_e, + hdmi_data, + + i2s_mclk, + i2s_bclk, + i2s_lrclk, + i2s_sdata_out, + i2s_sdata_in, + + spdif, + + iic_scl, + iic_sda, + iic_mux_scl, + iic_mux_sda, + + adc_sdo_i, + adc_sdi_o, + adc_cs_o, + adc_sclk_o, + led_clk_o, + + otg_vbusoc); + + inout [14:0] DDR_addr; + inout [ 2:0] DDR_ba; + inout DDR_cas_n; + inout DDR_ck_n; + inout DDR_ck_p; + inout DDR_cke; + inout DDR_cs_n; + inout [ 3:0] DDR_dm; + inout [31:0] DDR_dq; + inout [ 3:0] DDR_dqs_n; + inout [ 3:0] DDR_dqs_p; + inout DDR_odt; + inout DDR_ras_n; + inout DDR_reset_n; + inout DDR_we_n; + + inout FIXED_IO_ddr_vrn; + inout FIXED_IO_ddr_vrp; + inout [53:0] FIXED_IO_mio; + inout FIXED_IO_ps_clk; + inout FIXED_IO_ps_porb; + inout FIXED_IO_ps_srstb; + + inout [31:0] gpio_bd; + + output hdmi_out_clk; + output hdmi_vsync; + output hdmi_hsync; + output hdmi_data_e; + output [15:0] hdmi_data; + + output spdif; + + output i2s_mclk; + output i2s_bclk; + output i2s_lrclk; + output i2s_sdata_out; + input i2s_sdata_in; + + + inout iic_scl; + inout iic_sda; + inout [ 1:0] iic_mux_scl; + inout [ 1:0] iic_mux_sda; + + input adc_sdo_i; + output adc_sdi_o; + output adc_cs_o; + output adc_sclk_o; + output led_clk_o; + + input otg_vbusoc; + + // internal signals + + wire [31:0] gpio_i; + wire [31:0] gpio_o; + wire [31:0] gpio_t; + wire [ 1:0] iic_mux_scl_i_s; + wire [ 1:0] iic_mux_scl_o_s; + wire iic_mux_scl_t_s; + wire [ 1:0] iic_mux_sda_i_s; + wire [ 1:0] iic_mux_sda_o_s; + wire iic_mux_sda_t_s; + wire [31:0] adc_data_0; + wire [31:0] adc_data_1; + wire [31:0] adc_data_2; + wire [31:0] adc_data_3; + wire [127:0] dma_data; + + // instantiations + + genvar n; + generate + for (n = 0; n <= 31; n = n + 1) begin: g_iobuf_gpio_bd + IOBUF i_iobuf_gpio_bd ( + .I (gpio_o[n]), + .O (gpio_i[n]), + .T (gpio_t[n]), + .IO (gpio_bd[n])); + end + endgenerate + + IOBUF i_iic_mux_scl_0 (.I(iic_mux_scl_o_s[0]), .O(iic_mux_scl_i_s[0]), .T(iic_mux_scl_t_s), .IO(iic_mux_scl[0])); + IOBUF i_iic_mux_scl_1 (.I(iic_mux_scl_o_s[1]), .O(iic_mux_scl_i_s[1]), .T(iic_mux_scl_t_s), .IO(iic_mux_scl[1])); + IOBUF i_iic_mux_sda_0 (.I(iic_mux_sda_o_s[0]), .O(iic_mux_sda_i_s[0]), .T(iic_mux_sda_t_s), .IO(iic_mux_sda[0])); + IOBUF i_iic_mux_sda_1 (.I(iic_mux_sda_o_s[1]), .O(iic_mux_sda_i_s[1]), .T(iic_mux_sda_t_s), .IO(iic_mux_sda[1])); + + system_wrapper i_system_wrapper ( + .DDR_addr (DDR_addr), + .DDR_ba (DDR_ba), + .DDR_cas_n (DDR_cas_n), + .DDR_ck_n (DDR_ck_n), + .DDR_ck_p (DDR_ck_p), + .DDR_cke (DDR_cke), + .DDR_cs_n (DDR_cs_n), + .DDR_dm (DDR_dm), + .DDR_dq (DDR_dq), + .DDR_dqs_n (DDR_dqs_n), + .DDR_dqs_p (DDR_dqs_p), + .DDR_odt (DDR_odt), + .DDR_ras_n (DDR_ras_n), + .DDR_reset_n (DDR_reset_n), + .DDR_we_n (DDR_we_n), + .FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn), + .FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp), + .FIXED_IO_mio (FIXED_IO_mio), + .FIXED_IO_ps_clk (FIXED_IO_ps_clk), + .FIXED_IO_ps_porb (FIXED_IO_ps_porb), + .FIXED_IO_ps_srstb (FIXED_IO_ps_srstb), + .GPIO_I (gpio_i), + .GPIO_O (gpio_o), + .GPIO_T (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_fmc_scl_io (iic_scl), + .iic_fmc_sda_io (iic_sda), + .iic_mux_scl_I (iic_mux_scl_i_s), + .iic_mux_scl_O (iic_mux_scl_o_s), + .iic_mux_scl_T (iic_mux_scl_t_s), + .iic_mux_sda_I (iic_mux_sda_i_s), + .iic_mux_sda_O (iic_mux_sda_o_s), + .iic_mux_sda_T (iic_mux_sda_t_s), + .adc_sdo_i (adc_sdo_i), + .adc_sdi_o (adc_sdi_o), + .adc_cs_o (adc_cs_o), + .adc_sclk_o (adc_sclk_o), + .led_clk_o (led_clk_o), + .dma_data ({adc_data_3, adc_data_2, adc_data_1, adc_data_0}), + .adc_data_3(adc_data_3), + .adc_data_2(adc_data_2), + .adc_data_1(adc_data_1), + .adc_data_0(adc_data_0), + .otg_vbusoc (otg_vbusoc), + .spdif (spdif)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/scripts/adi_board.tcl b/projects/scripts/adi_board.tcl index 1594d4771..d9aeede0a 100644 --- a/projects/scripts/adi_board.tcl +++ b/projects/scripts/adi_board.tcl @@ -16,11 +16,11 @@ variable sys_interrupts_q ################################################################################################### set sys_cpu_interconnect_index 0 -set sys_hp0_interconnect_index 0 -set sys_hp1_interconnect_index 0 -set sys_hp2_interconnect_index 0 -set sys_hp3_interconnect_index 0 -set sys_mem_interconnect_index 0 +set sys_hp0_interconnect_index -1 +set sys_hp1_interconnect_index -1 +set sys_hp2_interconnect_index -1 +set sys_hp3_interconnect_index -1 +set sys_mem_interconnect_index -1 set sys_interrupts_n 0 ################################################################################################### @@ -65,14 +65,138 @@ proc ad_connect {p_name_1 p_name_2} { ################################################################################################### ################################################################################################### -proc ad_mem_interconnect {p_sel p_name p_clk} { +proc ad_mem_interconnect {p_clk p_name} { - set m_clk_source [filter [get_bd_pins -of_objects [get_bd_nets $p_clk]] -regexp "DIR == O"] + ad_mem_interconnect_int "MEM" $p_clk $p_name +} - if {($p_sel == "HP0") && ($sys_zynq == 1)} { +proc ad_hp0_interconnect {p_clk p_name} { + + ad_mem_interconnect_int "HP0" $p_clk $p_name +} + +proc ad_hp1_interconnect {p_clk p_name} { + + ad_mem_interconnect_int "HP1" $p_clk $p_name +} + +proc ad_hp2_interconnect {p_clk p_name} { + + ad_mem_interconnect_int "HP2" $p_clk $p_name +} + +proc ad_hp3_interconnect {p_name p_clk} { + + ad_mem_interconnect_int "HP3" $p_clk $p_name +} + +################################################################################################### +################################################################################################### + +proc ad_mem_interconnect_int {p_sel p_clk p_name} { + + global sys_zynq + global sys_hp0_interconnect_index + global sys_hp1_interconnect_index + global sys_hp2_interconnect_index + global sys_hp3_interconnect_index + global sys_mem_interconnect_index + + set p_intf_name [lrange [split $p_name "/"] end end] + set p_cell_name [lrange [split $p_name "/"] 0 0] + set p_intf_clock [filter [get_bd_pins -quiet -of_objects [get_bd_cells $p_cell_name]] \ + -regexp "CONFIG.ASSOCIATED_BUSIF == ${p_intf_name}"] + + if {($p_sel eq "HP0") && ($sys_zynq == 1)} { if {$sys_hp0_interconnect_index == 0} { } } + + + if {($p_sel eq "MEM") && ($sys_zynq == 1)} { + + set i_str "S$sys_mem_interconnect_index" + if {$sys_mem_interconnect_index < 10} { + set i_str "S0$sys_mem_interconnect_index" + } + + if {$sys_mem_interconnect_index == -1} { + ad_connect sys_cpu_resetn axi_mem_interconnect/ARESETN + ad_connect $p_clk axi_mem_interconnect/ACLK + ad_connect sys_cpu_resetn axi_mem_interconnect/M00_ARESETN + ad_connect $p_clk axi_mem_interconnect/M00_ACLK + ad_connect axi_mem_interconnect/M00_AXI $p_name + } else { + ad_connect sys_cpu_resetn axi_mem_interconnect/${i_str}_ARESETN + ad_connect $p_clk axi_mem_interconnect/${i_str}_ACLK + ad_connect axi_mem_interconnect/${i_str}_AXI $p_name + ad_connect $p_clk $p_intf_clock + } + + set sys_mem_interconnect_index [expr $sys_mem_interconnect_index + 1] + } +} + +################################################################################################### +################################################################################################### + +proc ad_cpu_interconnect {p_address p_name} { + + global sys_zynq + global sys_addr_cntrl_space + global sys_cpu_interconnect_index + + set i_str "M$sys_cpu_interconnect_index" + if {$sys_cpu_interconnect_index < 10} { + set i_str "M0$sys_cpu_interconnect_index" + } + + if {($sys_cpu_interconnect_index == 0) && ($sys_zynq == 1)} { + ad_connect sys_cpu_clk sys_ps7/M_AXI_GP0_ACLK + ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK + ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK + ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN + ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN + ad_connect axi_cpu_interconnect/S00_AXI sys_ps7/M_AXI_GP0 + } + + if {($sys_cpu_interconnect_index == 0) && ($sys_zynq == 0)} { + ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK + ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK + ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN + ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN + ad_connect axi_cpu_interconnect/S00_AXI sys_mb/M_AXI_DP + } + + set sys_cpu_interconnect_index [expr $sys_cpu_interconnect_index + 1] + set p_intf [filter [get_bd_intf_pins -of_objects [get_bd_cells $p_name]] \ + -regexp "MODE == Slave && VLNV == xilinx.com:interface:aximm_rtl:1.0"] + set p_intf_name [lrange [split $p_intf "/"] end end] + set p_intf_clock [filter [get_bd_pins -quiet -of_objects [get_bd_cells $p_name]] \ + -regexp "CONFIG.ASSOCIATED_BUSIF == ${p_intf_name}"] + set p_intf_reset [get_property CONFIG.ASSOCIATED_RESET [get_bd_pins ${p_intf_clock}]] + + set_property CONFIG.NUM_MI $sys_cpu_interconnect_index [get_bd_cells axi_cpu_interconnect] + + ad_connect sys_cpu_clk axi_cpu_interconnect/${i_str}_ACLK + ad_connect sys_cpu_clk ${p_intf_clock} + ad_connect sys_cpu_resetn axi_cpu_interconnect/${i_str}_ARESETN + ad_connect sys_cpu_resetn ${p_name}/${p_intf_reset} + ad_connect axi_cpu_interconnect/${i_str}_AXI ${p_intf} + + set p_seg [get_bd_addr_segs -of_objects [get_bd_cells $p_name]] + set p_index 0 + foreach p_seg_name $p_seg { + if {$p_index == 0} { + set p_seg_range [get_property range $p_seg_name] + create_bd_addr_seg -range $p_seg_range \ + -offset $p_address $sys_addr_cntrl_space \ + $p_seg_name "SEG_data_${p_name}" + } else { + assign_bd_address $p_seg_name + } + incr p_index + } } ################################################################################################### @@ -130,89 +254,3 @@ proc ad_cpu_interrupt_update {} { ################################################################################################### ################################################################################################### -proc ad_cpu_interconnect {p_address p_name} { - - global sys_zynq - global sys_addr_cntrl_space - global sys_cpu_interconnect_index - - set i_str "M$sys_cpu_interconnect_index" - if {$sys_cpu_interconnect_index < 10} { - set i_str "M0$sys_cpu_interconnect_index" - } - - set m_clk_source [filter [get_bd_pins -of_objects [get_bd_nets sys_cpu_clk]] -regexp "DIR == O"] - set m_reset_source [filter [get_bd_pins -of_objects [get_bd_nets sys_cpu_resetn]] -regexp "DIR == O"] - - if {($sys_cpu_interconnect_index == 0) && ($sys_zynq == 1)} { - - connect_bd_net -net sys_cpu_clk \ - [get_bd_pins sys_ps7/M_AXI_GP0_ACLK] \ - [get_bd_pins axi_cpu_interconnect/ACLK] \ - [get_bd_pins axi_cpu_interconnect/S00_ACLK] \ - $m_clk_source - - connect_bd_net -net sys_cpu_resetn \ - [get_bd_pins axi_cpu_interconnect/ARESETN] \ - [get_bd_pins axi_cpu_interconnect/S00_ARESETN] \ - $m_reset_source - - connect_bd_intf_net -intf_net sys_ps7_axi \ - [get_bd_intf_pins axi_cpu_interconnect/S00_AXI] \ - [get_bd_intf_pins sys_ps7/M_AXI_GP0] - - } - - if {($sys_cpu_interconnect_index == 0) && ($sys_zynq == 0)} { - - connect_bd_net -net sys_cpu_clk \ - [get_bd_pins sys_ps7/M_AXI_GP0_ACLK] \ - [get_bd_pins axi_cpu_interconnect/ACLK] \ - [get_bd_pins axi_cpu_interconnect/S00_ACLK] \ - $m_clk_source - - connect_bd_net -net sys_cpu_resetn \ - [get_bd_pins axi_cpu_interconnect/ARESETN] \ - [get_bd_pins axi_cpu_interconnect/S00_ARESETN] \ - $m_reset_source - - connect_bd_intf_net -intf_net sys_ps7_axi \ - [get_bd_intf_pins axi_cpu_interconnect/S00_AXI] \ - [get_bd_intf_pins sys_ps7/M_AXI_GP0] - - } - - set sys_cpu_interconnect_index [expr $sys_cpu_interconnect_index + 1] - set p_seg [get_bd_addr_segs -of_objects [get_bd_cells $p_name]] - set p_seg_range [get_property range $p_seg] - set p_seg_fields [split $p_seg "/"] - - lassign $p_seg_fields no_use p_seg_name p_seg_intf p_seg_base - - set_property CONFIG.NUM_MI $sys_cpu_interconnect_index [get_bd_cells axi_cpu_interconnect] - - set p_clock [filter [get_bd_pins -quiet -of_objects [get_bd_cells $p_name]] \ - -regexp "CONFIG.ASSOCIATED_BUSIF == ${p_seg_intf}"] - set p_reset [get_property CONFIG.ASSOCIATED_RESET [get_bd_pins ${p_clock}]] - - connect_bd_net -net sys_cpu_clk \ - [get_bd_pins "axi_cpu_interconnect/${i_str}_ACLK"] \ - [get_bd_pins ${p_clock}] \ - $m_clk_source - - connect_bd_net -net sys_cpu_resetn \ - [get_bd_pins "axi_cpu_interconnect/${i_str}_ARESETN"] \ - [get_bd_pins ${p_name}/${p_reset}] \ - $m_reset_source - - connect_bd_intf_net -intf_net "${p_name}_axi_lite" \ - [get_bd_intf_pins "axi_cpu_interconnect/${i_str}_AXI"] \ - [get_bd_intf_pins ${p_seg_name}/${p_seg_intf}] - - create_bd_addr_seg -range $p_seg_range \ - -offset $p_address $sys_addr_cntrl_space \ - $p_seg "SEG_data_${p_name}" -} - -################################################################################################### -################################################################################################### diff --git a/projects/scripts/adi_project.tcl b/projects/scripts/adi_project.tcl index 545bc94b1..b24abbb2f 100644 --- a/projects/scripts/adi_project.tcl +++ b/projects/scripts/adi_project.tcl @@ -94,6 +94,7 @@ proc adi_project_create {project_name} { update_ip_catalog set_msg_config -id {BD 41-1348} -new_severity info + set_msg_config -id {BD 41-1343} -new_severity info set_msg_config -id {BD 41-1306} -new_severity info set_msg_config -id {IP_Flow 19-1687} -new_severity info set_msg_config -id {filemgmt 20-1763} -new_severity info @@ -178,11 +179,11 @@ proc adi_project_run {project_name} { #get_property STATS.TNS [get_runs impl_1] #get_property STATS.TPWS [get_runs impl_1] + export_hardware [get_files $project_system_dir/system.bd] [get_runs impl_1] -bitstream + if [expr [get_property SLACK [get_timing_paths]] < 0] { puts "ERROR: Timing Constraints NOT met." use_this_invalid_command_to_crash } - - export_hardware [get_files $project_system_dir/system.bd] [get_runs impl_1] -bitstream }