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common/vcu118: Balance clocks 

Minimize skew on synchronous CDC timing paths between clocks originating
from the same MMCM source. (sys_mem_clk and sys_cpu_clk)
This is required mostly by the smart interconnect.
The CLOCK_DELAY_GROUP property must be applied directly to the output net of BUFGs.
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Laszlo Nagy 2019-09-09 12:41:42 +01:00 committed by Laszlo Nagy
parent cfc8ff51e1
commit b7d48b8c74
1 changed files with 13 additions and 0 deletions
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projects/common/vcu118/vcu118_system_constr.xdc
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@ -57,3 +57,16 @@ set_property -dict {PACKAGE_PIN AL24 IOSTANDARD LVCMOS18 DRIVE 8 SLEW SLOW}
create_generated_clock -name spi_clk \
-source [get_pins i_system_wrapper/system_i/axi_spi/ext_spi_clk] \
-divide_by 2 [get_pins i_system_wrapper/system_i/axi_spi/sck_o]
# Balance clocks
#
# Minimize skew on synchronous CDC timing paths between clocks originating
# from the same MMCM source. (sys_mem_clk and sys_cpu_clk)
# This is required mostly by the smart interconnect.
# Property must be applied directly to the output net of BUFGs.
set_property CLOCK_DELAY_GROUP BALANCE_CLOCKS \
[list [get_nets [get_property PARENT [get_nets {i_system_wrapper/system_i/sys_cpu_clk}]]] \
[get_nets [get_property PARENT [get_nets {i_system_wrapper/system_i/sys_mem_clk}]]] \
]