altera- xcvr cores
Rejeesh Kutty
parent
a6e6b3f96e
commit
b7ea2efa87
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module avl_adxcfg (
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// reconfig sharing
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input rcfg_clk,
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input rcfg_reset_n,
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input rcfg_in_read_0,
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input rcfg_in_write_0,
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input [11:0] rcfg_in_address_0,
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input [31:0] rcfg_in_writedata_0,
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output [31:0] rcfg_in_readata_0,
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output rcfg_in_waitrequest_0,
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output rcfg_out_read_0,
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output rcfg_out_write_0,
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output [11:0] rcfg_out_address_0,
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output [31:0] rcfg_out_writedata_0,
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input [31:0] rcfg_out_readata_0,
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input rcfg_out_waitrequest_0,
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input rcfg_in_read_1,
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input rcfg_in_write_1,
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input [11:0] rcfg_in_address_1,
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input [31:0] rcfg_in_writedata_1,
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output [31:0] rcfg_in_readata_1,
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output rcfg_in_waitrequest_1,
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output rcfg_out_read_1,
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output rcfg_out_write_1,
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output [11:0] rcfg_out_address_1,
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output [31:0] rcfg_out_writedata_1,
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input [31:0] rcfg_out_readata_1,
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input rcfg_out_waitrequest_1,
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input rcfg_in_read_2,
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input rcfg_in_write_2,
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input [11:0] rcfg_in_address_2,
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input [31:0] rcfg_in_writedata_2,
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output [31:0] rcfg_in_readata_2,
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output rcfg_in_waitrequest_2,
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output rcfg_out_read_2,
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output rcfg_out_write_2,
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output [11:0] rcfg_out_address_2,
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output [31:0] rcfg_out_writedata_2,
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input [31:0] rcfg_out_readata_2,
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input rcfg_out_waitrequest_2,
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input rcfg_in_read_3,
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input rcfg_in_write_3,
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input [11:0] rcfg_in_address_3,
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input [31:0] rcfg_in_writedata_3,
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output [31:0] rcfg_in_readata_3,
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output rcfg_in_waitrequest_3,
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output rcfg_out_read_3,
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output rcfg_out_write_3,
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output [11:0] rcfg_out_address_3,
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output [31:0] rcfg_out_writedata_3,
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input [31:0] rcfg_out_readata_3,
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input rcfg_out_waitrequest_3,
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input rcfg_in_read_4,
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input rcfg_in_write_4,
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input [11:0] rcfg_in_address_4,
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input [31:0] rcfg_in_writedata_4,
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output [31:0] rcfg_in_readata_4,
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output rcfg_in_waitrequest_4,
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output rcfg_out_read_4,
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output rcfg_out_write_4,
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output [11:0] rcfg_out_address_4,
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output [31:0] rcfg_out_writedata_4,
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input [31:0] rcfg_out_readata_4,
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input rcfg_out_waitrequest_4,
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input rcfg_in_read_5,
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input rcfg_in_write_5,
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input [11:0] rcfg_in_address_5,
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input [31:0] rcfg_in_writedata_5,
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output [31:0] rcfg_in_readata_5,
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output rcfg_in_waitrequest_5,
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output rcfg_out_read_5,
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output rcfg_out_write_5,
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output [11:0] rcfg_out_address_5,
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output [31:0] rcfg_out_writedata_5,
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input [31:0] rcfg_out_readata_5,
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input rcfg_out_waitrequest_5,
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input rcfg_in_read_6,
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input rcfg_in_write_6,
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input [11:0] rcfg_in_address_6,
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input [31:0] rcfg_in_writedata_6,
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output [31:0] rcfg_in_readata_6,
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output rcfg_in_waitrequest_6,
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output rcfg_out_read_6,
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output rcfg_out_write_6,
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output [11:0] rcfg_out_address_6,
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output [31:0] rcfg_out_writedata_6,
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input [31:0] rcfg_out_readata_6,
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input rcfg_out_waitrequest_6,
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input rcfg_in_read_7,
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input rcfg_in_write_7,
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input [11:0] rcfg_in_address_7,
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input [31:0] rcfg_in_writedata_7,
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output [31:0] rcfg_in_readata_7,
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output rcfg_in_waitrequest_7,
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output rcfg_out_read_7,
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output rcfg_out_write_7,
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output [11:0] rcfg_out_address_7,
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output [31:0] rcfg_out_writedata_7,
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input [31:0] rcfg_out_readata_7,
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input rcfg_out_waitrequest_7);
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// internal registers
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reg [11:0] rcfg_out_address = 'd0;
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reg [31:0] rcfg_out_writedata = 'd0;
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reg rcfg_out_iread_0 = 'd0;
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reg rcfg_out_iwrite_0 = 'd0;
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reg [31:0] rcfg_in_ireadata_0 = 'd0;
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reg rcfg_in_iwaitrequest_0 = 'd0;
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reg rcfg_out_iread_1 = 'd0;
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reg rcfg_out_iwrite_1 = 'd0;
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reg [31:0] rcfg_in_ireadata_1 = 'd0;
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reg rcfg_in_iwaitrequest_1 = 'd0;
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reg rcfg_out_iread_2 = 'd0;
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reg rcfg_out_iwrite_2 = 'd0;
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reg [31:0] rcfg_in_ireadata_2 = 'd0;
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reg rcfg_in_iwaitrequest_2 = 'd0;
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reg rcfg_out_iread_3 = 'd0;
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reg rcfg_out_iwrite_3 = 'd0;
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reg [31:0] rcfg_in_ireadata_3 = 'd0;
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reg rcfg_in_iwaitrequest_3 = 'd0;
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reg rcfg_out_iread_4 = 'd0;
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reg rcfg_out_iwrite_4 = 'd0;
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reg [31:0] rcfg_in_ireadata_4 = 'd0;
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reg rcfg_in_iwaitrequest_4 = 'd0;
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reg rcfg_out_iread_5 = 'd0;
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reg rcfg_out_iwrite_5 = 'd0;
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reg [31:0] rcfg_in_ireadata_5 = 'd0;
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reg rcfg_in_iwaitrequest_5 = 'd0;
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reg rcfg_out_iread_6 = 'd0;
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reg rcfg_out_iwrite_6 = 'd0;
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reg [31:0] rcfg_in_ireadata_6 = 'd0;
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reg rcfg_in_iwaitrequest_6 = 'd0;
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reg rcfg_out_iread_7 = 'd0;
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reg rcfg_out_iwrite_7 = 'd0;
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reg [31:0] rcfg_in_ireadata_7 = 'd0;
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reg rcfg_in_iwaitrequest_7 = 'd0;
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reg [ 3:0] rcfg_select = 'd0;
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// internal signals
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wire recfg_in_req_0_s;
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wire recfg_in_req_1_s;
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wire recfg_in_req_2_s;
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wire recfg_in_req_3_s;
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wire recfg_in_req_4_s;
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wire recfg_in_req_5_s;
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wire recfg_in_req_6_s;
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wire recfg_in_req_7_s;
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// xcvr sharing requires same bus with ONLY different write/read signals
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assign rcfg_out_address_0 <= rcfg_out_address;
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assign rcfg_out_writedata_0 <= rcfg_out_writedata;
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assign rcfg_out_address_1 <= rcfg_out_address;
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assign rcfg_out_writedata_1 <= rcfg_out_writedata;
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assign rcfg_out_address_2 <= rcfg_out_address;
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assign rcfg_out_writedata_2 <= rcfg_out_writedata;
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assign rcfg_out_address_3 <= rcfg_out_address;
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assign rcfg_out_writedata_3 <= rcfg_out_writedata;
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assign rcfg_out_address_4 <= rcfg_out_address;
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assign rcfg_out_writedata_4 <= rcfg_out_writedata;
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assign rcfg_out_address_5 <= rcfg_out_address;
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assign rcfg_out_writedata_5 <= rcfg_out_writedata;
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assign rcfg_out_address_6 <= rcfg_out_address;
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assign rcfg_out_writedata_6 <= rcfg_out_writedata;
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assign rcfg_out_address_7 <= rcfg_out_address;
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assign rcfg_out_writedata_7 <= rcfg_out_writedata;
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always @(negedge rcfg_reset_n or posedge rcfg_clk) begin
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if (rcfg_reset_n == 0) begin
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rcfg_out_address <= 12'd0;
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rcfg_out_writedata <= 32'd0;
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end else begin
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case (rcfg_select)
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4'h8: begin
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rcfg_out_address <= rcfg_in_address_0;
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rcfg_out_writedata <= rcfg_in_writedata_0;
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end
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4'h9: begin
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rcfg_out_address <= rcfg_in_address_1;
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rcfg_out_writedata <= rcfg_in_writedata_1;
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end
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4'ha: begin
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rcfg_out_address <= rcfg_in_address_2;
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rcfg_out_writedata <= rcfg_in_writedata_2;
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end
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4'hb: begin
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rcfg_out_address <= rcfg_in_address_3;
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rcfg_out_writedata <= rcfg_in_writedata_3;
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end
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4'hc: begin
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rcfg_out_address <= rcfg_in_address_4;
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rcfg_out_writedata <= rcfg_in_writedata_4;
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end
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4'hd: begin
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rcfg_out_address <= rcfg_in_address_5;
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rcfg_out_writedata <= rcfg_in_writedata_5;
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end
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4'he: begin
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rcfg_out_address <= rcfg_in_address_6;
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rcfg_out_writedata <= rcfg_in_writedata_6;
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end
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4'hf: begin
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rcfg_out_address <= rcfg_in_address_7;
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rcfg_out_writedata <= rcfg_in_writedata_7;
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end
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default: begin
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rcfg_out_address <= 12'd0;
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rcfg_out_writedata <= 32'd0;
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end
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endcase
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end
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end
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assign rcfg_out_read_0 = rcfg_out_iread_0;
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assign rcfg_out_write_0 = rcfg_out_iwrite_0;
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assign rcfg_in_readata_0 = rcfg_in_ireadata_0;
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assign rcfg_in_waitrequest_0 = rcfg_in_iwaitrequest_0;
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assign rcfg_out_read_1 = rcfg_out_iread_1;
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assign rcfg_out_write_1 = rcfg_out_iwrite_1;
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assign rcfg_in_readata_1 = rcfg_in_ireadata_1;
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assign rcfg_in_waitrequest_1 = rcfg_in_iwaitrequest_1;
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assign rcfg_out_read_2 = rcfg_out_iread_2;
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assign rcfg_out_write_2 = rcfg_out_iwrite_2;
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assign rcfg_in_readata_2 = rcfg_in_ireadata_2;
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assign rcfg_in_waitrequest_2 = rcfg_in_iwaitrequest_2;
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assign rcfg_out_read_3 = rcfg_out_iread_3;
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assign rcfg_out_write_3 = rcfg_out_iwrite_3;
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assign rcfg_in_readata_3 = rcfg_in_ireadata_3;
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assign rcfg_in_waitrequest_3 = rcfg_in_iwaitrequest_3;
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assign rcfg_out_read_4 = rcfg_out_iread_4;
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assign rcfg_out_write_4 = rcfg_out_iwrite_4;
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assign rcfg_in_readata_4 = rcfg_in_ireadata_4;
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assign rcfg_in_waitrequest_4 = rcfg_in_iwaitrequest_4;
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assign rcfg_out_read_5 = rcfg_out_iread_5;
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assign rcfg_out_write_5 = rcfg_out_iwrite_5;
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assign rcfg_in_readata_5 = rcfg_in_ireadata_5;
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assign rcfg_in_waitrequest_5 = rcfg_in_iwaitrequest_5;
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assign rcfg_out_read_6 = rcfg_out_iread_6;
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assign rcfg_out_write_6 = rcfg_out_iwrite_6;
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assign rcfg_in_readata_6 = rcfg_in_ireadata_6;
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assign rcfg_in_waitrequest_6 = rcfg_in_iwaitrequest_6;
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assign rcfg_out_read_7 = rcfg_out_iread_7;
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assign rcfg_out_write_7 = rcfg_out_iwrite_7;
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assign rcfg_in_readata_7 = rcfg_in_ireadata_7;
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assign rcfg_in_waitrequest_7 = rcfg_in_iwaitrequest_7;
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always @(negedge rcfg_reset_n or posedge rcfg_clk) begin
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if (rcfg_reset_n == 0) begin
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rcfg_out_iread_0 <= 1'd0;
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rcfg_out_iwrite_0 <= 1'd0;
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rcfg_in_ireaddata_0 <= 32'd0;
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rcfg_in_iwaitrequest_0 <= 1'd1;
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rcfg_out_iread_1 <= 1'd0;
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rcfg_out_iwrite_1 <= 1'd0;
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rcfg_in_ireaddata_1 <= 32'd0;
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rcfg_in_iwaitrequest_1 <= 1'd1;
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rcfg_out_iread_2 <= 1'd0;
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rcfg_out_iwrite_2 <= 1'd0;
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rcfg_in_ireaddata_2 <= 32'd0;
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rcfg_in_iwaitrequest_2 <= 1'd1;
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rcfg_out_iread_3 <= 1'd0;
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rcfg_out_iwrite_3 <= 1'd0;
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rcfg_in_ireaddata_3 <= 32'd0;
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rcfg_in_iwaitrequest_3 <= 1'd1;
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rcfg_out_iread_4 <= 1'd0;
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rcfg_out_iwrite_4 <= 1'd0;
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rcfg_in_ireaddata_4 <= 32'd0;
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rcfg_in_iwaitrequest_4 <= 1'd1;
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rcfg_out_iread_5 <= 1'd0;
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rcfg_out_iwrite_5 <= 1'd0;
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rcfg_in_ireaddata_5 <= 32'd0;
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rcfg_in_iwaitrequest_5 <= 1'd1;
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rcfg_out_iread_6 <= 1'd0;
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rcfg_out_iwrite_6 <= 1'd0;
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rcfg_in_ireaddata_6 <= 32'd0;
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rcfg_in_iwaitrequest_6 <= 1'd1;
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rcfg_out_iread_7 <= 1'd0;
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rcfg_out_iwrite_7 <= 1'd0;
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rcfg_in_ireaddata_7 <= 32'd0;
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rcfg_in_iwaitrequest_7 <= 1'd1;
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end else begin
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if (rcfg_select == 4'h8) begin
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rcfg_out_iread_0 <= rcfg_in_read_0;
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rcfg_out_iwrite_0 <= rcfg_in_write_0;
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rcfg_in_ireaddata_0 <= rcfg_out_readdata_0;
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rcfg_in_iwaitrequest_0 <= rcfg_out_waitrequest_0 | ~rcfg_in_req_0_s;
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end else begin
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rcfg_out_iread_0 <= 1'd0;
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rcfg_out_iwrite_0 <= 1'd0;
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rcfg_in_ireaddata_0 <= 32'd0;
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rcfg_in_iwaitrequest_0 <= 1'd1;
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end
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if (rcfg_select == 4'h9) begin
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rcfg_out_iread_1 <= rcfg_in_read_1;
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rcfg_out_iwrite_1 <= rcfg_in_write_1;
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rcfg_in_ireaddata_1 <= rcfg_out_readdata_1;
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rcfg_in_iwaitrequest_1 <= rcfg_out_waitrequest_1 | ~rcfg_in_req_1_s;
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end else begin
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rcfg_out_iread_1 <= 1'd0;
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rcfg_out_iwrite_1 <= 1'd0;
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rcfg_in_ireaddata_1 <= 32'd0;
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rcfg_in_iwaitrequest_1 <= 1'd1;
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end
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if (rcfg_select == 4'ha) begin
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rcfg_out_iread_2 <= rcfg_in_read_2;
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rcfg_out_iwrite_2 <= rcfg_in_write_2;
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rcfg_in_ireaddata_2 <= rcfg_out_readdata_2;
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rcfg_in_iwaitrequest_2 <= rcfg_out_waitrequest_2 | ~rcfg_in_req_2_s;
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end else begin
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rcfg_out_iread_2 <= 1'd0;
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rcfg_out_iwrite_2 <= 1'd0;
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rcfg_in_ireaddata_2 <= 32'd0;
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rcfg_in_iwaitrequest_2 <= 1'd1;
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end
|
||||
if (rcfg_select == 4'hb) begin
|
||||
rcfg_out_iread_3 <= rcfg_in_read_3;
|
||||
rcfg_out_iwrite_3 <= rcfg_in_write_3;
|
||||
rcfg_in_ireaddata_3 <= rcfg_out_readdata_3;
|
||||
rcfg_in_iwaitrequest_3 <= rcfg_out_waitrequest_3 | ~rcfg_in_req_3_s;
|
||||
end else begin
|
||||
rcfg_out_iread_3 <= 1'd0;
|
||||
rcfg_out_iwrite_3 <= 1'd0;
|
||||
rcfg_in_ireaddata_3 <= 32'd0;
|
||||
rcfg_in_iwaitrequest_3 <= 1'd1;
|
||||
end
|
||||
if (rcfg_select == 4'hc) begin
|
||||
rcfg_out_iread_4 <= rcfg_in_read_4;
|
||||
rcfg_out_iwrite_4 <= rcfg_in_write_4;
|
||||
rcfg_in_ireaddata_4 <= rcfg_out_readdata_4;
|
||||
rcfg_in_iwaitrequest_4 <= rcfg_out_waitrequest_4 | ~rcfg_in_req_4_s;
|
||||
end else begin
|
||||
rcfg_out_iread_4 <= 1'd0;
|
||||
rcfg_out_iwrite_4 <= 1'd0;
|
||||
rcfg_in_ireaddata_4 <= 32'd0;
|
||||
rcfg_in_iwaitrequest_4 <= 1'd1;
|
||||
end
|
||||
if (rcfg_select == 4'hd) begin
|
||||
rcfg_out_iread_5 <= rcfg_in_read_5;
|
||||
rcfg_out_iwrite_5 <= rcfg_in_write_5;
|
||||
rcfg_in_ireaddata_5 <= rcfg_out_readdata_5;
|
||||
rcfg_in_iwaitrequest_5 <= rcfg_out_waitrequest_5 | ~rcfg_in_req_5_s;
|
||||
end else begin
|
||||
rcfg_out_iread_5 <= 1'd0;
|
||||
rcfg_out_iwrite_5 <= 1'd0;
|
||||
rcfg_in_ireaddata_5 <= 32'd0;
|
||||
rcfg_in_iwaitrequest_5 <= 1'd1;
|
||||
end
|
||||
if (rcfg_select == 4'he) begin
|
||||
rcfg_out_iread_6 <= rcfg_in_read_6;
|
||||
rcfg_out_iwrite_6 <= rcfg_in_write_6;
|
||||
rcfg_in_ireaddata_6 <= rcfg_out_readdata_6;
|
||||
rcfg_in_iwaitrequest_6 <= rcfg_out_waitrequest_6 | ~rcfg_in_req_6_s;
|
||||
end else begin
|
||||
rcfg_out_iread_6 <= 1'd0;
|
||||
rcfg_out_iwrite_6 <= 1'd0;
|
||||
rcfg_in_ireaddata_6 <= 32'd0;
|
||||
rcfg_in_iwaitrequest_6 <= 1'd1;
|
||||
end
|
||||
if (rcfg_select == 4'hf) begin
|
||||
rcfg_out_iread_7 <= rcfg_in_read_7;
|
||||
rcfg_out_iwrite_7 <= rcfg_in_write_7;
|
||||
rcfg_in_ireaddata_7 <= rcfg_out_readdata_7;
|
||||
rcfg_in_iwaitrequest_7 <= rcfg_out_waitrequest_7 | ~rcfg_in_req_7_s;
|
||||
end else begin
|
||||
rcfg_out_iread_7 <= 1'd0;
|
||||
rcfg_out_iwrite_7 <= 1'd0;
|
||||
rcfg_in_ireaddata_7 <= 32'd0;
|
||||
rcfg_in_iwaitrequest_7 <= 1'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign rcfg_in_req_0_s = rcfg_in_read_0 | rcfg_in_write_0;
|
||||
assign rcfg_in_req_1_s = rcfg_in_read_1 | rcfg_in_write_1;
|
||||
assign rcfg_in_req_2_s = rcfg_in_read_2 | rcfg_in_write_2;
|
||||
assign rcfg_in_req_3_s = rcfg_in_read_3 | rcfg_in_write_3;
|
||||
assign rcfg_in_req_4_s = rcfg_in_read_4 | rcfg_in_write_4;
|
||||
assign rcfg_in_req_5_s = rcfg_in_read_5 | rcfg_in_write_5;
|
||||
assign rcfg_in_req_6_s = rcfg_in_read_6 | rcfg_in_write_6;
|
||||
assign rcfg_in_req_7_s = rcfg_in_read_7 | rcfg_in_write_7;
|
||||
|
||||
always @(negedge rcfg_reset_n or posedge rcfg_clk) begin
|
||||
if (rcfg_reset_n == 0) begin
|
||||
rcfg_select <= 4'h0;
|
||||
end else begin
|
||||
case (rcfg_select)
|
||||
4'h8: begin
|
||||
if (rcfg_in_req_1_s == 1'b1) begin
|
||||
rcfg_select <= 4'h9;
|
||||
end else if (rcfg_in_req_2_s == 1'b1) begin
|
||||
rcfg_select <= 4'ha;
|
||||
end else if (rcfg_in_req_3_s == 1'b1) begin
|
||||
rcfg_select <= 4'hb;
|
||||
end else if (rcfg_in_req_4_s == 1'b1) begin
|
||||
rcfg_select <= 4'hc;
|
||||
end else if (rcfg_in_req_5_s == 1'b1) begin
|
||||
rcfg_select <= 4'hd;
|
||||
end else if (rcfg_in_req_6_s == 1'b1) begin
|
||||
rcfg_select <= 4'he;
|
||||
end else if (rcfg_in_req_7_s == 1'b1) begin
|
||||
rcfg_select <= 4'hf;
|
||||
end else if (rcfg_in_req_0_s == 1'b1) begin
|
||||
rcfg_select <= 4'h8;
|
||||
end else begin
|
||||
rcfg_select <= 4'h0;
|
||||
end
|
||||
end
|
||||
4'h9: begin
|
||||
if (rcfg_in_req_2_s == 1'b1) begin
|
||||
rcfg_select <= 4'ha;
|
||||
end else if (rcfg_in_req_3_s == 1'b1) begin
|
||||
rcfg_select <= 4'hb;
|
||||
end else if (rcfg_in_req_4_s == 1'b1) begin
|
||||
rcfg_select <= 4'hc;
|
||||
end else if (rcfg_in_req_5_s == 1'b1) begin
|
||||
rcfg_select <= 4'hd;
|
||||
end else if (rcfg_in_req_6_s == 1'b1) begin
|
||||
rcfg_select <= 4'he;
|
||||
end else if (rcfg_in_req_7_s == 1'b1) begin
|
||||
rcfg_select <= 4'hf;
|
||||
end else if (rcfg_in_req_0_s == 1'b1) begin
|
||||
rcfg_select <= 4'h8;
|
||||
end else if (rcfg_in_req_1_s == 1'b1) begin
|
||||
rcfg_select <= 4'h9;
|
||||
end else begin
|
||||
rcfg_select <= 4'h0;
|
||||
end
|
||||
end
|
||||
4'ha: begin
|
||||
if (rcfg_in_req_3_s == 1'b1) begin
|
||||
rcfg_select <= 4'hb;
|
||||
end else if (rcfg_in_req_4_s == 1'b1) begin
|
||||
rcfg_select <= 4'hc;
|
||||
end else if (rcfg_in_req_5_s == 1'b1) begin
|
||||
rcfg_select <= 4'hd;
|
||||
end else if (rcfg_in_req_6_s == 1'b1) begin
|
||||
rcfg_select <= 4'he;
|
||||
end else if (rcfg_in_req_7_s == 1'b1) begin
|
||||
rcfg_select <= 4'hf;
|
||||
end else if (rcfg_in_req_0_s == 1'b1) begin
|
||||
rcfg_select <= 4'h8;
|
||||
end else if (rcfg_in_req_1_s == 1'b1) begin
|
||||
rcfg_select <= 4'h9;
|
||||
end else if (rcfg_in_req_2_s == 1'b1) begin
|
||||
rcfg_select <= 4'ha;
|
||||
end else begin
|
||||
rcfg_select <= 4'h0;
|
||||
end
|
||||
end
|
||||
4'hb: begin
|
||||
if (rcfg_in_req_4_s == 1'b1) begin
|
||||
rcfg_select <= 4'hc;
|
||||
end else if (rcfg_in_req_5_s == 1'b1) begin
|
||||
rcfg_select <= 4'hd;
|
||||
end else if (rcfg_in_req_6_s == 1'b1) begin
|
||||
rcfg_select <= 4'he;
|
||||
end else if (rcfg_in_req_7_s == 1'b1) begin
|
||||
rcfg_select <= 4'hf;
|
||||
end else if (rcfg_in_req_0_s == 1'b1) begin
|
||||
rcfg_select <= 4'h8;
|
||||
end else if (rcfg_in_req_1_s == 1'b1) begin
|
||||
rcfg_select <= 4'h9;
|
||||
end else if (rcfg_in_req_2_s == 1'b1) begin
|
||||
rcfg_select <= 4'ha;
|
||||
end else if (rcfg_in_req_3_s == 1'b1) begin
|
||||
rcfg_select <= 4'hb;
|
||||
end else begin
|
||||
rcfg_select <= 4'h0;
|
||||
end
|
||||
end
|
||||
4'hc: begin
|
||||
if (rcfg_in_req_5_s == 1'b1) begin
|
||||
rcfg_select <= 4'hd;
|
||||
end else if (rcfg_in_req_6_s == 1'b1) begin
|
||||
rcfg_select <= 4'he;
|
||||
end else if (rcfg_in_req_7_s == 1'b1) begin
|
||||
rcfg_select <= 4'hf;
|
||||
end else if (rcfg_in_req_0_s == 1'b1) begin
|
||||
rcfg_select <= 4'h8;
|
||||
end else if (rcfg_in_req_1_s == 1'b1) begin
|
||||
rcfg_select <= 4'h9;
|
||||
end else if (rcfg_in_req_2_s == 1'b1) begin
|
||||
rcfg_select <= 4'ha;
|
||||
end else if (rcfg_in_req_3_s == 1'b1) begin
|
||||
rcfg_select <= 4'hb;
|
||||
end else if (rcfg_in_req_4_s == 1'b1) begin
|
||||
rcfg_select <= 4'hc;
|
||||
end else begin
|
||||
rcfg_select <= 4'h0;
|
||||
end
|
||||
end
|
||||
4'hd: begin
|
||||
if (rcfg_in_req_6_s == 1'b1) begin
|
||||
rcfg_select <= 4'he;
|
||||
end else if (rcfg_in_req_7_s == 1'b1) begin
|
||||
rcfg_select <= 4'hf;
|
||||
end else if (rcfg_in_req_0_s == 1'b1) begin
|
||||
rcfg_select <= 4'h8;
|
||||
end else if (rcfg_in_req_1_s == 1'b1) begin
|
||||
rcfg_select <= 4'h9;
|
||||
end else if (rcfg_in_req_2_s == 1'b1) begin
|
||||
rcfg_select <= 4'ha;
|
||||
end else if (rcfg_in_req_3_s == 1'b1) begin
|
||||
rcfg_select <= 4'hb;
|
||||
end else if (rcfg_in_req_4_s == 1'b1) begin
|
||||
rcfg_select <= 4'hc;
|
||||
end else if (rcfg_in_req_5_s == 1'b1) begin
|
||||
rcfg_select <= 4'hd;
|
||||
end else begin
|
||||
rcfg_select <= 4'h0;
|
||||
end
|
||||
end
|
||||
4'he: begin
|
||||
if (rcfg_in_req_7_s == 1'b1) begin
|
||||
rcfg_select <= 4'hf;
|
||||
end else if (rcfg_in_req_0_s == 1'b1) begin
|
||||
rcfg_select <= 4'h8;
|
||||
end else if (rcfg_in_req_1_s == 1'b1) begin
|
||||
rcfg_select <= 4'h9;
|
||||
end else if (rcfg_in_req_2_s == 1'b1) begin
|
||||
rcfg_select <= 4'ha;
|
||||
end else if (rcfg_in_req_3_s == 1'b1) begin
|
||||
rcfg_select <= 4'hb;
|
||||
end else if (rcfg_in_req_4_s == 1'b1) begin
|
||||
rcfg_select <= 4'hc;
|
||||
end else if (rcfg_in_req_5_s == 1'b1) begin
|
||||
rcfg_select <= 4'hd;
|
||||
end else if (rcfg_in_req_6_s == 1'b1) begin
|
||||
rcfg_select <= 4'he;
|
||||
end else begin
|
||||
rcfg_select <= 4'h0;
|
||||
end
|
||||
end
|
||||
4'hf: begin
|
||||
if (rcfg_in_req_0_s == 1'b1) begin
|
||||
rcfg_select <= 4'h8;
|
||||
end else if (rcfg_in_req_1_s == 1'b1) begin
|
||||
rcfg_select <= 4'h9;
|
||||
end else if (rcfg_in_req_2_s == 1'b1) begin
|
||||
rcfg_select <= 4'ha;
|
||||
end else if (rcfg_in_req_3_s == 1'b1) begin
|
||||
rcfg_select <= 4'hb;
|
||||
end else if (rcfg_in_req_4_s == 1'b1) begin
|
||||
rcfg_select <= 4'hc;
|
||||
end else if (rcfg_in_req_5_s == 1'b1) begin
|
||||
rcfg_select <= 4'hd;
|
||||
end else if (rcfg_in_req_6_s == 1'b1) begin
|
||||
rcfg_select <= 4'he;
|
||||
end else if (rcfg_in_req_7_s == 1'b1) begin
|
||||
rcfg_select <= 4'hf;
|
||||
end else begin
|
||||
rcfg_select <= 4'h0;
|
||||
end
|
||||
end
|
||||
default: begin
|
||||
if (rcfg_in_req_0_s == 1'b1) begin
|
||||
rcfg_select <= 4'h8;
|
||||
end else if (rcfg_in_req_1_s == 1'b1) begin
|
||||
rcfg_select <= 4'h9;
|
||||
end else if (rcfg_in_req_2_s == 1'b1) begin
|
||||
rcfg_select <= 4'ha;
|
||||
end else if (rcfg_in_req_3_s == 1'b1) begin
|
||||
rcfg_select <= 4'hb;
|
||||
end else if (rcfg_in_req_4_s == 1'b1) begin
|
||||
rcfg_select <= 4'hc;
|
||||
end else if (rcfg_in_req_5_s == 1'b1) begin
|
||||
rcfg_select <= 4'hd;
|
||||
end else if (rcfg_in_req_6_s == 1'b1) begin
|
||||
rcfg_select <= 4'he;
|
||||
end else if (rcfg_in_req_7_s == 1'b1) begin
|
||||
rcfg_select <= 4'hf;
|
||||
end else begin
|
||||
rcfg_select <= 4'h0;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
|
||||
package require -exact qsys 14.0
|
||||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
|
||||
|
||||
set_module_property NAME axi_adxcvr
|
||||
set_module_property DESCRIPTION "AXI ADXCVR Interface"
|
||||
set_module_property VERSION 1.0
|
||||
set_module_property GROUP "Analog Devices"
|
||||
set_module_property DISPLAY_NAME axi_adxcvr
|
||||
|
||||
# files
|
||||
|
||||
add_fileset quartus_synth QUARTUS_SYNTH "" ""
|
||||
set_fileset_property quartus_synth TOP_LEVEL axi_adxcvr
|
||||
add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
|
||||
add_fileset_file axi_adxcvr_up.v VERILOG PATH axi_adxcvr_up.v
|
||||
add_fileset_file axi_adxcvr.v VERILOG PATH axi_adxcvr.v TOP_LEVEL_FILE
|
||||
|
||||
# parameters
|
||||
|
||||
add_parameter ID INTEGER 0
|
||||
set_parameter_property ID DISPLAY_NAME ID
|
||||
set_parameter_property ID TYPE INTEGER
|
||||
set_parameter_property ID UNITS None
|
||||
set_parameter_property ID HDL_PARAMETER true
|
||||
|
||||
add_parameter TX_OR_RX_N INTEGER 0
|
||||
set_parameter_property DEVICE_TYPE DISPLAY_NAME TX_OR_RX_N
|
||||
set_parameter_property DEVICE_TYPE TYPE INTEGER
|
||||
set_parameter_property DEVICE_TYPE UNITS None
|
||||
set_parameter_property DEVICE_TYPE HDL_PARAMETER true
|
||||
|
||||
# axi4 slave interface
|
||||
|
||||
add_interface s_axi_clock clock end
|
||||
add_interface_port s_axi_clock s_axi_aclk clk Input 1
|
||||
|
||||
add_interface s_axi_reset reset end
|
||||
set_interface_property s_axi_reset associatedClock s_axi_clock
|
||||
add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
|
||||
|
||||
add_interface s_axi axi4lite end
|
||||
set_interface_property s_axi associatedClock s_axi_clock
|
||||
set_interface_property s_axi associatedReset s_axi_reset
|
||||
add_interface_port s_axi s_axi_awvalid awvalid Input 1
|
||||
add_interface_port s_axi s_axi_awaddr awaddr Input 16
|
||||
add_interface_port s_axi s_axi_awprot awprot Input 3
|
||||
add_interface_port s_axi s_axi_awready awready Output 1
|
||||
add_interface_port s_axi s_axi_wvalid wvalid Input 1
|
||||
add_interface_port s_axi s_axi_wdata wdata Input 32
|
||||
add_interface_port s_axi s_axi_wstrb wstrb Input 4
|
||||
add_interface_port s_axi s_axi_wready wready Output 1
|
||||
add_interface_port s_axi s_axi_bvalid bvalid Output 1
|
||||
add_interface_port s_axi s_axi_bresp bresp Output 2
|
||||
add_interface_port s_axi s_axi_bready bready Input 1
|
||||
add_interface_port s_axi s_axi_arvalid arvalid Input 1
|
||||
add_interface_port s_axi s_axi_araddr araddr Input 16
|
||||
add_interface_port s_axi s_axi_arprot arprot Input 3
|
||||
add_interface_port s_axi s_axi_arready arready Output 1
|
||||
add_interface_port s_axi s_axi_rvalid rvalid Output 1
|
||||
add_interface_port s_axi s_axi_rresp rresp Output 2
|
||||
add_interface_port s_axi s_axi_rdata rdata Output 32
|
||||
add_interface_port s_axi s_axi_rready rready Input 1
|
||||
|
||||
# xcvr interface
|
||||
|
||||
add_interface if_xcvr conduit end
|
||||
add_interface_port if_xcvr up_rst up_rst Output 1
|
||||
add_interface_port if_xcvr up_ref_pll_locked up_ref_pll_locked Input 1
|
||||
add_interface_port if_xcvr up_pll_locked up_pll_locked Input 1
|
||||
add_interface_port if_xcvr up_ready up_ready Input 1
|
||||
|
||||
set_interface_property if_xcvr associatedClock s_axi_clock
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,299 @@
|
|||
|
||||
package require -exact qsys 14.0
|
||||
|
||||
set_module_property NAME avl_adxcvr
|
||||
set_module_property DESCRIPTION "Avalon Transceiver"
|
||||
set_module_property VERSION 1.0
|
||||
set_module_property GROUP "Analog Devices"
|
||||
set_module_property DISPLAY_NAME avl_adxcvr
|
||||
set_module_property COMPOSITION_CALLBACK p_avl_adxcvr
|
||||
|
||||
# parameters
|
||||
|
||||
add_parameter DEVICE_FAMILY STRING
|
||||
set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
|
||||
set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
|
||||
set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
|
||||
set_parameter_property DEVICE_FAMILY ENABLED false
|
||||
|
||||
add_parameter TX_OR_RX_N INTEGER 0
|
||||
set_parameter_property TX_OR_RX_N DISPLAY_NAME TX_OR_RX_N
|
||||
set_parameter_property TX_OR_RX_N TYPE INTEGER
|
||||
set_parameter_property TX_OR_RX_N UNITS None
|
||||
set_parameter_property TX_OR_RX_N HDL_PARAMETER false
|
||||
|
||||
add_parameter ID INTEGER 0
|
||||
set_parameter_property ID DISPLAY_NAME ID
|
||||
set_parameter_property ID TYPE INTEGER
|
||||
set_parameter_property ID UNITS None
|
||||
set_parameter_property ID HDL_PARAMETER false
|
||||
|
||||
add_parameter PCS_CONFIG STRING "JESD_PCS_CFG2"
|
||||
set_parameter_property PCS_CONFIG DISPLAY_NAME PCS_CONFIG
|
||||
set_parameter_property PCS_CONFIG TYPE STRING
|
||||
set_parameter_property PCS_CONFIG UNITS None
|
||||
set_parameter_property PCS_CONFIG HDL_PARAMETER false
|
||||
|
||||
add_parameter LANE_RATE FLOAT 10000
|
||||
set_parameter_property LANE_RATE DISPLAY_NAME LANE_RATE
|
||||
set_parameter_property LANE_RATE TYPE FLOAT
|
||||
set_parameter_property LANE_RATE UNITS None
|
||||
set_parameter_property LANE_RATE DISPLAY_UNITS "Mbps"
|
||||
set_parameter_property LANE_RATE HDL_PARAMETER false
|
||||
|
||||
add_parameter PLLCLK_FREQUENCY FLOAT 5000.0
|
||||
set_parameter_property PLLCLK_FREQUENCY DISPLAY_NAME PLLCLK_FREQUENCY
|
||||
set_parameter_property PLLCLK_FREQUENCY TYPE FLOAT
|
||||
set_parameter_property PLLCLK_FREQUENCY UNITS Megahertz
|
||||
set_parameter_property PLLCLK_FREQUENCY HDL_PARAMETER false
|
||||
|
||||
add_parameter REFCLK_FREQUENCY FLOAT 500.0
|
||||
set_parameter_property REFCLK_FREQUENCY DISPLAY_NAME REFCLK_FREQUENCY
|
||||
set_parameter_property REFCLK_FREQUENCY TYPE FLOAT
|
||||
set_parameter_property REFCLK_FREQUENCY UNITS Megahertz
|
||||
set_parameter_property REFCLK_FREQUENCY HDL_PARAMETER false
|
||||
|
||||
add_parameter CORECLK_FREQUENCY FLOAT 250.0
|
||||
set_parameter_property CORECLK_FREQUENCY DISPLAY_NAME CORECLK_FREQUENCY
|
||||
set_parameter_property CORECLK_FREQUENCY TYPE FLOAT
|
||||
set_parameter_property CORECLK_FREQUENCY UNITS Megahertz
|
||||
set_parameter_property CORECLK_FREQUENCY HDL_PARAMETER false
|
||||
|
||||
add_parameter NUM_OF_LANES INTEGER 4
|
||||
set_parameter_property NUM_OF_LANES DISPLAY_NAME NUM_OF_LANES
|
||||
set_parameter_property NUM_OF_LANES TYPE INTEGER
|
||||
set_parameter_property NUM_OF_LANES UNITS None
|
||||
set_parameter_property NUM_OF_LANES HDL_PARAMETER false
|
||||
|
||||
add_parameter NUM_OF_CONVS INTEGER 2
|
||||
set_parameter_property NUM_OF_CONVS DISPLAY_NAME NUM_OF_CONVS
|
||||
set_parameter_property NUM_OF_CONVS TYPE INTEGER
|
||||
set_parameter_property NUM_OF_CONVS UNITS None
|
||||
set_parameter_property NUM_OF_CONVS HDL_PARAMETER false
|
||||
|
||||
add_parameter FRM_BCNT INTEGER 1
|
||||
set_parameter_property FRM_BCNT DISPLAY_NAME FRM_BCNT
|
||||
set_parameter_property FRM_BCNT TYPE INTEGER
|
||||
set_parameter_property FRM_BCNT UNITS None
|
||||
set_parameter_property FRM_BCNT HDL_PARAMETER false
|
||||
|
||||
add_parameter FRM_SCNT INTEGER 1
|
||||
set_parameter_property FRM_SCNT DISPLAY_NAME FRM_SCNT
|
||||
set_parameter_property FRM_SCNT TYPE INTEGER
|
||||
set_parameter_property FRM_SCNT UNITS None
|
||||
set_parameter_property FRM_SCNT HDL_PARAMETER false
|
||||
|
||||
add_parameter MF_FCNT INTEGER 32
|
||||
set_parameter_property MF_FCNT DISPLAY_NAME MF_FCNT
|
||||
set_parameter_property MF_FCNT TYPE INTEGER
|
||||
set_parameter_property MF_FCNT UNITS None
|
||||
set_parameter_property MF_FCNT HDL_PARAMETER false
|
||||
|
||||
add_parameter HD INTEGER 1
|
||||
set_parameter_property HD DISPLAY_NAME HD
|
||||
set_parameter_property HD TYPE INTEGER
|
||||
set_parameter_property HD UNITS None
|
||||
set_parameter_property HD HDL_PARAMETER false
|
||||
|
||||
proc p_avl_adxcvr {} {
|
||||
|
||||
set m_id [get_parameter_value "ID"]
|
||||
set m_lane_rate [get_parameter_value "LANE_RATE"]
|
||||
set m_pcs_config [get_parameter_value "PCS_CONFIG"]
|
||||
set m_tx_or_rx_n [get_parameter_value "TX_OR_RX_N"]
|
||||
set m_num_of_lanes [get_parameter_value "NUM_OF_LANES"]
|
||||
set m_device_family [get_parameter_value "DEVICE_FAMILY"]
|
||||
set m_pllclk_frequency [get_parameter_value "PLLCLK_FREQUENCY"]
|
||||
set m_refclk_frequency [get_parameter_value "REFCLK_FREQUENCY"]
|
||||
set m_coreclk_frequency [get_parameter_value "CORECLK_FREQUENCY"]
|
||||
set m_num_of_convs [get_parameter_value "NUM_OF_CONVS"]
|
||||
set m_frm_bcnt [get_parameter_value "FRM_BCNT"]
|
||||
set m_frm_scnt [get_parameter_value "FRM_SCNT"]
|
||||
set m_mf_fcnt [get_parameter_value "MF_FCNT"]
|
||||
set m_hd [get_parameter_value "HD"]
|
||||
|
||||
add_instance alt_sys_clk clock_source 16.0
|
||||
set_instance_parameter_value alt_sys_clk {clockFrequency} {100000000.0}
|
||||
add_interface sys_clk clock sink
|
||||
set_interface_property sys_clk EXPORT_OF alt_sys_clk.clk_in
|
||||
add_interface sys_resetn reset sink
|
||||
set_interface_property sys_resetn EXPORT_OF alt_sys_clk.clk_in_reset
|
||||
|
||||
add_instance alt_ref_clk altera_clock_bridge 16.0
|
||||
set_instance_parameter_value alt_ref_clk {EXPLICIT_CLOCK_RATE} $m_refclk_frequency
|
||||
add_interface ref_clk clock sink
|
||||
set_interface_property ref_clk EXPORT_OF alt_ref_clk.in_clk
|
||||
|
||||
add_instance alt_ref_pll altera_iopll 16.0
|
||||
set_instance_parameter_value alt_ref_pll {gui_en_reconf} {1}
|
||||
set_instance_parameter_value alt_ref_pll {gui_reference_clock_frequency} $m_refclk_frequency
|
||||
set_instance_parameter_value alt_ref_pll {gui_use_locked} {1}
|
||||
set_instance_parameter_value alt_ref_pll {gui_output_clock_frequency0} $m_coreclk_frequency
|
||||
add_connection alt_ref_clk.out_clk alt_ref_pll.refclk
|
||||
add_connection alt_sys_clk.clk_reset alt_ref_pll.reset
|
||||
add_interface ref_pll_locked conduit end
|
||||
set_interface_property ref_pll_locked EXPORT_OF alt_ref_pll.locked
|
||||
|
||||
add_instance alt_ref_pll_reconfig altera_pll_reconfig 16.0
|
||||
add_connection alt_sys_clk.clk_reset alt_ref_pll_reconfig.mgmt_reset
|
||||
add_connection alt_sys_clk.clk alt_ref_pll_reconfig.mgmt_clk
|
||||
add_connection alt_ref_pll_reconfig.reconfig_to_pll alt_ref_pll.reconfig_to_pll
|
||||
add_connection alt_ref_pll.reconfig_from_pll alt_ref_pll_reconfig.reconfig_from_pll
|
||||
add_interface ref_pll_reconfig avalon slave
|
||||
set_interface_property ref_pll_reconfig EXPORT_OF alt_ref_pll_reconfig.mgmt_avalon_slave
|
||||
|
||||
add_instance alt_core_clk altera_clock_bridge 16.0
|
||||
set_instance_parameter_value alt_core_clk {EXPLICIT_CLOCK_RATE} $m_coreclk_frequency
|
||||
add_connection alt_ref_pll.outclk0 alt_core_clk.in_clk
|
||||
add_interface core_clk clock source
|
||||
set_interface_property core_clk EXPORT_OF alt_core_clk.out_clk
|
||||
|
||||
if {$m_tx_or_rx_n == 1} {
|
||||
|
||||
add_instance alt_rst_cntrol altera_xcvr_reset_control 16.0
|
||||
set_instance_parameter_value alt_rst_cntrol {CHANNELS} $m_num_of_lanes
|
||||
set_instance_parameter_value alt_rst_cntrol {SYS_CLK_IN_MHZ} {100}
|
||||
set_instance_parameter_value alt_rst_cntrol {TX_PLL_ENABLE} {1}
|
||||
set_instance_parameter_value alt_rst_cntrol {T_PLL_POWERDOWN} {1000}
|
||||
set_instance_parameter_value alt_rst_cntrol {TX_ENABLE} {1}
|
||||
set_instance_parameter_value alt_rst_cntrol {T_TX_ANALOGRESET} {70000}
|
||||
set_instance_parameter_value alt_rst_cntrol {T_TX_DIGITALRESET} {70000}
|
||||
set_instance_parameter_value alt_rst_cntrol {gui_pll_cal_busy} {1}
|
||||
set_instance_parameter_value alt_rst_cntrol {RX_ENABLE} {0}
|
||||
add_connection alt_sys_clk.clk alt_rst_cntrol.clock
|
||||
add_interface rst reset sink
|
||||
set_interface_property rst EXPORT_OF alt_rst_cntrol.reset
|
||||
add_interface ready conduit end
|
||||
set_interface_property ready EXPORT_OF alt_rst_cntrol.tx_ready
|
||||
|
||||
add_instance alt_lane_pll altera_xcvr_atx_pll_a10 16.0
|
||||
set_instance_parameter_value alt_lane_pll {enable_pll_reconfig} {1}
|
||||
set_instance_parameter_value alt_lane_pll {rcfg_separate_avmm_busy} {1}
|
||||
set_instance_parameter_value alt_lane_pll {set_capability_reg_enable} {1}
|
||||
set_instance_parameter_value alt_lane_pll {set_user_identifier} $m_id
|
||||
set_instance_parameter_value alt_lane_pll {set_csr_soft_logic_enable} {1}
|
||||
set_instance_parameter_value alt_lane_pll {set_output_clock_frequency} $m_pllclk_frequency
|
||||
set_instance_parameter_value alt_lane_pll {set_auto_reference_clock_frequency} $m_refclk_frequency
|
||||
add_connection alt_rst_cntrol.pll_powerdown alt_lane_pll.pll_powerdown
|
||||
add_connection alt_lane_pll.pll_locked alt_rst_cntrol.pll_locked
|
||||
add_connection alt_lane_pll.pll_cal_busy alt_rst_cntrol.pll_cal_busy
|
||||
add_connection alt_ref_clk.out_clk alt_lane_pll.pll_refclk0
|
||||
add_connection alt_sys_clk.clk alt_lane_pll.reconfig_clk0
|
||||
add_connection alt_sys_clk.clk_reset alt_lane_pll.reconfig_reset0
|
||||
add_interface lane_pll_reconfig avalon slave
|
||||
set_interface_property lane_pll_reconfig EXPORT_OF alt_lane_pll.reconfig_avmm0
|
||||
|
||||
add_instance alt_xcvr altera_jesd204 16.0
|
||||
set_instance_parameter_value alt_xcvr {wrapper_opt} {base_phy}
|
||||
set_instance_parameter_value alt_xcvr {DATA_PATH} {TX}
|
||||
set_instance_parameter_value alt_xcvr {lane_rate} $m_lane_rate
|
||||
set_instance_parameter_value alt_xcvr {PCS_CONFIG} $m_pcs_config
|
||||
set_instance_parameter_value alt_xcvr {bonded_mode} {non_bonded}
|
||||
set_instance_parameter_value alt_xcvr {pll_reconfig_enable} {1}
|
||||
set_instance_parameter_value alt_xcvr {set_capability_reg_enable} {1}
|
||||
set_instance_parameter_value alt_xcvr {set_user_identifier} $m_id
|
||||
set_instance_parameter_value alt_xcvr {set_csr_soft_logic_enable} {1}
|
||||
set_instance_parameter_value alt_xcvr {L} $m_num_of_lanes
|
||||
set_instance_parameter_value alt_xcvr {M} $m_num_of_convs
|
||||
set_instance_parameter_value alt_xcvr {GUI_EN_CFG_F} {1}
|
||||
set_instance_parameter_value alt_xcvr {GUI_CFG_F} $m_frm_bcnt
|
||||
set_instance_parameter_value alt_xcvr {N} {16}
|
||||
set_instance_parameter_value alt_xcvr {N_PRIME} {16}
|
||||
set_instance_parameter_value alt_xcvr {S} $m_frm_scnt
|
||||
set_instance_parameter_value alt_xcvr {K} $m_mf_fcnt
|
||||
set_instance_parameter_value alt_xcvr {SCR} {1}
|
||||
set_instance_parameter_value alt_xcvr {HD} $m_hd
|
||||
add_connection alt_rst_cntrol.tx_digitalreset alt_xcvr.tx_digitalreset
|
||||
add_connection alt_rst_cntrol.tx_analogreset alt_xcvr.tx_analogreset
|
||||
add_connection alt_xcvr.tx_cal_busy alt_rst_cntrol.tx_cal_busy
|
||||
add_connection alt_xcvr.dev_sync_n alt_xcvr.mdev_sync_n
|
||||
add_connection alt_sys_clk.clk alt_xcvr.reconfig_clk
|
||||
add_connection alt_sys_clk.clk_reset alt_xcvr.reconfig_reset
|
||||
add_interface phy_reconfig avalon slave
|
||||
set_interface_property phy_reconfig EXPORT_OF alt_xcvr.reconfig_avmm
|
||||
add_connection alt_sys_clk.clk alt_xcvr.jesd204_tx_avs_clk
|
||||
add_connection alt_sys_clk.clk_reset alt_xcvr.jesd204_tx_avs_rst_n
|
||||
add_interface ip_reconfig avalon slave
|
||||
set_interface_property ip_reconfig EXPORT_OF alt_xcvr.jesd204_tx_avs
|
||||
add_connection alt_ref_pll.outclk0 alt_xcvr.txlink_clk
|
||||
add_connection alt_sys_clk.clk_reset alt_xcvr.txlink_rst_n
|
||||
add_interface ip_data avalon_streaming sink
|
||||
set_interface_property ip_data EXPORT_OF alt_xcvr.jesd204_tx_link
|
||||
add_interface sysref conduit end
|
||||
set_interface_property sysref EXPORT_OF alt_xcvr.sysref
|
||||
add_interface sync conduit end
|
||||
set_interface_property sync EXPORT_OF alt_xcvr.sync_n
|
||||
add_interface tx_data conduit end
|
||||
set_interface_property tx_data EXPORT_OF alt_xcvr.tx_serial_data
|
||||
add_interface pll_locked conduit end
|
||||
set_interface_property pll_locked EXPORT_OF alt_xcvr.pll_locked
|
||||
for {set n 0} {$n < $m_num_of_lanes} {incr n} {
|
||||
add_connection alt_lane_pll.tx_serial_clk alt_xcvr.tx_serial_clk0_ch${n}
|
||||
}
|
||||
}
|
||||
|
||||
if {$m_tx_or_rx_n == 0} {
|
||||
|
||||
add_instance alt_rst_cntrol altera_xcvr_reset_control 16.0
|
||||
set_instance_parameter_value alt_rst_cntrol {CHANNELS} $m_num_of_lanes
|
||||
set_instance_parameter_value alt_rst_cntrol {SYS_CLK_IN_MHZ} {100}
|
||||
set_instance_parameter_value alt_rst_cntrol {TX_PLL_ENABLE} {0}
|
||||
set_instance_parameter_value alt_rst_cntrol {TX_ENABLE} {0}
|
||||
set_instance_parameter_value alt_rst_cntrol {RX_ENABLE} {1}
|
||||
set_instance_parameter_value alt_rst_cntrol {T_RX_ANALOGRESET} {70000}
|
||||
set_instance_parameter_value alt_rst_cntrol {T_RX_DIGITALRESET} {4000}
|
||||
add_connection alt_sys_clk.clk alt_rst_cntrol.clock
|
||||
add_interface rst reset sink
|
||||
set_interface_property rst EXPORT_OF alt_rst_cntrol.reset
|
||||
add_interface ready conduit end
|
||||
set_interface_property ready EXPORT_OF alt_rst_cntrol.rx_ready
|
||||
|
||||
add_instance alt_xcvr altera_jesd204 16.0
|
||||
set_instance_parameter_value alt_xcvr {wrapper_opt} {base_phy}
|
||||
set_instance_parameter_value alt_xcvr {DATA_PATH} {RX}
|
||||
set_instance_parameter_value alt_xcvr {lane_rate} $m_lane_rate
|
||||
set_instance_parameter_value alt_xcvr {PCS_CONFIG} $m_pcs_config
|
||||
set_instance_parameter_value alt_xcvr {REFCLK_FREQ} $m_refclk_frequency
|
||||
set_instance_parameter_value alt_xcvr {pll_reconfig_enable} {1}
|
||||
set_instance_parameter_value alt_xcvr {set_capability_reg_enable} {1}
|
||||
set_instance_parameter_value alt_xcvr {set_user_identifier} $m_id
|
||||
set_instance_parameter_value alt_xcvr {set_csr_soft_logic_enable} {1}
|
||||
set_instance_parameter_value alt_xcvr {L} $m_num_of_lanes
|
||||
set_instance_parameter_value alt_xcvr {M} $m_num_of_convs
|
||||
set_instance_parameter_value alt_xcvr {GUI_EN_CFG_F} {1}
|
||||
set_instance_parameter_value alt_xcvr {GUI_CFG_F} $m_frm_bcnt
|
||||
set_instance_parameter_value alt_xcvr {N} {16}
|
||||
set_instance_parameter_value alt_xcvr {N_PRIME} {16}
|
||||
set_instance_parameter_value alt_xcvr {S} $m_frm_scnt
|
||||
set_instance_parameter_value alt_xcvr {K} $m_mf_fcnt
|
||||
set_instance_parameter_value alt_xcvr {SCR} {1}
|
||||
set_instance_parameter_value alt_xcvr {HD} $m_hd
|
||||
add_connection alt_rst_cntrol.rx_digitalreset alt_xcvr.rx_digitalreset
|
||||
add_connection alt_rst_cntrol.rx_analogreset alt_xcvr.rx_analogreset
|
||||
add_connection alt_xcvr.rx_cal_busy alt_rst_cntrol.rx_cal_busy
|
||||
add_connection alt_xcvr.rx_islockedtodata alt_rst_cntrol.rx_is_lockedtodata
|
||||
add_connection alt_xcvr.dev_lane_aligned alt_xcvr.alldev_lane_aligned
|
||||
add_connection alt_sys_clk.clk alt_xcvr.reconfig_clk
|
||||
add_connection alt_sys_clk.clk_reset alt_xcvr.reconfig_reset
|
||||
add_interface phy_reconfig avalon slave
|
||||
set_interface_property phy_reconfig EXPORT_OF alt_xcvr.reconfig_avmm
|
||||
add_connection alt_sys_clk.clk alt_xcvr.jesd204_rx_avs_clk
|
||||
add_connection alt_sys_clk.clk_reset alt_xcvr.jesd204_rx_avs_rst_n
|
||||
add_interface ip_reconfig avalon slave
|
||||
set_interface_property ip_reconfig EXPORT_OF alt_xcvr.jesd204_rx_avs
|
||||
add_connection alt_ref_clk.out_clk alt_xcvr.pll_ref_clk
|
||||
add_connection alt_ref_pll.outclk0 alt_xcvr.rxlink_clk
|
||||
add_connection alt_sys_clk.clk_reset alt_xcvr.rxlink_rst_n
|
||||
add_interface ip_data avalon_streaming source
|
||||
set_interface_property ip_data EXPORT_OF alt_xcvr.jesd204_rx_link
|
||||
add_interface sysref conduit end
|
||||
set_interface_property sysref EXPORT_OF alt_xcvr.sysref
|
||||
add_interface sync conduit end
|
||||
set_interface_property sync EXPORT_OF alt_xcvr.dev_sync_n
|
||||
add_interface ip_sof conduit end
|
||||
set_interface_property ip_sof EXPORT_OF alt_xcvr.sof
|
||||
add_interface rx_data conduit end
|
||||
set_interface_property rx_data EXPORT_OF alt_xcvr.rx_serial_data
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,148 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2011(c) Analog Devices, Inc.
|
||||
//
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// - Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in
|
||||
// the documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
// contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
// - The use of this software may or may not infringe the patent rights
|
||||
// of one or more patent holders. This license does not release you
|
||||
// from the requirement that you obtain separate licenses from these
|
||||
// patent holders to use this software.
|
||||
// - Use of the software either in source or binary form, must be run
|
||||
// on or directly connected to an Analog Devices Inc. component.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
//
|
||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module axi_adxcvr (
|
||||
|
||||
// xcvr, lane-pll and ref-pll are shared
|
||||
|
||||
output up_rst,
|
||||
input up_ref_pll_locked,
|
||||
input up_pll_locked,
|
||||
input up_ready,
|
||||
|
||||
input s_axi_clk,
|
||||
input s_axi_aresetn,
|
||||
input s_axi_awvalid,
|
||||
input [31:0] s_axi_awaddr,
|
||||
input [ 2:0] s_axi_awprot,
|
||||
output s_axi_awready,
|
||||
input s_axi_wvalid,
|
||||
input [31:0] s_axi_wdata,
|
||||
input [ 3:0] s_axi_wstrb,
|
||||
output s_axi_wready,
|
||||
output s_axi_bvalid,
|
||||
output [ 1:0] s_axi_bresp,
|
||||
input s_axi_bready,
|
||||
input s_axi_arvalid,
|
||||
input [31:0] s_axi_araddr,
|
||||
input [ 2:0] s_axi_arprot,
|
||||
output s_axi_arready,
|
||||
output s_axi_rvalid,
|
||||
output [ 1:0] s_axi_rresp,
|
||||
output [31:0] s_axi_rdata,
|
||||
input s_axi_rready);
|
||||
|
||||
// parameters
|
||||
|
||||
parameter integer ID = 0;
|
||||
parameter integer TX_OR_RX_N = 0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire up_rstn;
|
||||
wire up_clk;
|
||||
wire up_wreq;
|
||||
wire [ 9:0] up_waddr;
|
||||
wire [31:0] up_wdata;
|
||||
wire up_wack;
|
||||
wire up_rreq;
|
||||
wire [ 9:0] up_raddr;
|
||||
wire [31:0] up_rdata;
|
||||
wire up_rack;
|
||||
|
||||
// clk & rst
|
||||
|
||||
assign up_rstn = axi_aresetn;
|
||||
assign up_clk = axi_clk;
|
||||
|
||||
// instantiations
|
||||
|
||||
axi_adxcvr_up #(
|
||||
.ID (ID),
|
||||
.TX_OR_RX_N (TX_OR_RX_N))
|
||||
i_up (
|
||||
.up_rst (up_rst),
|
||||
.up_ref_pll_locked (up_ref_pll_locked),
|
||||
.up_pll_locked (up_pll_locked),
|
||||
.up_ready (up_ready),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata),
|
||||
.up_rack (up_rack));
|
||||
|
||||
up_axi #(.ADDRESS_WIDTH (10)) i_axi (
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_axi_awvalid (s_axi_awvalid),
|
||||
.up_axi_awaddr (s_axi_awaddr),
|
||||
.up_axi_awready (s_axi_awready),
|
||||
.up_axi_wvalid (s_axi_wvalid),
|
||||
.up_axi_wdata (s_axi_wdata),
|
||||
.up_axi_wstrb (s_axi_wstrb),
|
||||
.up_axi_wready (s_axi_wready),
|
||||
.up_axi_bvalid (s_axi_bvalid),
|
||||
.up_axi_bresp (s_axi_bresp),
|
||||
.up_axi_bready (s_axi_bready),
|
||||
.up_axi_arvalid (s_axi_arvalid),
|
||||
.up_axi_araddr (s_axi_araddr),
|
||||
.up_axi_arready (s_axi_arready),
|
||||
.up_axi_rvalid (s_axi_rvalid),
|
||||
.up_axi_rresp (s_axi_rresp),
|
||||
.up_axi_rdata (s_axi_rdata),
|
||||
.up_axi_rready (s_axi_rready),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata),
|
||||
.up_rack (up_rack));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
|
||||
package require -exact qsys 14.0
|
||||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
|
||||
|
||||
set_module_property NAME axi_adxcvr
|
||||
set_module_property DESCRIPTION "AXI ADXCVR Interface"
|
||||
set_module_property VERSION 1.0
|
||||
set_module_property GROUP "Analog Devices"
|
||||
set_module_property DISPLAY_NAME axi_adxcvr
|
||||
|
||||
# files
|
||||
|
||||
add_fileset quartus_synth QUARTUS_SYNTH "" ""
|
||||
set_fileset_property quartus_synth TOP_LEVEL axi_adxcvr
|
||||
add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
|
||||
add_fileset_file axi_adxcvr_up.v VERILOG PATH axi_adxcvr_up.v
|
||||
add_fileset_file axi_adxcvr.v VERILOG PATH axi_adxcvr.v TOP_LEVEL_FILE
|
||||
|
||||
# parameters
|
||||
|
||||
add_parameter ID INTEGER 0
|
||||
set_parameter_property ID DISPLAY_NAME ID
|
||||
set_parameter_property ID TYPE INTEGER
|
||||
set_parameter_property ID UNITS None
|
||||
set_parameter_property ID HDL_PARAMETER true
|
||||
|
||||
add_parameter TX_OR_RX_N INTEGER 0
|
||||
set_parameter_property DEVICE_TYPE DISPLAY_NAME TX_OR_RX_N
|
||||
set_parameter_property DEVICE_TYPE TYPE INTEGER
|
||||
set_parameter_property DEVICE_TYPE UNITS None
|
||||
set_parameter_property DEVICE_TYPE HDL_PARAMETER true
|
||||
|
||||
# axi4 slave interface
|
||||
|
||||
add_interface s_axi_clock clock end
|
||||
add_interface_port s_axi_clock s_axi_aclk clk Input 1
|
||||
|
||||
add_interface s_axi_reset reset end
|
||||
set_interface_property s_axi_reset associatedClock s_axi_clock
|
||||
add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
|
||||
|
||||
add_interface s_axi axi4lite end
|
||||
set_interface_property s_axi associatedClock s_axi_clock
|
||||
set_interface_property s_axi associatedReset s_axi_reset
|
||||
add_interface_port s_axi s_axi_awvalid awvalid Input 1
|
||||
add_interface_port s_axi s_axi_awaddr awaddr Input 16
|
||||
add_interface_port s_axi s_axi_awprot awprot Input 3
|
||||
add_interface_port s_axi s_axi_awready awready Output 1
|
||||
add_interface_port s_axi s_axi_wvalid wvalid Input 1
|
||||
add_interface_port s_axi s_axi_wdata wdata Input 32
|
||||
add_interface_port s_axi s_axi_wstrb wstrb Input 4
|
||||
add_interface_port s_axi s_axi_wready wready Output 1
|
||||
add_interface_port s_axi s_axi_bvalid bvalid Output 1
|
||||
add_interface_port s_axi s_axi_bresp bresp Output 2
|
||||
add_interface_port s_axi s_axi_bready bready Input 1
|
||||
add_interface_port s_axi s_axi_arvalid arvalid Input 1
|
||||
add_interface_port s_axi s_axi_araddr araddr Input 16
|
||||
add_interface_port s_axi s_axi_arprot arprot Input 3
|
||||
add_interface_port s_axi s_axi_arready arready Output 1
|
||||
add_interface_port s_axi s_axi_rvalid rvalid Output 1
|
||||
add_interface_port s_axi s_axi_rresp rresp Output 2
|
||||
add_interface_port s_axi s_axi_rdata rdata Output 32
|
||||
add_interface_port s_axi s_axi_rready rready Input 1
|
||||
|
||||
# xcvr interface
|
||||
|
||||
add_interface if_xcvr conduit end
|
||||
add_interface_port if_xcvr up_rst up_rst Output 1
|
||||
add_interface_port if_xcvr up_ref_pll_locked up_ref_pll_locked Input 1
|
||||
add_interface_port if_xcvr up_pll_locked up_pll_locked Input 1
|
||||
add_interface_port if_xcvr up_ready up_ready Input 1
|
||||
|
||||
set_interface_property if_xcvr associatedClock s_axi_clock
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,158 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2011(c) Analog Devices, Inc.
|
||||
//
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// - Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in
|
||||
// the documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
// contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
// - The use of this software may or may not infringe the patent rights
|
||||
// of one or more patent holders. This license does not release you
|
||||
// from the requirement that you obtain separate licenses from these
|
||||
// patent holders to use this software.
|
||||
// - Use of the software either in source or binary form, must be run
|
||||
// on or directly connected to an Analog Devices Inc. component.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
//
|
||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_adxcvr_up (
|
||||
|
||||
// xcvr, lane-pll and ref-pll are shared
|
||||
|
||||
output up_rst,
|
||||
input up_ref_pll_locked,
|
||||
input up_pll_locked,
|
||||
input up_ready,
|
||||
|
||||
// bus interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_wreq,
|
||||
input [ 9:0] up_waddr,
|
||||
input [31:0] up_wdata,
|
||||
output up_wack,
|
||||
input up_rreq,
|
||||
input [ 9:0] up_raddr,
|
||||
output [31:0] up_rdata,
|
||||
output up_rack);
|
||||
|
||||
// parameters
|
||||
|
||||
localparam [31:0] VERSION = 32'h00100161;
|
||||
parameter integer ID = 0;
|
||||
parameter integer TX_OR_RX_N = 0;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg up_wreq_d = 'd0;
|
||||
reg [31:0] up_scratch = 'd0;
|
||||
reg up_resetn = 'd0;
|
||||
reg [ 3:0] up_rst_cnt = 'd0;
|
||||
reg up_status_int = 'd0;
|
||||
reg up_rreq_d = 'd0;
|
||||
reg [31:0] up_rdata_d = 'd0;
|
||||
|
||||
// defaults
|
||||
|
||||
assign up_wack = up_wreq_d;
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_wreq_d <= 'd0;
|
||||
up_scratch <= 'd0;
|
||||
end else begin
|
||||
up_wreq_d <= up_wreq;
|
||||
if ((up_wreq == 1'b1) && (up_waddr == 10'h002)) begin
|
||||
up_scratch <= up_wdata;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// reset-controller
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_resetn <= 'd0;
|
||||
end else begin
|
||||
if ((up_wreq == 1'b1) && (up_waddr == 10'h004)) begin
|
||||
up_resetn <= up_wdata[0];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign up_rst = up_rst_cnt[3];
|
||||
assign up_status = up_status_int;
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_rst_cnt <= 4'h8;
|
||||
up_status_int <= 1'b0;
|
||||
end else begin
|
||||
if (up_resetn == 1'b0) begin
|
||||
up_rst_cnt <= 4'h8;
|
||||
end else if (up_rst_cnt[3] == 1'b1) begin
|
||||
up_rst_cnt <= up_rst_cnt + 1'b1;
|
||||
end
|
||||
if (up_resetn == 1'b0) begin
|
||||
up_status_int <= 1'b0;
|
||||
end else if ((up_pll_locked == 1'b1) && (up_ready == 1'b1) &&
|
||||
(up_ref_pll_locked == 1'b1)) begin
|
||||
up_status_int <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// read interface
|
||||
|
||||
assign up_rack = up_rreq_d;
|
||||
assign up_rdata = up_rdata_d;
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_rreq_d <= 'd0;
|
||||
up_rdata_d <= 'd0;
|
||||
end else begin
|
||||
up_rreq_d <= up_rreq;
|
||||
if (up_rreq == 1'b1) begin
|
||||
case (up_raddr)
|
||||
10'h000: up_rdata_d <= VERSION;
|
||||
10'h001: up_rdata_d <= ID;
|
||||
10'h002: up_rdata_d <= up_scratch;
|
||||
10'h004: up_rdata_d <= {31'd0, up_resetn};
|
||||
10'h005: up_rdata_d <= {31'd0, up_status_int};
|
||||
10'h006: up_rdata_d <= {29'd0, up_pll_locked, up_ref_pll_locked, up_ready};
|
||||
default: up_rdata_d <= 32'd0;
|
||||
endcase
|
||||
end else begin
|
||||
up_rdata_d <= 32'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
Loading…
Reference in New Issue