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xilinx/common: Set the register to an initial value 

Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
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Ionut Podgoreanu 2023-11-07 08:02:41 +02:00 committed by podgori
parent 38037641af
commit b8418e7e92
1 changed files with 2 additions and 2 deletions
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4
library/xilinx/common/ad_mul.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -52,7 +52,7 @@ module ad_mul #(
// delay interface
input [(DELAY_DATA_WIDTH-1):0] ddata_in,
output reg [(DELAY_DATA_WIDTH-1):0] ddata_out
output reg [(DELAY_DATA_WIDTH-1):0] ddata_out = 'd0
);
// internal registers