From b8418e7e928eeca188d32a61bb9f093eb272af4f Mon Sep 17 00:00:00 2001 From: Ionut Podgoreanu Date: Tue, 7 Nov 2023 08:02:41 +0200 Subject: [PATCH] xilinx/common: Set the register to an initial value Signed-off-by: Ionut Podgoreanu --- library/xilinx/common/ad_mul.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/library/xilinx/common/ad_mul.v b/library/xilinx/common/ad_mul.v index 3028b98cb..e95ed05a9 100644 --- a/library/xilinx/common/ad_mul.v +++ b/library/xilinx/common/ad_mul.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -52,7 +52,7 @@ module ad_mul #( // delay interface input [(DELAY_DATA_WIDTH-1):0] ddata_in, - output reg [(DELAY_DATA_WIDTH-1):0] ddata_out + output reg [(DELAY_DATA_WIDTH-1):0] ddata_out = 'd0 ); // internal registers