fmcomms2: take into consideration both adc_r1 and dac_r1 for clock division selection
parent
4b2602437f
commit
b84325d43f
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@ -75,6 +75,12 @@ set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $dac_fifo
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set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $dac_fifo
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set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $dac_fifo
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set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $dac_fifo
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set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $dac_fifo
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set clkdiv_sel_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 clkdiv_sel_logic]
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set_property -dict [list CONFIG.C_SIZE {2}] $clkdiv_sel_logic
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set concat_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 concat_logic]
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set_property -dict [list CONFIG.NUM_PORTS {2}] $concat_logic
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# connections
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# connections
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ad_connect sys_200m_clk axi_ad9361/delay_clk
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ad_connect sys_200m_clk axi_ad9361/delay_clk
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@ -128,7 +134,12 @@ ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din
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ad_connect axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf
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ad_connect axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf
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ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf
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ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf
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ad_connect axi_ad9361_clk clkdiv/clk
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ad_connect axi_ad9361_clk clkdiv/clk
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ad_connect axi_ad9361/adc_r1_mode clkdiv/clk_sel
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ad_connect axi_ad9361/adc_r1_mode concat_logic/In0
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ad_connect axi_ad9361/dac_r1_mode concat_logic/In1
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ad_connect concat_logic/dout clkdiv_sel_logic/Op1
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ad_connect clkdiv/clk_sel clkdiv_sel_logic/Res
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ad_connect clkdiv/clk_out axi_ad9361_adc_dma/fifo_wr_clk
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ad_connect clkdiv/clk_out axi_ad9361_adc_dma/fifo_wr_clk
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ad_connect clkdiv/clk_out util_ad9361_adc_fifo/dout_clk
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ad_connect clkdiv/clk_out util_ad9361_adc_fifo/dout_clk
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ad_connect clkdiv/clk_out util_ad9361_adc_pack/adc_clk
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ad_connect clkdiv/clk_out util_ad9361_adc_pack/adc_clk
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