diff --git a/projects/cn0579/Makefile b/projects/cn0579/Makefile new file mode 100644 index 000000000..1402069e1 --- /dev/null +++ b/projects/cn0579/Makefile @@ -0,0 +1,7 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +include ../scripts/project-toplevel.mk diff --git a/projects/cn0579/Readme.md b/projects/cn0579/Readme.md new file mode 100644 index 000000000..eb900f35b --- /dev/null +++ b/projects/cn0579/Readme.md @@ -0,0 +1,8 @@ +# CN0579 HDL Project + +Here are some pointers to help you: + * [Board Product Page](https://www.analog.com/en/products/cn0579.html) + * Parts : [Multichannel IEPE DAQ for CbM](https://www.analog.com/en/products/cn0579.html) + * Project Doc: https://wiki.analog.com/resources/eval/user-guides/cn0579 + * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/cn0579 + * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/axi-adc-hdl \ No newline at end of file diff --git a/projects/cn0579/common/cn0579_bd.tcl b/projects/cn0579/common/cn0579_bd.tcl new file mode 100644 index 000000000..daa00bdb7 --- /dev/null +++ b/projects/cn0579/common/cn0579_bd.tcl @@ -0,0 +1,70 @@ +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_dac + +# ad7768-4 interface + +create_bd_port -dir I clk_in +create_bd_port -dir I ready_in +create_bd_port -dir I -from 7 -to 0 data_in + +#dac iic + +ad_ip_instance axi_iic axi_iic_dac +ad_connect iic_dac axi_iic_dac/iic + +# adc(cn0579-dma) + +ad_ip_instance axi_dmac cn0579_dma +ad_ip_parameter cn0579_dma CONFIG.DMA_TYPE_SRC 2 +ad_ip_parameter cn0579_dma CONFIG.DMA_TYPE_DEST 0 +ad_ip_parameter cn0579_dma CONFIG.CYCLIC 0 +ad_ip_parameter cn0579_dma CONFIG.SYNC_TRANSFER_START 1 +ad_ip_parameter cn0579_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter cn0579_dma CONFIG.AXI_SLICE_DEST 0 +ad_ip_parameter cn0579_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter cn0579_dma CONFIG.DMA_DATA_WIDTH_SRC 128 +ad_ip_parameter cn0579_dma CONFIG.DMA_DATA_WIDTH_DEST 64 + +# axi_ad77684 + +ad_ip_instance axi_ad7768 axi_ad77684_adc +ad_ip_parameter axi_ad77684_adc CONFIG.NUM_CHANNELS 4 + +# adc-path channel pack + +ad_ip_instance util_cpack2 cn0579_adc_pack +ad_ip_parameter cn0579_adc_pack CONFIG.NUM_OF_CHANNELS 4 +ad_ip_parameter cn0579_adc_pack CONFIG.SAMPLE_DATA_WIDTH 32 + +# connections + +for {set i 0} {$i < 4} {incr i} { + ad_connect axi_ad77684_adc/adc_enable_$i cn0579_adc_pack/enable_$i + ad_connect axi_ad77684_adc/adc_data_$i cn0579_adc_pack/fifo_wr_data_$i +} + +ad_connect axi_ad77684_adc/s_axi_aclk sys_ps7/FCLK_CLK0 +ad_connect axi_ad77684_adc/clk_in clk_in +ad_connect axi_ad77684_adc/ready_in ready_in +ad_connect axi_ad77684_adc/data_in data_in +ad_connect axi_ad77684_adc/adc_valid cn0579_adc_pack/fifo_wr_en +ad_connect axi_ad77684_adc/adc_clk cn0579_adc_pack/clk +ad_connect axi_ad77684_adc/adc_reset cn0579_adc_pack/reset +ad_connect axi_ad77684_adc/adc_dovf cn0579_adc_pack/fifo_wr_overflow + +ad_connect cn0579_dma/m_dest_axi_aresetn sys_cpu_resetn +ad_connect cn0579_dma/fifo_wr_clk axi_ad77684_adc/adc_clk +ad_connect cn0579_dma/fifo_wr cn0579_adc_pack/packed_fifo_wr + +# interrupts + +ad_cpu_interrupt "ps-13" "mb-13" cn0579_dma/irq +ad_cpu_interrupt "ps-12" "mb-12" axi_iic_dac/iic2intc_irpt + +# cpu / memory interconnects + +ad_cpu_interconnect 0x44a00000 axi_ad77684_adc +ad_cpu_interconnect 0x44a30000 cn0579_dma +ad_cpu_interconnect 0x44a40000 axi_iic_dac + +ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1 +ad_mem_hp1_interconnect $sys_cpu_clk cn0579_dma/m_dest_axi diff --git a/projects/cn0579/common/cn0579_qsys.tcl b/projects/cn0579/common/cn0579_qsys.tcl new file mode 100644 index 000000000..7c619e92d --- /dev/null +++ b/projects/cn0579/common/cn0579_qsys.tcl @@ -0,0 +1,70 @@ +# ad77684 + +add_instance axi_ad77684_adc axi_ad7768 +set_instance_parameter_value axi_ad77684_adc {NUM_CHANNELS} {4} +add_interface if_clk_in_bd conduit end +add_interface if_ready_in_bd conduit end +add_interface if_data_in_bd conduit end + +set_interface_property if_clk_in_bd EXPORT_OF axi_ad77684_adc.if_clk_in +set_interface_property if_ready_in_bd EXPORT_OF axi_ad77684_adc.if_ready_in +set_interface_property if_data_in_bd EXPORT_OF axi_ad77684_adc.if_data_in + +# adc-path channel pack + +add_instance cn0579_adc_pack util_cpack2 +set_instance_parameter_value cn0579_adc_pack {NUM_OF_CHANNELS} {4} +set_instance_parameter_value cn0579_adc_pack {SAMPLE_DATA_WIDTH} {32} + +add_connection axi_ad77684_adc.if_adc_clk cn0579_adc_pack.clk +add_connection axi_ad77684_adc.if_adc_reset cn0579_adc_pack.reset +add_connection axi_ad77684_adc.if_adc_dovf cn0579_adc_pack.if_fifo_wr_overflow +add_connection axi_ad77684_adc.adc_ch_0 cn0579_adc_pack.adc_ch_0 +add_connection axi_ad77684_adc.adc_ch_1 cn0579_adc_pack.adc_ch_1 +add_connection axi_ad77684_adc.adc_ch_2 cn0579_adc_pack.adc_ch_2 +add_connection axi_ad77684_adc.adc_ch_3 cn0579_adc_pack.adc_ch_3 + +# adc(cn0579-dma) + +add_instance cn0579_dma axi_dmac +set_instance_parameter_value cn0579_dma {ID} {0} +set_instance_parameter_value cn0579_dma {DMA_DATA_WIDTH_SRC} {128} +set_instance_parameter_value cn0579_dma {DMA_DATA_WIDTH_DEST} {64} +set_instance_parameter_value cn0579_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value cn0579_dma {AXI_SLICE_DEST} {0} +set_instance_parameter_value cn0579_dma {AXI_SLICE_SRC} {0} +set_instance_parameter_value cn0579_dma {SYNC_TRANSFER_START} {1} +set_instance_parameter_value cn0579_dma {CYCLIC} {0} +set_instance_parameter_value cn0579_dma {DMA_TYPE_DEST} {0} +set_instance_parameter_value cn0579_dma {DMA_TYPE_SRC} {2} + +add_connection axi_ad77684_adc.if_adc_clk cn0579_dma.if_fifo_wr_clk +add_connection cn0579_adc_pack.if_packed_fifo_wr_en cn0579_dma.if_fifo_wr_en +add_connection cn0579_adc_pack.if_packed_fifo_wr_sync cn0579_dma.if_fifo_wr_sync +add_connection cn0579_adc_pack.if_packed_fifo_wr_data cn0579_dma.if_fifo_wr_din +add_connection cn0579_adc_pack.if_packed_fifo_wr_overflow cn0579_dma.if_fifo_wr_overflow + +#clocks + +add_connection sys_clk.clk cn0579_dma.s_axi_clock +add_connection sys_clk.clk axi_ad77684_adc.s_axi_clock +add_connection sys_dma_clk.clk cn0579_dma.m_dest_axi_clock + +#resets + +add_connection sys_clk.clk_reset axi_ad77684_adc.s_axi_reset +add_connection sys_clk.clk_reset cn0579_dma.s_axi_reset +add_connection sys_dma_clk.clk_reset cn0579_dma.m_dest_axi_reset + +# interrupts + +ad_cpu_interrupt 5 cn0579_dma.interrupt_sender + +# cpu interconnects + +ad_cpu_interconnect 0x00028000 cn0579_dma.s_axi +ad_cpu_interconnect 0x00030000 axi_ad77684_adc.s_axi + +# mem interconnects + +ad_dma_interconnect cn0579_dma.m_dest_axi diff --git a/projects/cn0579/coraz7s/Makefile b/projects/cn0579/coraz7s/Makefile new file mode 100644 index 000000000..723c07f22 --- /dev/null +++ b/projects/cn0579/coraz7s/Makefile @@ -0,0 +1,22 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := cn0579_coraz7s + +M_DEPS += ../common/cn0579_bd.tcl +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl +M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc +M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl +M_DEPS += ../../../library/common/ad_iobuf.v + +LIB_DEPS += axi_ad7768 +LIB_DEPS += axi_dmac +LIB_DEPS += axi_sysid +LIB_DEPS += sysid_rom +LIB_DEPS += util_pack/util_cpack2 + +include ../../scripts/project-xilinx.mk diff --git a/projects/cn0579/coraz7s/system_bd.tcl b/projects/cn0579/coraz7s/system_bd.tcl new file mode 100644 index 000000000..0e1b2817c --- /dev/null +++ b/projects/cn0579/coraz7s/system_bd.tcl @@ -0,0 +1,12 @@ +source $ad_hdl_dir/projects/common/coraz7s/coraz7s_system_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl + +#system ID + +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 +set sys_cstring "sys rom custom string placeholder" +sysid_gen_sys_init_file $sys_cstring + +source ../common/cn0579_bd.tcl diff --git a/projects/cn0579/coraz7s/system_constr.xdc b/projects/cn0579/coraz7s/system_constr.xdc new file mode 100644 index 000000000..1dc82644a --- /dev/null +++ b/projects/cn0579/coraz7s/system_constr.xdc @@ -0,0 +1,26 @@ + set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33} [get_ports clk_in ]; ## P12.10 IO8 + set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports ready_in ]; ## P12.9 IO9 + + set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports data_in[0] ]; ## P14.1 IO7 + set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports data_in[1] ]; ## P14.2 IO6 + set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports data_in[2] ]; ## P14.3 IO5 + set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports data_in[3] ]; ## P14.4 IO4 + + set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports shutdown_n ]; ## P14.5 IO3 + set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports reset_n ]; ## P14.6 IO2 + + set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33} [get_ports spi_csn ]; ## P12.8 IO10 + set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports spi_mosi ]; ## P12.7 IO11 + set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports spi_miso ]; ## P12.6 IO12 + set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports spi_clk ]; ## P12.5 IO13 + set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports dac_i2c_scl]; ## P12.1 CK_SCL + set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports dac_i2c_sda]; ## P12.2 CK_SDA + +set input_clock_period 30.51; # Period of input clock fMAX_DCLK=32.768MHz +set hold_time 8.5; +set setup_time 8.5; + +create_clock -name adc_clk -period $input_clock_period [get_ports clk_in] + +set_input_delay -clock adc_clk -max [expr $input_clock_period - $setup_time] [get_ports data_in[*]] -clock_fall -add_delay; +set_input_delay -clock adc_clk -min $hold_time [get_ports data_in[*]] -clock_fall -add_delay; diff --git a/projects/cn0579/coraz7s/system_project.tcl b/projects/cn0579/coraz7s/system_project.tcl new file mode 100644 index 000000000..36e7eaafd --- /dev/null +++ b/projects/cn0579/coraz7s/system_project.tcl @@ -0,0 +1,13 @@ +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project cn0579_coraz7s 0 + +adi_project_files cn0579_coraz7s [list \ + "$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "system_top.v" \ + "system_constr.xdc" ] + +adi_project_run cn0579_coraz7s diff --git a/projects/cn0579/coraz7s/system_top.v b/projects/cn0579/coraz7s/system_top.v new file mode 100644 index 000000000..8c636ce30 --- /dev/null +++ b/projects/cn0579/coraz7s/system_top.v @@ -0,0 +1,160 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [ 1:0] btn, + inout [ 5:0] led, + + input clk_in, + input ready_in, + input [ 3:0] data_in, + + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso, + output shutdown_n, + output reset_n, + + // dac i2c + + inout dac_i2c_scl, + inout dac_i2c_sda +); + + // internal signals + + wire [63:0] adc_gpio_i; + wire [63:0] adc_gpio_o; + wire [63:0] adc_gpio_t; + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + assign shutdown_n = 1; + assign reset_n = gpio_o[32]; + assign gpio_i[63:8] = gpio_o[63:8]; + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iobuf_buttons ( + .dio_t(gpio_t[1:0]), + .dio_i(gpio_o[1:0]), + .dio_o(gpio_i[1:0]), + .dio_p(btn)); + + ad_iobuf #( + .DATA_WIDTH(6) + ) i_iobuf_leds ( + .dio_t(gpio_t[7:2]), + .dio_i(gpio_o[7:2]), + .dio_o(gpio_i[7:2]), + .dio_p(led)); + + system_wrapper i_system_wrapper ( + .clk_in (clk_in), + .ready_in (ready_in), + .data_in (data_in), + .iic_dac_scl_io (dac_i2c_scl), + .iic_dac_sda_io (dac_i2c_sda), + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk), + .spi0_csn_0_o (spi_csn), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o ()); + +endmodule diff --git a/projects/cn0579/de10nano/Makefile b/projects/cn0579/de10nano/Makefile new file mode 100644 index 000000000..dbc3ef47d --- /dev/null +++ b/projects/cn0579/de10nano/Makefile @@ -0,0 +1,21 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := cn0579_de10nano + +M_DEPS += ../common/cn0579_qsys.tcl +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/de10nano/de10nano_system_qsys.tcl +M_DEPS += ../../common/de10nano/de10nano_system_assign.tcl + +LIB_DEPS += axi_ad7768 +LIB_DEPS += axi_dmac +LIB_DEPS += axi_hdmi_tx +LIB_DEPS += axi_sysid +LIB_DEPS += sysid_rom +LIB_DEPS += util_pack/util_cpack2 + +include ../../scripts/project-intel.mk diff --git a/projects/cn0579/de10nano/system_constr.sdc b/projects/cn0579/de10nano/system_constr.sdc new file mode 100644 index 000000000..d6276d034 --- /dev/null +++ b/projects/cn0579/de10nano/system_constr.sdc @@ -0,0 +1,13 @@ +create_clock -period "20.000 ns" -name sys_clk [get_ports {sys_clk}] +create_clock -period "16.666 ns" -name usb1_clk [get_ports {usb1_clk}] +create_clock -period "122.07 ns" -name adc_clk [get_ports {adc_clk_in}] + +derive_pll_clocks +derive_clock_uncertainty + +set input_clock_period 30.51; # Period of input clock fMAX_DCLK=32.768MHz +set hold_time 8.5; +set setup_time 8.5; + +set_input_delay -clock adc_clk -max [expr $input_clock_period - $setup_time] [get_ports data_in[*]] -clock_fall -add_delay; +set_input_delay -clock adc_clk -min $hold_time [get_ports data_in[*]] -clock_fall -add_delay; diff --git a/projects/cn0579/de10nano/system_project.tcl b/projects/cn0579/de10nano/system_project.tcl new file mode 100644 index 000000000..72654aea3 --- /dev/null +++ b/projects/cn0579/de10nano/system_project.tcl @@ -0,0 +1,53 @@ +set REQUIRED_QUARTUS_VERSION 21.1 +set QUARTUS_PRO_ISUSED 0 +source ../../../scripts/adi_env.tcl +source ../../scripts/adi_project_intel.tcl + +adi_project cn0579_de10nano + +source $ad_hdl_dir/projects/common/de10nano/de10nano_system_assign.tcl + +# ad77684 interface + +set_location_assignment PIN_AF17 -to adc_clk_in ; ## P12.10 Arduino_IO08 +set_location_assignment PIN_AE15 -to adc_ready_in ; ## P12.9 Arduino_IO09 + +set_location_assignment PIN_AH8 -to adc_data_in[0]; ## P14.1 Arduino_IO07 +set_location_assignment PIN_AG8 -to adc_data_in[1]; ## P14.2 Arduino_IO06 +set_location_assignment PIN_U13 -to adc_data_in[2]; ## P14.3 Arduino_IO05 +set_location_assignment PIN_U14 -to adc_data_in[3]; ## P14.4 Arduino_IO04 + +set_location_assignment PIN_AG9 -to shutdown_n ; ## P14.5 Arduino_IO03 +set_location_assignment PIN_AG10 -to reset_n ; ## P14.6 Arduino_IO02 + +set_location_assignment PIN_AF15 -to spi_csn ; ## P12.8 Arduino_IO10 +set_location_assignment PIN_AG16 -to spi_mosi ; ## P12.7 Arduino_IO11 +set_location_assignment PIN_AH11 -to spi_miso ; ## P12.6 Arduino_IO12 +set_location_assignment PIN_AH12 -to spi_clk ; ## P12.5 Arduino_IO13 + +set_location_assignment PIN_AG11 -to dac_i2c_scl ; ## P12.1 Arduino_IO15 +set_location_assignment PIN_AH9 -to dac_i2c_sda ; ## P12.2 Arduino_IO14 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to adc_clk_in +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to adc_ready_in + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to adc_data_in[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to adc_data_in[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to adc_data_in[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to adc_data_in[3] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to shutdown_n +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to reset_n + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi_csn +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi_mosi +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi_miso +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi_clk + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dac_i2c_scl +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dac_i2c_sda + +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to dac_i2c_scl +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to dac_i2c_sda + +execute_flow -compile diff --git a/projects/cn0579/de10nano/system_qsys.tcl b/projects/cn0579/de10nano/system_qsys.tcl new file mode 100644 index 000000000..12310c27f --- /dev/null +++ b/projects/cn0579/de10nano/system_qsys.tcl @@ -0,0 +1,20 @@ +source $ad_hdl_dir/projects/scripts/adi_pd.tcl +source $ad_hdl_dir/projects/common/de10nano/de10nano_system_qsys.tcl + + +if [info exists ad_project_dir] { + source ../../common/cn0579_qsys.tcl +} else { + source ../common/cn0579_qsys.tcl +} + +set_instance_parameter_value sys_spi {clockPolarity} {0} + +#system ID + +set_instance_parameter_value axi_sysid_0 {ROM_ADDR_BITS} {9} +set_instance_parameter_value rom_sys_0 {ROM_ADDR_BITS} {9} + +set_instance_parameter_value rom_sys_0 {PATH_TO_FILE} "[pwd]/mem_init_sys.txt" + +sysid_gen_sys_init_file; diff --git a/projects/cn0579/de10nano/system_top.v b/projects/cn0579/de10nano/system_top.v new file mode 100644 index 000000000..42d2577af --- /dev/null +++ b/projects/cn0579/de10nano/system_top.v @@ -0,0 +1,276 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2022 - 2023 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + // clock and resets + + input sys_clk, + + // hps-ddr + + output [14:0] ddr3_a, + output [ 2:0] ddr3_ba, + output ddr3_reset_n, + output ddr3_ck_p, + output ddr3_ck_n, + output ddr3_cke, + output ddr3_cs_n, + output ddr3_ras_n, + output ddr3_cas_n, + output ddr3_we_n, + inout [31:0] ddr3_dq, + inout [ 3:0] ddr3_dqs_p, + inout [ 3:0] ddr3_dqs_n, + output [ 3:0] ddr3_dm, + output ddr3_odt, + input ddr3_rzq, + + // hps-ethernet + + output eth1_tx_clk, + output eth1_tx_ctl, + output [ 3:0] eth1_tx_d, + input eth1_rx_clk, + input eth1_rx_ctl, + input [ 3:0] eth1_rx_d, + output eth1_mdc, + inout eth1_mdio, + + // hps-sdio + + output sdio_clk, + inout sdio_cmd, + inout [ 3:0] sdio_d, + + // hps-spim1 + + output spim1_ss0, + output spim1_clk, + output spim1_mosi, + input spim1_miso, + + // hps-usb + + input usb1_clk, + output usb1_stp, + input usb1_dir, + input usb1_nxt, + inout [ 7:0] usb1_d, + + // hps-uart + + input uart0_rx, + output uart0_tx, + inout hps_conv_usb_n, + + // board gpio + + output [ 7:0] gpio_bd_o, + input [ 5:0] gpio_bd_i, + + // hdmi + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [ 23:0] hdmi_data, + + inout hdmi_i2c_scl, + inout hdmi_i2c_sda, + + // ad77684 + + input adc_clk_in, + input adc_ready_in, + input [ 3:0] adc_data_in, + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso, + output reset_n, + output start_n, + output shutdown_n, + + // dac i2c + + inout dac_i2c_scl, + inout dac_i2c_sda +); + + // internal signals + + wire sys_resetn; + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + wire i2c1_out_data; + wire i2c1_sda; + wire i2c1_out_clk; + wire i2c1_scl_in_clk; + + wire i2c0_out_data; + wire i2c0_sda; + wire i2c0_out_clk; + wire i2c0_scl_in_clk; + + // adc control gpio assign + + assign shutdown_n = 1; + assign reset_n = gpio_o[32]; + assign gpio_i[63:15] = gpio_o[63:15]; + + // bd gpio + + assign gpio_i[13:8] = gpio_bd_i[5:0]; + assign gpio_bd_o[7:0] = gpio_o[7:0]; + + // IO Buffers for I2C + + ALT_IOBUF scl_video_iobuf ( + .i(1'b0), + .oe(i2c0_out_clk), + .o(i2c0_scl_in_clk), + .io(hdmi_i2c_scl)); + + ALT_IOBUF sda_video_iobuf ( + .i(1'b0), + .oe(i2c0_out_data), + .o(i2c0_sda), + .io(hdmi_i2c_sda)); + + // IO Buffers for DAC I2C + + ALT_IOBUF scl_dac_iobuf ( + .i(1'b0), + .oe(i2c1_out_clk), + .o(i2c1_scl_in_clk), + .io(dac_i2c_scl)); + + ALT_IOBUF sda_dac_iobuf ( + .i(1'b0), + .oe(i2c1_out_data), + .o(i2c1_sda), + .io(dac_i2c_sda)); + + system_bd i_system_bd ( + .sys_clk_clk(sys_clk), + .sys_hps_h2f_reset_reset_n(sys_resetn), + .sys_hps_memory_mem_a(ddr3_a), + .sys_hps_memory_mem_ba(ddr3_ba), + .sys_hps_memory_mem_ck(ddr3_ck_p), + .sys_hps_memory_mem_ck_n(ddr3_ck_n), + .sys_hps_memory_mem_cke(ddr3_cke), + .sys_hps_memory_mem_cs_n(ddr3_cs_n), + .sys_hps_memory_mem_ras_n(ddr3_ras_n), + .sys_hps_memory_mem_cas_n(ddr3_cas_n), + .sys_hps_memory_mem_we_n(ddr3_we_n), + .sys_hps_memory_mem_reset_n(ddr3_reset_n), + .sys_hps_memory_mem_dq(ddr3_dq), + .sys_hps_memory_mem_dqs(ddr3_dqs_p), + .sys_hps_memory_mem_dqs_n(ddr3_dqs_n), + .sys_hps_memory_mem_odt(ddr3_odt), + .sys_hps_memory_mem_dm(ddr3_dm), + .sys_hps_memory_oct_rzqin(ddr3_rzq), + .sys_rst_reset_n(sys_resetn), + .sys_hps_i2c0_out_data(i2c0_out_data), + .sys_hps_i2c0_sda(i2c0_sda), + .sys_hps_i2c0_clk_clk(i2c0_out_clk), + .sys_hps_i2c0_scl_in_clk(i2c0_scl_in_clk), + .sys_hps_hps_io_hps_io_emac1_inst_TX_CLK(eth1_tx_clk), + .sys_hps_hps_io_hps_io_emac1_inst_TXD0(eth1_tx_d[0]), + .sys_hps_hps_io_hps_io_emac1_inst_TXD1(eth1_tx_d[1]), + .sys_hps_hps_io_hps_io_emac1_inst_TXD2(eth1_tx_d[2]), + .sys_hps_hps_io_hps_io_emac1_inst_TXD3(eth1_tx_d[3]), + .sys_hps_hps_io_hps_io_emac1_inst_RXD0(eth1_rx_d[0]), + .sys_hps_hps_io_hps_io_emac1_inst_MDIO(eth1_mdio), + .sys_hps_hps_io_hps_io_emac1_inst_MDC(eth1_mdc), + .sys_hps_hps_io_hps_io_emac1_inst_RX_CTL(eth1_rx_ctl), + .sys_hps_hps_io_hps_io_emac1_inst_TX_CTL(eth1_tx_ctl), + .sys_hps_hps_io_hps_io_emac1_inst_RX_CLK(eth1_rx_clk), + .sys_hps_hps_io_hps_io_emac1_inst_RXD1(eth1_rx_d[1]), + .sys_hps_hps_io_hps_io_emac1_inst_RXD2(eth1_rx_d[2]), + .sys_hps_hps_io_hps_io_emac1_inst_RXD3(eth1_rx_d[3]), + .sys_hps_hps_io_hps_io_sdio_inst_CMD(sdio_cmd), + .sys_hps_hps_io_hps_io_sdio_inst_D0(sdio_d[0]), + .sys_hps_hps_io_hps_io_sdio_inst_D1(sdio_d[1]), + .sys_hps_hps_io_hps_io_sdio_inst_CLK(sdio_clk), + .sys_hps_hps_io_hps_io_sdio_inst_D2(sdio_d[2]), + .sys_hps_hps_io_hps_io_sdio_inst_D3(sdio_d[3]), + .sys_hps_hps_io_hps_io_usb1_inst_D0(usb1_d[0]), + .sys_hps_hps_io_hps_io_usb1_inst_D1(usb1_d[1]), + .sys_hps_hps_io_hps_io_usb1_inst_D2(usb1_d[2]), + .sys_hps_hps_io_hps_io_usb1_inst_D3(usb1_d[3]), + .sys_hps_hps_io_hps_io_usb1_inst_D4(usb1_d[4]), + .sys_hps_hps_io_hps_io_usb1_inst_D5(usb1_d[5]), + .sys_hps_hps_io_hps_io_usb1_inst_D6(usb1_d[6]), + .sys_hps_hps_io_hps_io_usb1_inst_D7(usb1_d[7]), + .sys_hps_hps_io_hps_io_usb1_inst_CLK(usb1_clk), + .sys_hps_hps_io_hps_io_usb1_inst_STP(usb1_stp), + .sys_hps_hps_io_hps_io_usb1_inst_DIR(usb1_dir), + .sys_hps_hps_io_hps_io_usb1_inst_NXT(usb1_nxt), + .sys_hps_hps_io_hps_io_uart0_inst_RX(uart0_rx), + .sys_hps_hps_io_hps_io_uart0_inst_TX(uart0_tx), + .sys_hps_hps_io_hps_io_spim1_inst_CLK(spim1_clk), + .sys_hps_hps_io_hps_io_spim1_inst_MOSI(spim1_mosi), + .sys_hps_hps_io_hps_io_spim1_inst_MISO(spim1_miso), + .sys_hps_hps_io_hps_io_spim1_inst_SS0(spim1_ss0), + .sys_hps_hps_io_hps_io_gpio_inst_GPIO09(hps_conv_usb_n), + .sys_hps_i2c1_sda(i2c1_sda), + .sys_hps_i2c1_out_data(i2c1_out_data), + .sys_hps_i2c1_clk_clk(i2c1_out_clk), + .sys_hps_i2c1_scl_in_clk(i2c1_scl_in_clk), + .sys_gpio_bd_in_port(gpio_i[31:0]), + .sys_gpio_bd_out_port(gpio_o[31:0]), + .sys_gpio_in_export(gpio_i[63:32]), + .sys_gpio_out_export(gpio_o[63:32]), + .sys_spi_MISO(spi_miso), + .sys_spi_MOSI(spi_mosi), + .sys_spi_SCLK(spi_clk), + .sys_spi_SS_n(spi_csn), + .if_clk_in_bd_clk_in(adc_clk_in), + .if_data_in_bd_data_in(adc_data_in), + .if_ready_in_bd_ready_in(adc_ready_in), + .axi_hdmi_tx_0_hdmi_if_h_clk(hdmi_out_clk), + .axi_hdmi_tx_0_hdmi_if_h24_hsync(hdmi_hsync), + .axi_hdmi_tx_0_hdmi_if_h24_vsync(hdmi_vsync), + .axi_hdmi_tx_0_hdmi_if_h24_data_e(hdmi_data_e), + .axi_hdmi_tx_0_hdmi_if_h24_data(hdmi_data)); + +endmodule