diff --git a/library/axi_ad9162/axi_ad9162_channel.v b/library/axi_ad9162/axi_ad9162_channel.v index c15a3a996..d13fd047e 100644 --- a/library/axi_ad9162/axi_ad9162_channel.v +++ b/library/axi_ad9162/axi_ad9162_channel.v @@ -100,8 +100,7 @@ module axi_ad9162_channel ( reg dac_enable = 'd0; reg [255:0] dac_data = 'd0; - reg [255:0] dac_pn7_data = 'd0; - reg [255:0] dac_pn15_data = 'd0; + reg [255:0] dac_data_int = 'd0; reg [ 15:0] dac_dds_phase_00_0 = 'd0; reg [ 15:0] dac_dds_phase_00_1 = 'd0; reg [ 15:0] dac_dds_phase_01_0 = 'd0; @@ -150,65 +149,33 @@ module axi_ad9162_channel ( wire [ 15:0] dac_pat_data_2_s; wire [ 3:0] dac_data_sel_s; wire dac_iq_mode_s; - wire [255:0] dac_pn7_data_i_s; - wire [255:0] dac_pn15_data_i_s; - wire [255:0] dac_pn7_data_s; - wire [255:0] dac_pn15_data_s; wire [255:0] dac_pat_data_s; wire [255:0] dac_dds_data_s; + + // dac sample mux + + always @(posedge dac_clk) begin + dac_data[255:240] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[255:240] : dac_data_int[255:240]; + dac_data[239:224] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[223:208] : dac_data_int[239:224]; + dac_data[223:208] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[239:224] : dac_data_int[223:208]; + dac_data[207:192] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[207:192] : dac_data_int[207:192]; + dac_data[191:176] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[191:176] : dac_data_int[191:176]; + dac_data[175:160] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[159:144] : dac_data_int[175:160]; + dac_data[159:144] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[175:160] : dac_data_int[159:144]; + dac_data[143:128] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[143:128] : dac_data_int[143:128]; + dac_data[127:112] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[127:112] : dac_data_int[127:112]; + dac_data[111: 96] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[ 95: 80] : dac_data_int[111: 96]; + dac_data[ 95: 80] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[111: 96] : dac_data_int[ 95: 80]; + dac_data[ 79: 64] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[ 79: 64] : dac_data_int[ 79: 64]; + dac_data[ 63: 48] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[ 63: 48] : dac_data_int[ 63: 48]; + dac_data[ 47: 32] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[ 31: 16] : dac_data_int[ 47: 32]; + dac_data[ 31: 16] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[ 47: 32] : dac_data_int[ 31: 16]; + dac_data[ 15: 0] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[ 15: 0] : dac_data_int[ 15: 0]; + end + // dac pattern data + genvar n; - - // PN7 function - - function [255:0] pn7; - input [7:0] din; - reg [255:0] dout; - reg [15:0] dout16; - reg [7:0] din_reg; - integer i; - integer j; - begin - din_reg = din; - for ( j=0 ; j<16 ; j=j+1)begin - for ( i=0 ; i<16 ; i= i+1)begin - din_reg = {din_reg,din_reg[6]^din_reg[5]}; - dout16[15-i] = din_reg[0]; - end - dout = {dout16,dout[255:16]}; - end - pn7 = dout; - end - endfunction - - // PN15 function - - function [255:0] pn15; - input [15:0] din; - reg [255:0] dout; - reg [15:0] dout16; - reg [15:0] din_reg; - integer i; - integer j; - begin - din_reg = din; - for (j=0 ; j<16 ; j=j+1)begin - for (i=0 ; i<16 ; i= i+1)begin - din_reg = {din_reg,din_reg[14]^din_reg[13]}; - dout16[15-i] = din_reg[0]; - end - dout = {dout16,dout[255:16]}; - end - pn15 = dout; - end - endfunction - - assign dac_pn7_data_i_s = ~dac_pn7_data; - assign dac_pn15_data_i_s = ~dac_pn15_data; - - assign dac_pn7_data_s = dac_pn7_data; - assign dac_pn15_data_s = dac_pn15_data; - generate for (n = 0; n < 8; n = n + 1) begin: g_dac_pat_data assign dac_pat_data_s[((32*n)+31):((32*n)+16)] = dac_pat_data_2_s; @@ -221,29 +188,13 @@ module axi_ad9162_channel ( always @(posedge dac_clk) begin dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0; case (dac_data_sel_s) - 4'h7: dac_data <= dac_pn15_data_s; - 4'h6: dac_data <= dac_pn7_data_s; - 4'h5: dac_data <= dac_pn15_data_i_s; - 4'h4: dac_data <= dac_pn7_data_i_s; - 4'h3: dac_data <= 256'd0; - 4'h2: dac_data <= dma_data; - 4'h1: dac_data <= dac_pat_data_s; - default: dac_data <= dac_dds_data; + 4'h3: dac_data_int <= 256'd0; + 4'h2: dac_data_int <= dma_data; + 4'h1: dac_data_int <= dac_pat_data_s; + default: dac_data_int <= dac_dds_data; endcase end - // pn registers - - always @(posedge dac_clk) begin - if (dac_data_sync == 1'b1) begin - dac_pn7_data <= {255{1'd1}}; - dac_pn15_data <= {255{1'd1}}; - end else begin - dac_pn7_data <= pn7(dac_pn7_data[247:240]); - dac_pn15_data <= pn15(dac_pn15_data[255:240]); - end - end - // dds always @(posedge dac_clk) begin @@ -358,11 +309,7 @@ module axi_ad9162_channel ( end end - generate - if (DATAPATH_DISABLE == 1) begin - assign dac_dds_data_s[15:0] = 16'd0; - end else begin - ad_dds i_dds_00 ( + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_00 ( .clk (dac_clk), .dds_format (dac_dds_format), .dds_phase_0 (dac_dds_phase_00_0), @@ -370,14 +317,8 @@ module axi_ad9162_channel ( .dds_phase_1 (dac_dds_phase_00_1), .dds_scale_1 (dac_dds_scale_2_s), .dds_data (dac_dds_data_s[15:0])); - end - endgenerate - generate - if (DATAPATH_DISABLE == 1) begin - assign dac_dds_data_s[31:16] = 16'd0; - end else begin - ad_dds i_dds_01 ( + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_01 ( .clk (dac_clk), .dds_format (dac_dds_format), .dds_phase_0 (dac_dds_phase_01_0), @@ -385,14 +326,8 @@ module axi_ad9162_channel ( .dds_phase_1 (dac_dds_phase_01_1), .dds_scale_1 (dac_dds_scale_2_s), .dds_data (dac_dds_data_s[31:16])); - end - endgenerate - generate - if (DATAPATH_DISABLE == 1) begin - assign dac_dds_data_s[47:32] = 16'd0; - end else begin - ad_dds i_dds_02 ( + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_02 ( .clk (dac_clk), .dds_format (dac_dds_format), .dds_phase_0 (dac_dds_phase_02_0), @@ -400,14 +335,8 @@ module axi_ad9162_channel ( .dds_phase_1 (dac_dds_phase_02_1), .dds_scale_1 (dac_dds_scale_2_s), .dds_data (dac_dds_data_s[47:32])); - end - endgenerate - generate - if (DATAPATH_DISABLE == 1) begin - assign dac_dds_data_s[63:48] = 16'd0; - end else begin - ad_dds i_dds_03 ( + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_03 ( .clk (dac_clk), .dds_format (dac_dds_format), .dds_phase_0 (dac_dds_phase_03_0), @@ -415,14 +344,8 @@ module axi_ad9162_channel ( .dds_phase_1 (dac_dds_phase_03_1), .dds_scale_1 (dac_dds_scale_2_s), .dds_data (dac_dds_data_s[63:48])); - end - endgenerate - generate - if (DATAPATH_DISABLE == 1) begin - assign dac_dds_data_s[79:64] = 16'd0; - end else begin - ad_dds i_dds_04 ( + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_04 ( .clk (dac_clk), .dds_format (dac_dds_format), .dds_phase_0 (dac_dds_phase_04_0), @@ -430,14 +353,8 @@ module axi_ad9162_channel ( .dds_phase_1 (dac_dds_phase_04_1), .dds_scale_1 (dac_dds_scale_2_s), .dds_data (dac_dds_data_s[79:64])); - end - endgenerate - generate - if (DATAPATH_DISABLE == 1) begin - assign dac_dds_data_s[95:80] = 16'd0; - end else begin - ad_dds i_dds_05 ( + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_05 ( .clk (dac_clk), .dds_format (dac_dds_format), .dds_phase_0 (dac_dds_phase_05_0), @@ -445,14 +362,8 @@ module axi_ad9162_channel ( .dds_phase_1 (dac_dds_phase_05_1), .dds_scale_1 (dac_dds_scale_2_s), .dds_data (dac_dds_data_s[95:80])); - end - endgenerate - generate - if (DATAPATH_DISABLE == 1) begin - assign dac_dds_data_s[111:96] = 16'd0; - end else begin - ad_dds i_dds_06 ( + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_06 ( .clk (dac_clk), .dds_format (dac_dds_format), .dds_phase_0 (dac_dds_phase_06_0), @@ -460,14 +371,8 @@ module axi_ad9162_channel ( .dds_phase_1 (dac_dds_phase_06_1), .dds_scale_1 (dac_dds_scale_2_s), .dds_data (dac_dds_data_s[111:96])); - end - endgenerate - generate - if (DATAPATH_DISABLE == 1) begin - assign dac_dds_data_s[127:112] = 16'd0; - end else begin - ad_dds i_dds_07 ( + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_07 ( .clk (dac_clk), .dds_format (dac_dds_format), .dds_phase_0 (dac_dds_phase_07_0), @@ -475,14 +380,8 @@ module axi_ad9162_channel ( .dds_phase_1 (dac_dds_phase_07_1), .dds_scale_1 (dac_dds_scale_2_s), .dds_data (dac_dds_data_s[127:112])); - end - endgenerate - generate - if (DATAPATH_DISABLE == 1) begin - assign dac_dds_data_s[143:128] = 16'd0; - end else begin - ad_dds i_dds_08 ( + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_08 ( .clk (dac_clk), .dds_format (dac_dds_format), .dds_phase_0 (dac_dds_phase_08_0), @@ -490,14 +389,8 @@ module axi_ad9162_channel ( .dds_phase_1 (dac_dds_phase_08_1), .dds_scale_1 (dac_dds_scale_2_s), .dds_data (dac_dds_data_s[143:128])); - end - endgenerate - generate - if (DATAPATH_DISABLE == 1) begin - assign dac_dds_data_s[159:144] = 16'd0; - end else begin - ad_dds i_dds_09 ( + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_09 ( .clk (dac_clk), .dds_format (dac_dds_format), .dds_phase_0 (dac_dds_phase_09_0), @@ -505,14 +398,8 @@ module axi_ad9162_channel ( .dds_phase_1 (dac_dds_phase_09_1), .dds_scale_1 (dac_dds_scale_2_s), .dds_data (dac_dds_data_s[159:144])); - end - endgenerate - generate - if (DATAPATH_DISABLE == 1) begin - assign dac_dds_data_s[175:160] = 16'd0; - end else begin - ad_dds i_dds_10 ( + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_10 ( .clk (dac_clk), .dds_format (dac_dds_format), .dds_phase_0 (dac_dds_phase_10_0), @@ -520,14 +407,8 @@ module axi_ad9162_channel ( .dds_phase_1 (dac_dds_phase_10_1), .dds_scale_1 (dac_dds_scale_2_s), .dds_data (dac_dds_data_s[175:160])); - end - endgenerate - generate - if (DATAPATH_DISABLE == 1) begin - assign dac_dds_data_s[191:176] = 16'd0; - end else begin - ad_dds i_dds_11 ( + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_11 ( .clk (dac_clk), .dds_format (dac_dds_format), .dds_phase_0 (dac_dds_phase_11_0), @@ -535,14 +416,8 @@ module axi_ad9162_channel ( .dds_phase_1 (dac_dds_phase_11_1), .dds_scale_1 (dac_dds_scale_2_s), .dds_data (dac_dds_data_s[191:176])); - end - endgenerate - generate - if (DATAPATH_DISABLE == 1) begin - assign dac_dds_data_s[207:192] = 16'd0; - end else begin - ad_dds i_dds_12 ( + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_12 ( .clk (dac_clk), .dds_format (dac_dds_format), .dds_phase_0 (dac_dds_phase_12_0), @@ -550,14 +425,8 @@ module axi_ad9162_channel ( .dds_phase_1 (dac_dds_phase_12_1), .dds_scale_1 (dac_dds_scale_2_s), .dds_data (dac_dds_data_s[207:192])); - end - endgenerate - generate - if (DATAPATH_DISABLE == 1) begin - assign dac_dds_data_s[223:208] = 16'd0; - end else begin - ad_dds i_dds_13 ( + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_13 ( .clk (dac_clk), .dds_format (dac_dds_format), .dds_phase_0 (dac_dds_phase_13_0), @@ -565,14 +434,8 @@ module axi_ad9162_channel ( .dds_phase_1 (dac_dds_phase_13_1), .dds_scale_1 (dac_dds_scale_2_s), .dds_data (dac_dds_data_s[223:208])); - end - endgenerate - generate - if (DATAPATH_DISABLE == 1) begin - assign dac_dds_data_s[239:224] = 16'd0; - end else begin - ad_dds i_dds_14 ( + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_14 ( .clk (dac_clk), .dds_format (dac_dds_format), .dds_phase_0 (dac_dds_phase_14_0), @@ -580,14 +443,8 @@ module axi_ad9162_channel ( .dds_phase_1 (dac_dds_phase_14_1), .dds_scale_1 (dac_dds_scale_2_s), .dds_data (dac_dds_data_s[239:224])); - end - endgenerate - generate - if (DATAPATH_DISABLE == 1) begin - assign dac_dds_data_s[255:240] = 16'd0; - end else begin - ad_dds i_dds_15 ( + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_15 ( .clk (dac_clk), .dds_format (dac_dds_format), .dds_phase_0 (dac_dds_phase_15_0), @@ -595,8 +452,6 @@ module axi_ad9162_channel ( .dds_phase_1 (dac_dds_phase_15_1), .dds_scale_1 (dac_dds_scale_2_s), .dds_data (dac_dds_data_s[255:240])); - end - endgenerate // single channel processor diff --git a/library/axi_ad9162/axi_ad9162_if.v b/library/axi_ad9162/axi_ad9162_if.v index 59362b429..f114420a4 100644 --- a/library/axi_ad9162/axi_ad9162_if.v +++ b/library/axi_ad9162/axi_ad9162_if.v @@ -84,22 +84,22 @@ module axi_ad9162_if ( tx_data[215:208] <= (DEVICE_TYPE == 1) ? dac_data[127:120] : dac_data[191:184]; tx_data[207:200] <= (DEVICE_TYPE == 1) ? dac_data[191:184] : dac_data[127:120]; tx_data[199:192] <= (DEVICE_TYPE == 1) ? dac_data[255:248] : dac_data[ 63: 56]; - tx_data[191:184] <= (DEVICE_TYPE == 1) ? dac_data[ 23: 16] : dac_data[215:208]; - tx_data[183:176] <= (DEVICE_TYPE == 1) ? dac_data[ 87: 80] : dac_data[151:144]; - tx_data[175:168] <= (DEVICE_TYPE == 1) ? dac_data[151:144] : dac_data[ 87: 80]; - tx_data[167:160] <= (DEVICE_TYPE == 1) ? dac_data[215:208] : dac_data[ 23: 16]; - tx_data[159:152] <= (DEVICE_TYPE == 1) ? dac_data[ 31: 24] : dac_data[223:216]; - tx_data[151:144] <= (DEVICE_TYPE == 1) ? dac_data[ 95: 88] : dac_data[159:152]; - tx_data[143:136] <= (DEVICE_TYPE == 1) ? dac_data[159:152] : dac_data[ 95: 88]; - tx_data[135:128] <= (DEVICE_TYPE == 1) ? dac_data[223:216] : dac_data[ 31: 24]; - tx_data[127:120] <= (DEVICE_TYPE == 1) ? dac_data[ 39: 32] : dac_data[231:224]; - tx_data[119:112] <= (DEVICE_TYPE == 1) ? dac_data[103: 96] : dac_data[167:160]; - tx_data[111:104] <= (DEVICE_TYPE == 1) ? dac_data[167:160] : dac_data[103: 96]; - tx_data[103: 96] <= (DEVICE_TYPE == 1) ? dac_data[231:224] : dac_data[ 39: 32]; - tx_data[ 95: 88] <= (DEVICE_TYPE == 1) ? dac_data[ 47: 40] : dac_data[239:232]; - tx_data[ 87: 80] <= (DEVICE_TYPE == 1) ? dac_data[111:104] : dac_data[175:168]; - tx_data[ 79: 72] <= (DEVICE_TYPE == 1) ? dac_data[175:168] : dac_data[111:104]; - tx_data[ 71: 64] <= (DEVICE_TYPE == 1) ? dac_data[239:232] : dac_data[ 47: 40]; + tx_data[191:184] <= (DEVICE_TYPE == 1) ? dac_data[ 39: 32] : dac_data[231:224]; + tx_data[183:176] <= (DEVICE_TYPE == 1) ? dac_data[103: 96] : dac_data[167:160]; + tx_data[175:168] <= (DEVICE_TYPE == 1) ? dac_data[167:160] : dac_data[103: 96]; + tx_data[167:160] <= (DEVICE_TYPE == 1) ? dac_data[231:224] : dac_data[ 39: 32]; + tx_data[159:152] <= (DEVICE_TYPE == 1) ? dac_data[ 47: 40] : dac_data[239:232]; + tx_data[151:144] <= (DEVICE_TYPE == 1) ? dac_data[111:104] : dac_data[175:168]; + tx_data[143:136] <= (DEVICE_TYPE == 1) ? dac_data[175:168] : dac_data[111:104]; + tx_data[135:128] <= (DEVICE_TYPE == 1) ? dac_data[239:232] : dac_data[ 47: 40]; + tx_data[127:120] <= (DEVICE_TYPE == 1) ? dac_data[ 23: 16] : dac_data[215:208]; + tx_data[119:112] <= (DEVICE_TYPE == 1) ? dac_data[ 87: 80] : dac_data[151:144]; + tx_data[111:104] <= (DEVICE_TYPE == 1) ? dac_data[151:144] : dac_data[ 87: 80]; + tx_data[103: 96] <= (DEVICE_TYPE == 1) ? dac_data[215:208] : dac_data[ 23: 16]; + tx_data[ 95: 88] <= (DEVICE_TYPE == 1) ? dac_data[ 31: 24] : dac_data[223:216]; + tx_data[ 87: 80] <= (DEVICE_TYPE == 1) ? dac_data[ 95: 88] : dac_data[159:152]; + tx_data[ 79: 72] <= (DEVICE_TYPE == 1) ? dac_data[159:152] : dac_data[ 95: 88]; + tx_data[ 71: 64] <= (DEVICE_TYPE == 1) ? dac_data[223:216] : dac_data[ 31: 24]; tx_data[ 63: 56] <= (DEVICE_TYPE == 1) ? dac_data[ 7: 0] : dac_data[199:192]; tx_data[ 55: 48] <= (DEVICE_TYPE == 1) ? dac_data[ 71: 64] : dac_data[135:128]; tx_data[ 47: 40] <= (DEVICE_TYPE == 1) ? dac_data[135:128] : dac_data[ 71: 64]; diff --git a/projects/fmcomms11/zc706/system_constr.xdc b/projects/fmcomms11/zc706/system_constr.xdc index 89407b217..a219f9335 100644 --- a/projects/fmcomms11/zc706/system_constr.xdc +++ b/projects/fmcomms11/zc706/system_constr.xdc @@ -67,7 +67,7 @@ set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports ad9162_i create_clock -name tx_ref_clk -period 6.40 [get_ports tx_ref_clk_p] create_clock -name rx_ref_clk -period 6.40 [get_ports rx_ref_clk_p] -create_clock -name tx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcomms11_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK] +create_clock -name tx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_fmcomms11_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK] create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcomms11_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9162_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]