From b90c2e79dc8a46bdf1ab47b8399e3d54872cb39b Mon Sep 17 00:00:00 2001
From: Laszlo Nagy <laszlo.nagy@analog.com>
Date: Thu, 4 Apr 2019 14:53:53 +0100
Subject: [PATCH] jesd204_rx: add parameter for input pipeline stages

Pipeline stages must be implemented on register so placer can spread it
cross the device. Use the shreg_extract attribute to avoid SRL
inference.
---
 library/jesd204/jesd204_common/pipeline_stage.v | 16 ++++++++++++----
 library/jesd204/jesd204_rx/jesd204_rx.v         |  5 +++--
 library/jesd204/jesd204_rx/jesd204_rx_hw.tcl    |  5 +++++
 3 files changed, 20 insertions(+), 6 deletions(-)

diff --git a/library/jesd204/jesd204_common/pipeline_stage.v b/library/jesd204/jesd204_common/pipeline_stage.v
index b4afc025f..43addf231 100644
--- a/library/jesd204/jesd204_common/pipeline_stage.v
+++ b/library/jesd204/jesd204_common/pipeline_stage.v
@@ -50,13 +50,21 @@ module pipeline_stage #(
 ) (
   input clk,
   input [WIDTH-1:0] in,
-  output reg [WIDTH-1:0] out
+  output [WIDTH-1:0] out
 );
 
-generate if (REGISTERED == 1) begin
-  always @(posedge clk) out <= in;
+generate if (REGISTERED == 0) begin
+
+  assign out = in;
+
 end else begin
-  always @(*) out <= in;
+
+  (* shreg_extract = "no" *)  reg [REGISTERED*WIDTH-1:0] in_dly;
+
+  always @(posedge clk) in_dly <= {in_dly,in};
+
+  assign out = in_dly[REGISTERED*WIDTH-1 -: WIDTH];
+
 end endgenerate
 
 endmodule
diff --git a/library/jesd204/jesd204_rx/jesd204_rx.v b/library/jesd204/jesd204_rx/jesd204_rx.v
index 2e74503f8..da471bf58 100644
--- a/library/jesd204/jesd204_rx/jesd204_rx.v
+++ b/library/jesd204/jesd204_rx/jesd204_rx.v
@@ -46,7 +46,8 @@
 
 module jesd204_rx #(
   parameter NUM_LANES = 1,
-  parameter NUM_LINKS = 1
+  parameter NUM_LINKS = 1,
+  parameter NUM_INPUT_PIPELINE = 1
 ) (
   input clk,
   input reset,
@@ -183,7 +184,7 @@ end
 
 pipeline_stage #(
   .WIDTH(3 * CW + DW),
-  .REGISTERED(1)
+  .REGISTERED(NUM_INPUT_PIPELINE)
 ) i_input_pipeline_stage (
   .clk(clk),
   .in({
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_hw.tcl b/library/jesd204/jesd204_rx/jesd204_rx_hw.tcl
index 89b1133e4..4047eaca7 100644
--- a/library/jesd204/jesd204_rx/jesd204_rx_hw.tcl
+++ b/library/jesd204/jesd204_rx/jesd204_rx_hw.tcl
@@ -81,6 +81,11 @@ set_parameter_property NUM_LINKS DISPLAY_NAME "Number of Links"
 set_parameter_property NUM_LINKS ALLOWED_RANGES 1:8
 set_parameter_property NUM_LINKS HDL_PARAMETER true
 
+add_parameter NUM_INPUT_PIPELINE INTEGER 1
+set_parameter_property NUM_INPUT_PIPELINE DISPLAY_NAME "Number of input pipeline stages"
+set_parameter_property NUM_INPUT_PIPELINE ALLOWED_RANGES 1:3
+set_parameter_property NUM_INPUT_PIPELINE HDL_PARAMETER true
+
 #ad_ip_parameter PORT_ENABLE_RX_EOF BOOLEAN false false
 #ad_ip_parameter PORT_ENABLE_LMFC_CLK BOOLEAN false false
 #ad_ip_parameter PORT_ENABLE_LMFC_EDGE BOOLEAN false false