diff --git a/projects/daq3/common/daq3_bd.tcl b/projects/daq3/common/daq3_bd.tcl index c78586bee..cfb78a5b8 100644 --- a/projects/daq3/common/daq3_bd.tcl +++ b/projects/daq3/common/daq3_bd.tcl @@ -17,7 +17,7 @@ create_bd_port -dir O -from 3 -to 0 tx_data_n set axi_ad9152_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9152:1.0 axi_ad9152_core] -set axi_ad9152_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.0 axi_ad9152_jesd] +set axi_ad9152_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9152_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9152_jesd set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9152_jesd @@ -41,7 +41,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9152_upack set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core] -set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.0 axi_ad9680_jesd] +set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9680_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd @@ -65,106 +65,118 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9680_cpack # dac/adc common gt set axi_daq3_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq3_gt] -set_property -dict [list CONFIG.PCORE_NUM_OF_TX_LANES {4}] $axi_daq3_gt -set_property -dict [list CONFIG.PCORE_NUM_OF_RX_LANES {4}] $axi_daq3_gt -set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_0 {0}] $axi_daq3_gt -set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_1 {3}] $axi_daq3_gt -set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_2 {1}] $axi_daq3_gt -set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_3 {2}] $axi_daq3_gt +set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_daq3_gt +set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_daq3_gt +set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $axi_daq3_gt +set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $axi_daq3_gt +set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_daq3_gt +set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_0 {1}] $axi_daq3_gt +set_property -dict [list CONFIG.TX_DATA_SEL_0 {0}] $axi_daq3_gt +set_property -dict [list CONFIG.TX_DATA_SEL_1 {3}] $axi_daq3_gt +set_property -dict [list CONFIG.TX_DATA_SEL_2 {1}] $axi_daq3_gt +set_property -dict [list CONFIG.TX_DATA_SEL_3 {2}] $axi_daq3_gt + +set util_daq3_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_daq3_gt] +set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $util_daq3_gt +set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_daq3_gt +set_property -dict [list CONFIG.NUM_OF_LANES {4}] $util_daq3_gt +set_property -dict [list CONFIG.RX_ENABLE {1}] $util_daq3_gt +set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_daq3_gt +set_property -dict [list CONFIG.TX_ENABLE {1}] $util_daq3_gt +set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $util_daq3_gt # connections (gt) -ad_connect axi_daq3_gt/ref_clk_q rx_ref_clk -ad_connect axi_daq3_gt/ref_clk_c tx_ref_clk -ad_connect axi_daq3_gt/rx_data_p rx_data_p -ad_connect axi_daq3_gt/rx_data_n rx_data_n -ad_connect axi_daq3_gt/rx_sync rx_sync -ad_connect axi_daq3_gt/rx_ext_sysref rx_sysref -ad_connect axi_daq3_gt/tx_data_p tx_data_p -ad_connect axi_daq3_gt/tx_data_n tx_data_n -ad_connect axi_daq3_gt/tx_sync tx_sync -ad_connect axi_daq3_gt/tx_ext_sysref tx_sysref +ad_connect util_daq3_gt/qpll_ref_clk rx_ref_clk +ad_connect util_daq3_gt/cpll_ref_clk tx_ref_clk + +ad_connect axi_daq3_gt/gt_qpll_0 util_daq3_gt/gt_qpll_0 +ad_connect axi_daq3_gt/gt_pll_0 util_daq3_gt/gt_pll_0 +ad_connect axi_daq3_gt/gt_pll_1 util_daq3_gt/gt_pll_1 +ad_connect axi_daq3_gt/gt_pll_2 util_daq3_gt/gt_pll_2 +ad_connect axi_daq3_gt/gt_pll_3 util_daq3_gt/gt_pll_3 +ad_connect axi_daq3_gt/gt_rx_0 util_daq3_gt/gt_rx_0 +ad_connect axi_daq3_gt/gt_rx_1 util_daq3_gt/gt_rx_1 +ad_connect axi_daq3_gt/gt_rx_2 util_daq3_gt/gt_rx_2 +ad_connect axi_daq3_gt/gt_rx_3 util_daq3_gt/gt_rx_3 +ad_connect axi_daq3_gt/gt_rx_ip_0 axi_ad9680_jesd/gt0_rx +ad_connect axi_daq3_gt/gt_rx_ip_1 axi_ad9680_jesd/gt1_rx +ad_connect axi_daq3_gt/gt_rx_ip_2 axi_ad9680_jesd/gt2_rx +ad_connect axi_daq3_gt/gt_rx_ip_3 axi_ad9680_jesd/gt3_rx +ad_connect axi_daq3_gt/rx_gt_comma_align_enb_0 axi_ad9680_jesd/rxencommaalign_out +ad_connect axi_daq3_gt/rx_gt_comma_align_enb_1 axi_ad9680_jesd/rxencommaalign_out +ad_connect axi_daq3_gt/rx_gt_comma_align_enb_2 axi_ad9680_jesd/rxencommaalign_out +ad_connect axi_daq3_gt/rx_gt_comma_align_enb_3 axi_ad9680_jesd/rxencommaalign_out +ad_connect axi_daq3_gt/gt_tx_0 util_daq3_gt/gt_tx_0 +ad_connect axi_daq3_gt/gt_tx_1 util_daq3_gt/gt_tx_1 +ad_connect axi_daq3_gt/gt_tx_2 util_daq3_gt/gt_tx_2 +ad_connect axi_daq3_gt/gt_tx_3 util_daq3_gt/gt_tx_3 +ad_connect axi_daq3_gt/gt_tx_ip_0 axi_ad9152_jesd/gt0_tx +ad_connect axi_daq3_gt/gt_tx_ip_1 axi_ad9152_jesd/gt1_tx +ad_connect axi_daq3_gt/gt_tx_ip_2 axi_ad9152_jesd/gt2_tx +ad_connect axi_daq3_gt/gt_tx_ip_3 axi_ad9152_jesd/gt3_tx # connections (dac) -ad_connect axi_daq3_gt/tx_clk_g axi_daq3_gt/tx_clk -ad_connect axi_daq3_gt/tx_clk_g axi_ad9152_core/tx_clk -ad_connect axi_daq3_gt/tx_clk_g axi_ad9152_jesd/tx_core_clk -ad_connect axi_daq3_gt/tx_clk_g axi_ad9152_upack/dac_clk -ad_connect axi_daq3_gt/tx_rst axi_ad9152_jesd/tx_reset -ad_connect axi_daq3_gt/tx_sysref axi_ad9152_jesd/tx_sysref -ad_connect axi_daq3_gt/tx_gt_charisk_0 axi_ad9152_jesd/gt0_txcharisk -ad_connect axi_daq3_gt/tx_gt_charisk_1 axi_ad9152_jesd/gt1_txcharisk -ad_connect axi_daq3_gt/tx_gt_charisk_2 axi_ad9152_jesd/gt2_txcharisk -ad_connect axi_daq3_gt/tx_gt_charisk_3 axi_ad9152_jesd/gt3_txcharisk -ad_connect axi_daq3_gt/tx_gt_data_0 axi_ad9152_jesd/gt0_txdata -ad_connect axi_daq3_gt/tx_gt_data_1 axi_ad9152_jesd/gt1_txdata -ad_connect axi_daq3_gt/tx_gt_data_2 axi_ad9152_jesd/gt2_txdata -ad_connect axi_daq3_gt/tx_gt_data_3 axi_ad9152_jesd/gt3_txdata -ad_connect axi_daq3_gt/tx_rst_done axi_ad9152_jesd/tx_reset_done -ad_connect axi_daq3_gt/tx_ip_sync axi_ad9152_jesd/tx_sync -ad_connect axi_daq3_gt/tx_ip_sof axi_ad9152_jesd/tx_start_of_frame -ad_connect axi_daq3_gt/tx_ip_data axi_ad9152_jesd/tx_tdata -ad_connect axi_daq3_gt/tx_data axi_ad9152_core/tx_data -ad_connect axi_ad9152_core/dac_valid_0 axi_ad9152_upack/dac_valid_0 +ad_connect util_daq3_gt/tx_sysref tx_sysref +ad_connect util_daq3_gt/tx_p tx_data_p +ad_connect util_daq3_gt/tx_n tx_data_n +ad_connect util_daq3_gt/tx_sync tx_sync +ad_connect util_daq3_gt/tx_out_clk util_daq3_gt/tx_clk +ad_connect util_daq3_gt/tx_out_clk axi_ad9152_jesd/tx_core_clk +ad_connect util_daq3_gt/tx_ip_rst axi_ad9152_jesd/tx_reset +ad_connect util_daq3_gt/tx_ip_rst_done axi_ad9152_jesd/tx_reset_done +ad_connect util_daq3_gt/tx_ip_sysref axi_ad9152_jesd/tx_sysref +ad_connect util_daq3_gt/tx_ip_sync axi_ad9152_jesd/tx_sync +ad_connect util_daq3_gt/tx_ip_data axi_ad9152_jesd/tx_tdata +ad_connect util_daq3_gt/tx_out_clk axi_ad9152_core/tx_clk +ad_connect util_daq3_gt/tx_data axi_ad9152_core/tx_data +ad_connect util_daq3_gt/tx_out_clk axi_ad9152_upack/dac_clk ad_connect axi_ad9152_core/dac_enable_0 axi_ad9152_upack/dac_enable_0 ad_connect axi_ad9152_core/dac_ddata_0 axi_ad9152_upack/dac_data_0 -ad_connect axi_ad9152_core/dac_valid_1 axi_ad9152_upack/dac_valid_1 +ad_connect axi_ad9152_core/dac_valid_0 axi_ad9152_upack/dac_valid_0 ad_connect axi_ad9152_core/dac_enable_1 axi_ad9152_upack/dac_enable_1 ad_connect axi_ad9152_core/dac_ddata_1 axi_ad9152_upack/dac_data_1 -ad_connect sys_cpu_resetn axi_ad9152_dma/m_src_axi_aresetn -ad_connect sys_cpu_clk axi_ad9152_dma/m_axis_aclk -ad_connect axi_ad9152_dma/m_axis_xfer_req axi_ad9152_fifo/dma_xfer_req -ad_connect axi_ad9152_dma/m_axis_aclk axi_ad9152_fifo/dma_clk +ad_connect axi_ad9152_core/dac_valid_1 axi_ad9152_upack/dac_valid_1 +ad_connect util_daq3_gt/tx_out_clk axi_ad9152_fifo/dac_clk +ad_connect axi_ad9152_upack/dac_valid axi_ad9152_fifo/dac_valid +ad_connect axi_ad9152_upack/dac_data axi_ad9152_fifo/dac_data +ad_connect sys_cpu_clk axi_ad9152_fifo/dma_clk ad_connect sys_cpu_reset axi_ad9152_fifo/dma_rst -ad_connect axi_ad9152_dma/m_axis_ready axi_ad9152_fifo/dma_ready -ad_connect axi_ad9152_dma/m_axis_data axi_ad9152_fifo/dma_data -ad_connect axi_ad9152_dma/m_axis_valid axi_ad9152_fifo/dma_valid -ad_connect axi_ad9152_dma/m_axis_last axi_ad9152_fifo/dma_xfer_last -ad_connect axi_ad9152_fifo/dac_clk axi_daq3_gt/tx_clk -ad_connect axi_ad9152_fifo/dac_valid axi_ad9152_upack/dac_valid -ad_connect axi_ad9152_fifo/dac_data axi_ad9152_upack/dac_data +ad_connect sys_cpu_clk axi_ad9152_dma/m_axis_aclk +ad_connect sys_cpu_resetn axi_ad9152_dma/m_src_axi_aresetn +ad_connect axi_ad9152_fifo/dma_xfer_req axi_ad9152_dma/m_axis_xfer_req +ad_connect axi_ad9152_fifo/dma_ready axi_ad9152_dma/m_axis_ready +ad_connect axi_ad9152_fifo/dma_data axi_ad9152_dma/m_axis_data +ad_connect axi_ad9152_fifo/dma_valid axi_ad9152_dma/m_axis_valid +ad_connect axi_ad9152_fifo/dma_xfer_last axi_ad9152_dma/m_axis_last # connections (adc) -ad_connect axi_daq3_gt/rx_clk_g axi_daq3_gt/rx_clk -ad_connect axi_daq3_gt/rx_clk_g axi_ad9680_core/rx_clk -ad_connect axi_daq3_gt/rx_clk_g axi_ad9680_jesd/rx_core_clk -ad_connect axi_daq3_gt/rx_jesd_rst axi_ad9680_jesd/rx_reset -ad_connect axi_daq3_gt/rx_clk_g axi_ad9680_cpack/adc_clk -ad_connect axi_daq3_gt/rx_sysref axi_ad9680_jesd/rx_sysref -ad_connect axi_daq3_gt/rx_gt_charisk_0 axi_ad9680_jesd/gt0_rxcharisk -ad_connect axi_daq3_gt/rx_gt_disperr_0 axi_ad9680_jesd/gt0_rxdisperr -ad_connect axi_daq3_gt/rx_gt_notintable_0 axi_ad9680_jesd/gt0_rxnotintable -ad_connect axi_daq3_gt/rx_gt_data_0 axi_ad9680_jesd/gt0_rxdata -ad_connect axi_daq3_gt/rx_gt_charisk_1 axi_ad9680_jesd/gt1_rxcharisk -ad_connect axi_daq3_gt/rx_gt_disperr_1 axi_ad9680_jesd/gt1_rxdisperr -ad_connect axi_daq3_gt/rx_gt_notintable_1 axi_ad9680_jesd/gt1_rxnotintable -ad_connect axi_daq3_gt/rx_gt_data_1 axi_ad9680_jesd/gt1_rxdata -ad_connect axi_daq3_gt/rx_gt_charisk_2 axi_ad9680_jesd/gt2_rxcharisk -ad_connect axi_daq3_gt/rx_gt_disperr_2 axi_ad9680_jesd/gt2_rxdisperr -ad_connect axi_daq3_gt/rx_gt_notintable_2 axi_ad9680_jesd/gt2_rxnotintable -ad_connect axi_daq3_gt/rx_gt_data_2 axi_ad9680_jesd/gt2_rxdata -ad_connect axi_daq3_gt/rx_gt_charisk_3 axi_ad9680_jesd/gt3_rxcharisk -ad_connect axi_daq3_gt/rx_gt_disperr_3 axi_ad9680_jesd/gt3_rxdisperr -ad_connect axi_daq3_gt/rx_gt_notintable_3 axi_ad9680_jesd/gt3_rxnotintable -ad_connect axi_daq3_gt/rx_gt_data_3 axi_ad9680_jesd/gt3_rxdata -ad_connect axi_daq3_gt/rx_rst_done axi_ad9680_jesd/rx_reset_done -ad_connect axi_daq3_gt/rx_ip_comma_align axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_daq3_gt/rx_ip_sync axi_ad9680_jesd/rx_sync -ad_connect axi_daq3_gt/rx_ip_sof axi_ad9680_jesd/rx_start_of_frame -ad_connect axi_daq3_gt/rx_ip_data axi_ad9680_jesd/rx_tdata -ad_connect axi_daq3_gt/rx_data axi_ad9680_core/rx_data +ad_connect util_daq3_gt/rx_sysref rx_sysref +ad_connect util_daq3_gt/rx_p rx_data_p +ad_connect util_daq3_gt/rx_n rx_data_n +ad_connect util_daq3_gt/rx_sync rx_sync +ad_connect util_daq3_gt/rx_out_clk util_daq3_gt/rx_clk +ad_connect util_daq3_gt/rx_out_clk axi_ad9680_jesd/rx_core_clk +ad_connect util_daq3_gt/rx_ip_rst axi_ad9680_jesd/rx_reset +ad_connect util_daq3_gt/rx_ip_rst_done axi_ad9680_jesd/rx_reset_done +ad_connect util_daq3_gt/rx_ip_sysref axi_ad9680_jesd/rx_sysref +ad_connect util_daq3_gt/rx_ip_sync axi_ad9680_jesd/rx_sync +ad_connect util_daq3_gt/rx_ip_sof axi_ad9680_jesd/rx_start_of_frame +ad_connect util_daq3_gt/rx_ip_data axi_ad9680_jesd/rx_tdata +ad_connect util_daq3_gt/rx_out_clk axi_ad9680_core/rx_clk +ad_connect util_daq3_gt/rx_data axi_ad9680_core/rx_data +ad_connect util_daq3_gt/rx_out_clk axi_ad9680_cpack/adc_clk +ad_connect util_daq3_gt/rx_rst axi_ad9680_cpack/adc_rst ad_connect axi_ad9680_core/adc_enable_0 axi_ad9680_cpack/adc_enable_0 ad_connect axi_ad9680_core/adc_valid_0 axi_ad9680_cpack/adc_valid_0 ad_connect axi_ad9680_core/adc_data_0 axi_ad9680_cpack/adc_data_0 ad_connect axi_ad9680_core/adc_enable_1 axi_ad9680_cpack/adc_enable_1 ad_connect axi_ad9680_core/adc_valid_1 axi_ad9680_cpack/adc_valid_1 ad_connect axi_ad9680_core/adc_data_1 axi_ad9680_cpack/adc_data_1 -ad_connect axi_daq3_gt/rx_rst axi_ad9680_fifo/adc_rst -ad_connect axi_daq3_gt/rx_rst axi_ad9680_cpack/adc_rst -ad_connect axi_ad9680_core/adc_clk axi_ad9680_fifo/adc_clk -ad_connect axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf +ad_connect util_daq3_gt/rx_out_clk axi_ad9680_fifo/adc_clk +ad_connect util_daq3_gt/rx_rst axi_ad9680_fifo/adc_rst ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr ad_connect axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk @@ -174,6 +186,7 @@ ad_connect axi_ad9680_fifo/dma_wr axi_ad9680_dma/s_axis_valid ad_connect axi_ad9680_fifo/dma_wdata axi_ad9680_dma/s_axis_data ad_connect axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready ad_connect axi_ad9680_fifo/dma_xfer_req axi_ad9680_dma/s_axis_xfer_req +ad_connect axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf # interconnect (cpu)