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altera- cmos cores

main
Rejeesh Kutty 2016-10-31 13:13:48 -04:00
parent e0459df0f3
commit b94cc8afb1
3 changed files with 136 additions and 116 deletions
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81
library/altera/common/ad_cmos_out.v
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@ -37,55 +37,38 @@
`timescale 1ns/100ps
module ad_cmos_out (
module __ad_cmos_out__ #(
parameter DEVICE_TYPE = 0,
parameter SINGLE_ENDED = 0,
parameter IODELAY_ENABLE = 0,
parameter IODELAY_CTRL = 0,
parameter IODELAY_GROUP = "dev_if_delay_group") (
// data interface
tx_clk,
tx_data_p,
tx_data_n,
tx_data_out,
input tx_clk,
input tx_data_p,
input tx_data_n,
output tx_data_out,
// delay-data interface
up_clk,
up_dld,
up_dwdata,
up_drdata,
input up_clk,
input up_dld,
input [ 4:0] up_dwdata,
output [ 4:0] up_drdata,
// delay-cntrl interface
delay_clk,
delay_rst,
delay_locked);
input delay_clk,
input delay_rst,
output delay_locked);
// parameters
// local parameter
parameter DEVICE_TYPE = 0;
parameter SINGLE_ENDED = 0;
parameter IODELAY_ENABLE = 0;
parameter IODELAY_CTRL = 0;
parameter IODELAY_GROUP = "dev_if_delay_group";
// data interface
input tx_clk;
input tx_data_p;
input tx_data_n;
output tx_data_out;
// delay-data interface
input up_clk;
input up_dld;
input [ 4:0] up_dwdata;
output [ 4:0] up_drdata;
// delay-cntrl interface
input delay_clk;
input delay_rst;
output delay_locked;
localparam ARRIA10 = 0;
localparam CYCLONE5 = 1;
// defaults
@ -95,8 +78,8 @@ module ad_cmos_out (
// instantiations
generate
if (DEVICE_TYPE == 0) begin
alt_ddio_out i_tx_data_oddr (
if (DEVICE_TYPE == ARRIA10) begin
__ad_cmos_out_1__ i_tx_data_oddr (
.ck (tx_clk),
.din ({tx_data_p, tx_data_n}),
.pad_out (tx_data_out));
@ -104,19 +87,11 @@ module ad_cmos_out (
endgenerate
generate
if (DEVICE_TYPE == 1) begin
altddio_out #(.width (1), .lpm_hint ("UNUSED")) i_tx_data_oddr (
.outclock (tx_clk),
.datain_h (tx_data_p),
.datain_l (tx_data_n),
.dataout (tx_data_out),
.outclocken (1'b1),
.oe_out (),
.oe (1'b1),
.aclr (1'b0),
.aset (1'b0),
.sclr (1'b0),
.sset (1'b0));
if (DEVICE_TYPE == CYCLONE5) begin
ad_cmos_out_core_c5 i_tx_data_oddr (
.clk (tx_clk),
.din ({tx_data_p, tx_data_n}),
.pad_out (tx_data_out));
end
endgenerate

69
library/altera/common/ad_cmos_out_core_c5.v Normal file
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@ -0,0 +1,69 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module ad_cmos_out_core_c5 (
// data interface
input clk,
input [ 1:0] din,
output pad_out);
// instantiations
altddio_out #(
.width (1),
.lpm_hint ("UNUSED"))
i_altddio_out (
.outclock (clk),
.datain_h (din[1]),
.datain_l (din[0]),
.dataout (pad_out),
.outclocken (1'b1),
.oe_out (),
.oe (1'b1),
.aclr (1'b0),
.aset (1'b0),
.sclr (1'b0),
.sset (1'b0));
endmodule
// ***************************************************************************
// ***************************************************************************

102
library/axi_ad9361/altera/axi_ad9361_lvds_if.v
View File

@ -384,9 +384,9 @@ module axi_ad9361_lvds_if #(
// receive data path interface
ad_serdes_in #(
.DATA_WIDTH(6),
.SERDES_FACTOR(4),
.DEVICE_TYPE(DEVICE_TYPE))
.DATA_WIDTH (6),
.SERDES_FACTOR (4),
.DEVICE_TYPE (DEVICE_TYPE))
ad_serdes_data_in (
.rst (mmcm_rst),
.clk (s_clk),
@ -415,9 +415,9 @@ module axi_ad9361_lvds_if #(
// receive frame interface
ad_serdes_in #(
.DATA_WIDTH(1),
.SERDES_FACTOR(4),
.DEVICE_TYPE(DEVICE_TYPE))
.DATA_WIDTH (1),
.SERDES_FACTOR (4),
.DEVICE_TYPE (DEVICE_TYPE))
ad_serdes_frame_in (
.rst (mmcm_rst),
.clk (s_clk),
@ -446,9 +446,9 @@ module axi_ad9361_lvds_if #(
// transmit data interface
ad_serdes_out #(
.DATA_WIDTH(6),
.SERDES_FACTOR(4),
.DEVICE_TYPE(DEVICE_TYPE))
.DATA_WIDTH (6),
.SERDES_FACTOR (4),
.DEVICE_TYPE (DEVICE_TYPE))
ad_serdes_data_out (
.rst (mmcm_rst),
.clk (s_clk),
@ -458,19 +458,19 @@ module axi_ad9361_lvds_if #(
.data_s1 (tx_p_data_d_1),
.data_s2 (tx_p_data_d_2),
.data_s3 (tx_p_data_d_3),
.data_s4 (6'b0),
.data_s5 (6'b0),
.data_s6 (6'b0),
.data_s7 (6'b0),
.data_s4 (6'd0),
.data_s5 (6'd0),
.data_s6 (6'd0),
.data_s7 (6'd0),
.data_out_p (tx_data_out_p),
.data_out_n (tx_data_out_n));
// transmit frame interface
ad_serdes_out #(
.DATA_WIDTH(1),
.SERDES_FACTOR(4),
.DEVICE_TYPE(DEVICE_TYPE))
.DATA_WIDTH (1),
.SERDES_FACTOR (4),
.DEVICE_TYPE (DEVICE_TYPE))
ad_serdes_frame_out (
.rst (mmcm_rst),
.clk (s_clk),
@ -480,10 +480,10 @@ module axi_ad9361_lvds_if #(
.data_s1 (tx_p_frame[1]),
.data_s2 (tx_p_frame[2]),
.data_s3 (tx_p_frame[3]),
.data_s4 (1'b1),
.data_s5 (1'b1),
.data_s6 (1'b1),
.data_s7 (1'b1),
.data_s4 (1'd0),
.data_s5 (1'd0),
.data_s6 (1'd0),
.data_s7 (1'd0),
.data_out_p (tx_frame_out_p),
.data_out_n (tx_frame_out_n));
@ -502,17 +502,17 @@ module axi_ad9361_lvds_if #(
.data_s1 (~dac_clksel),
.data_s2 (dac_clksel),
.data_s3 (~dac_clksel),
.data_s4 (1'b0),
.data_s5 (1'b0),
.data_s6 (1'b0),
.data_s7 (1'b0),
.data_s4 (1'd0),
.data_s5 (1'd0),
.data_s6 (1'd0),
.data_s7 (1'd0),
.data_out_p (tx_clk_out_p),
.data_out_n (tx_clk_out_n));
// serdes clock interface
ad_serdes_clk #(
.DEVICE_TYPE(DEVICE_TYPE))
.DEVICE_TYPE (DEVICE_TYPE))
ad_serdes_clk (
.rst (mmcm_rst),
.clk_in_p (rx_clk_in_p),
@ -534,47 +534,23 @@ module axi_ad9361_lvds_if #(
// enable
ad_serdes_out #(
.DATA_WIDTH(1),
.SERDES_FACTOR(4),
.DEVICE_TYPE(DEVICE_TYPE))
i_enable(
.rst (mmcm_rst),
.clk (s_clk),
.div_clk (l_clk),
.loaden (loaden),
.data_s0 (enable_p_int),
.data_s1 (enable_p_int),
.data_s2 (enable_p_int),
.data_s3 (enable_p_int),
.data_s4 (1'b0),
.data_s5 (1'b0),
.data_s6 (1'b0),
.data_s7 (1'b0),
.data_out_p (enable),
.data_out_n ());
ad_cmos_out #(
.DEVICE_TYPE (DEVICE_TYPE))
i_enable (
.tx_clk (l_clk),
.tx_data_p (enable_p_int),
.tx_data_n (enable_p_int),
.tx_data_out (enable));
// txnrx
ad_serdes_out #(
.DATA_WIDTH(1),
.SERDES_FACTOR(4),
.DEVICE_TYPE(DEVICE_TYPE))
i_txnrx(
.rst (mmcm_rst),
.clk (s_clk),
.div_clk (l_clk),
.loaden (loaden),
.data_s0 (txnrx_p_int),
.data_s1 (txnrx_p_int),
.data_s2 (txnrx_p_int),
.data_s3 (txnrx_p_int),
.data_s4 (1'b0),
.data_s5 (1'b0),
.data_s6 (1'b0),
.data_s7 (1'b0),
.data_out_p (txnrx),
.data_out_n ());
ad_cmos_out #(
.DEVICE_TYPE (DEVICE_TYPE))
i_txnrx (
.tx_clk (l_clk),
.tx_data_p (txnrx_p_int),
.tx_data_n (txnrx_p_int),
.tx_data_out (txnrx));
endmodule