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ad9081_fmca_ebz: Integrate axi_tdd into zcu102 design 

Signed-off-by: David Winter <david.winter@analog.com>
main
David Winter 2021-06-17 15:22:49 +02:00 committed by Laszlo Nagy
parent 58737e09ba
commit b9554a9a5a
4 changed files with 98 additions and 42 deletions
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99
projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
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@ -19,6 +19,15 @@ set JESD_MODE $ad_project_params(JESD_MODE)
set RX_LANE_RATE $ad_project_params(RX_LANE_RATE)
set TX_LANE_RATE $ad_project_params(TX_LANE_RATE)
set TDD_SUPPORT [ expr { [info exists ad_project_params(TDD_SUPPORT)] \
? $ad_project_params(TDD_SUPPORT) : 0 } ]
set SHARED_DEVCLK [ expr { [info exists ad_project_params(SHARED_DEVCLK)] \
? $ad_project_params(SHARED_DEVCLK) : 0 } ]
if {$TDD_SUPPORT && !$SHARED_DEVCLK} {
error "ERROR: Cannot enable TDD support without shared deviceclocks!"
}
if {$JESD_MODE == "8B10B"} {
set DATAPATH_WIDTH 4
set NP12_DATAPATH_WIDTH 6
@ -97,7 +106,7 @@ set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 8* $TX_DATAPATH_WIDTH / ($TX
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
set adc_fifo_name mxfe_adc_fifo
set adc_data_offload_name mxfe_rx_data_offload
set adc_data_width [expr $RX_DMA_SAMPLE_WIDTH*$RX_NUM_OF_CONVERTERS*$RX_SAMPLES_PER_CHANNEL]
set adc_dma_data_width $adc_data_width
set adc_fifo_address_width [expr int(ceil(log(($adc_fifo_samples_per_converter*$RX_NUM_OF_CONVERTERS) / ($adc_data_width/$RX_DMA_SAMPLE_WIDTH))/log(2)))]
@ -158,7 +167,15 @@ ad_ip_instance util_cpack2 util_mxfe_cpack [list \
SAMPLE_DATA_WIDTH $RX_DMA_SAMPLE_WIDTH \
]
ad_adcfifo_create $adc_fifo_name $adc_data_width $adc_dma_data_width $adc_fifo_address_width
set adc_data_offload_size [expr $adc_data_width / 8 * 2**$adc_fifo_address_width]
ad_data_offload_create $adc_data_offload_name \
0 \
0 \
$adc_data_offload_size \
$adc_data_width \
$adc_data_width \
0 0 \
$SHARED_DEVCLK
ad_ip_instance axi_dmac axi_mxfe_rx_dma
ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_TYPE_SRC 1
@ -197,15 +214,15 @@ ad_ip_instance util_upack2 util_mxfe_upack [list \
SAMPLE_DATA_WIDTH $TX_DMA_SAMPLE_WIDTH \
]
set data_offload_size [expr $dac_data_width / 8 * 2**$dac_fifo_address_width]
set dac_data_offload_size [expr $dac_data_width / 8 * 2**$dac_fifo_address_width]
ad_data_offload_create $dac_data_offload_name \
1 \
0 \
$data_offload_size \
$dac_data_offload_size \
$dac_data_width \
$dac_data_width
ad_connect $dac_data_offload_name/sync_ext GND
$dac_data_width \
0 0 \
$SHARED_DEVCLK
ad_ip_instance axi_dmac axi_mxfe_tx_dma
ad_ip_parameter axi_mxfe_tx_dma CONFIG.DMA_TYPE_SRC 0
@ -234,15 +251,15 @@ for {set i 0} {$i < [expr max($TX_NUM_OF_LANES,$RX_NUM_OF_LANES)]} {incr i} {
}
}
ad_xcvrpll axi_mxfe_tx_xcvr/up_pll_rst util_mxfe_xcvr/up_qpll_rst_*
ad_xcvrpll axi_mxfe_rx_xcvr/up_pll_rst util_mxfe_xcvr/up_cpll_rst_*
ad_xcvrpll axi_mxfe_tx_xcvr/up_pll_rst util_mxfe_xcvr/up_qpll_rst_*
ad_xcvrpll axi_mxfe_rx_xcvr/up_pll_rst util_mxfe_xcvr/up_cpll_rst_*
ad_connect $sys_cpu_resetn util_mxfe_xcvr/up_rstn
ad_connect $sys_cpu_clk util_mxfe_xcvr/up_clk
ad_connect $sys_cpu_resetn util_mxfe_xcvr/up_rstn
ad_connect $sys_cpu_clk util_mxfe_xcvr/up_clk
# connections (adc)
ad_xcvrcon util_mxfe_xcvr axi_mxfe_rx_xcvr axi_mxfe_rx_jesd {} {} rx_device_clk
ad_xcvrcon util_mxfe_xcvr axi_mxfe_rx_xcvr axi_mxfe_rx_jesd {} {} rx_device_clk
# connections (dac)
ad_xcvrcon util_mxfe_xcvr axi_mxfe_tx_xcvr axi_mxfe_tx_jesd {} {} tx_device_clk
@ -250,29 +267,33 @@ ad_xcvrcon util_mxfe_xcvr axi_mxfe_tx_xcvr axi_mxfe_tx_jesd {} {} tx_device_clk
# device clock domain
ad_connect rx_device_clk rx_mxfe_tpl_core/link_clk
ad_connect rx_device_clk util_mxfe_cpack/clk
ad_connect rx_device_clk mxfe_adc_fifo/adc_clk
ad_connect rx_device_clk $adc_data_offload_name/s_axis_aclk
ad_connect tx_device_clk tx_mxfe_tpl_core/link_clk
ad_connect tx_device_clk util_mxfe_upack/clk
ad_connect tx_device_clk $dac_data_offload_name/m_axis_aclk
# Clocks
ad_connect $sys_cpu_clk mxfe_adc_fifo/dma_clk
ad_connect $sys_dma_clk $adc_data_offload_name/m_axis_aclk
ad_connect $sys_dma_clk $dac_data_offload_name/s_axis_aclk
ad_connect $sys_cpu_clk axi_mxfe_rx_dma/s_axis_aclk
ad_connect $sys_dma_clk axi_mxfe_rx_dma/s_axis_aclk
ad_connect $sys_dma_clk axi_mxfe_tx_dma/m_axis_aclk
ad_connect $sys_cpu_clk $dac_data_offload_name/s_axi_aclk
ad_connect $sys_cpu_clk $adc_data_offload_name/s_axi_aclk
# Resets
ad_connect rx_device_clk_rstgen/peripheral_reset mxfe_adc_fifo/adc_rst
ad_connect rx_device_clk_rstgen/peripheral_aresetn $adc_data_offload_name/s_axis_aresetn
ad_connect $sys_dma_resetn $adc_data_offload_name/m_axis_aresetn
ad_connect tx_device_clk_rstgen/peripheral_aresetn $dac_data_offload_name/m_axis_aresetn
ad_connect $sys_dma_resetn $dac_data_offload_name/s_axis_aresetn
ad_connect tx_device_clk_rstgen/peripheral_aresetn $dac_data_offload_name/m_axis_aresetn
ad_connect rx_device_clk_rstgen/peripheral_reset util_mxfe_cpack/reset
ad_connect tx_device_clk_rstgen/peripheral_reset util_mxfe_upack/reset
ad_connect $sys_cpu_resetn axi_mxfe_rx_dma/m_dest_axi_aresetn
ad_connect $sys_dma_resetn axi_mxfe_rx_dma/m_dest_axi_aresetn
ad_connect $sys_dma_resetn axi_mxfe_tx_dma/m_src_axi_aresetn
ad_connect $sys_cpu_resetn $dac_data_offload_name/s_axi_aresetn
ad_connect $sys_cpu_resetn $dac_data_offload_name/s_axi_aresetn
ad_connect $sys_cpu_resetn $adc_data_offload_name/s_axi_aresetn
#
# connect adc dataflow
@ -290,13 +311,12 @@ for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
}
ad_connect rx_mxfe_tpl_core/adc_dovf util_mxfe_cpack/fifo_wr_overflow
ad_connect util_mxfe_cpack/packed_fifo_wr_data mxfe_adc_fifo/adc_wdata
ad_connect util_mxfe_cpack/packed_fifo_wr_en mxfe_adc_fifo/adc_wr
ad_connect util_mxfe_cpack/packed_fifo_wr_data $adc_data_offload_name/s_axis_tdata
ad_connect util_mxfe_cpack/packed_fifo_wr_en $adc_data_offload_name/s_axis_tvalid
ad_connect $adc_data_offload_name/s_axis_tlast GND
ad_connect $adc_data_offload_name/s_axis_tkeep VCC
ad_connect mxfe_adc_fifo/dma_wr axi_mxfe_rx_dma/s_axis_valid
ad_connect mxfe_adc_fifo/dma_wdata axi_mxfe_rx_dma/s_axis_data
ad_connect mxfe_adc_fifo/dma_wready axi_mxfe_rx_dma/s_axis_ready
ad_connect mxfe_adc_fifo/dma_xfer_req axi_mxfe_rx_dma/s_axis_xfer_req
ad_connect $adc_data_offload_name/m_axis axi_mxfe_rx_dma/s_axis
# connect dac dataflow
#
@ -317,6 +337,7 @@ ad_connect util_mxfe_upack/s_axis $dac_data_offload_name/m_axis
ad_connect util_mxfe_upack/s_axis_valid VCC
ad_connect $dac_data_offload_name/init_req axi_mxfe_tx_dma/m_axis_xfer_req
ad_connect $adc_data_offload_name/init_req axi_mxfe_rx_dma/s_axis_xfer_req
ad_connect tx_mxfe_tpl_core/dac_dunf GND
# interconnect (cpu)
@ -329,6 +350,8 @@ ad_cpu_interconnect 0x44b90000 axi_mxfe_tx_jesd
ad_cpu_interconnect 0x7c420000 axi_mxfe_rx_dma
ad_cpu_interconnect 0x7c430000 axi_mxfe_tx_dma
ad_cpu_interconnect 0x7c440000 $dac_data_offload_name
ad_cpu_interconnect 0x7c450000 $adc_data_offload_name
# Reserved for TDD! 0x7c460000
# interconnect (gt/adc)
@ -355,3 +378,29 @@ for {set i $RX_NUM_OF_LANES} {$i < 8} {incr i} {
create_bd_port -dir I rx_data_${i}_n
create_bd_port -dir I rx_data_${i}_p
}
if {$TDD_SUPPORT} {
ad_ip_instance util_tdd_sync tdd_sync_0
ad_connect tx_device_clk tdd_sync_0/clk
ad_connect tx_device_clk_rstgen/peripheral_aresetn tdd_sync_0/rstn
ad_connect tdd_sync_0/sync_in GND
ad_connect tdd_sync_0/sync_mode GND
ad_ip_parameter tdd_sync_0 CONFIG.TDD_SYNC_PERIOD 400000000; # More or less 1 PPS ;)
ad_ip_instance axi_tdd axi_tdd_0
ad_connect tx_device_clk axi_tdd_0/clk
ad_connect tx_device_clk_rstgen/peripheral_reset axi_tdd_0/rst
ad_connect $sys_cpu_clk axi_tdd_0/s_axi_aclk
ad_connect $sys_cpu_resetn axi_tdd_0/s_axi_aresetn
ad_cpu_interconnect 0x7c460000 axi_tdd_0
ad_connect tdd_sync_0/sync_out axi_tdd_0/tdd_sync
delete_bd_objs [get_bd_nets mxfe_adc_fifo_dma_wr]
ad_connect $dac_data_offload_name/sync_ext axi_tdd_0/tdd_tx_valid
ad_connect $adc_data_offload_name/sync_ext axi_tdd_0/tdd_rx_valid
} else {
ad_connect $dac_data_offload_name/sync_ext GND
ad_connect $adc_data_offload_name/sync_ext GND
}

4
projects/ad9081_fmca_ebz/zcu102/Makefile
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@ -20,6 +20,7 @@ M_DEPS += ../../../library/common/ad_3w_spi.v
LIB_DEPS += axi_dmac
LIB_DEPS += axi_sysid
LIB_DEPS += axi_tdd
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
LIB_DEPS += jesd204/axi_jesd204_rx
@ -27,10 +28,9 @@ LIB_DEPS += jesd204/axi_jesd204_tx
LIB_DEPS += jesd204/jesd204_rx
LIB_DEPS += jesd204/jesd204_tx
LIB_DEPS += sysid_rom
LIB_DEPS += util_adcfifo
LIB_DEPS += util_dacfifo
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_tdd_sync
LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr
LIB_DEPS += data_offload

28
projects/ad9081_fmca_ebz/zcu102/system_project.tcl
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@ -28,19 +28,21 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
#
adi_project ad9081_fmca_ebz_zcu102 0 [list \
JESD_MODE [get_env_param JESD_MODE 8B10B ]\
RX_LANE_RATE [get_env_param RX_RATE 10 ] \
TX_LANE_RATE [get_env_param TX_RATE 10 ] \
RX_JESD_M [get_env_param RX_JESD_M 8 ] \
RX_JESD_L [get_env_param RX_JESD_L 4 ] \
RX_JESD_S [get_env_param RX_JESD_S 1 ] \
RX_JESD_NP [get_env_param RX_JESD_NP 16] \
RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \
TX_JESD_M [get_env_param TX_JESD_M 8 ] \
TX_JESD_L [get_env_param TX_JESD_L 4 ] \
TX_JESD_S [get_env_param TX_JESD_S 1 ] \
TX_JESD_NP [get_env_param TX_JESD_NP 16] \
TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \
JESD_MODE [get_env_param JESD_MODE 8B10B ] \
RX_LANE_RATE [get_env_param RX_RATE 10 ] \
TX_LANE_RATE [get_env_param TX_RATE 10 ] \
RX_JESD_M [get_env_param RX_JESD_M 8 ] \
RX_JESD_L [get_env_param RX_JESD_L 4 ] \
RX_JESD_S [get_env_param RX_JESD_S 1 ] \
RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \
RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \
TX_JESD_M [get_env_param TX_JESD_M 8 ] \
TX_JESD_L [get_env_param TX_JESD_L 4 ] \
TX_JESD_S [get_env_param TX_JESD_S 1 ] \
TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \
TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \
TDD_SUPPORT [get_env_param TDD_SUPPORT 0 ] \
SHARED_DEVCLK [get_env_param SHARED_DEVCLK 0 ] \
]
adi_project_files ad9081_fmca_ebz_zcu102 [list \

9
projects/ad9081_fmca_ebz/zcu102/system_top.v
View File

@ -40,7 +40,8 @@ module system_top #(
parameter TX_JESD_L = 8,
parameter TX_NUM_LINKS = 1,
parameter RX_JESD_L = 8,
parameter RX_NUM_LINKS = 1
parameter RX_NUM_LINKS = 1,
parameter SHARED_DEVCLK = 0
) (
input [12:0] gpio_bd_i,
@ -109,6 +110,7 @@ module system_top #(
wire clkin6;
wire clkin10;
wire tx_device_clk;
wire rx_device_clk_internal;
wire rx_device_clk;
assign iic_rstn = 1'b1;
@ -161,8 +163,11 @@ module system_top #(
BUFG i_rx_device_clk (
.I (clkin10),
.O (rx_device_clk)
.O (rx_device_clk_internal)
);
assign rx_device_clk = SHARED_DEVCLK ? tx_device_clk : rx_device_clk_internal;
// spi
assign spi0_csb = spi0_csn[0];