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daq2: Use new pack/unpack infrastructure 

Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2018-07-16 11:36:26 +02:00 committed by Adrian Costina
parent 76f6428bfc
commit b9958cac00
9 changed files with 72 additions and 51 deletions
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4
projects/daq2/a10gx/Makefile
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@ -16,8 +16,8 @@ LIB_DEPS += axi_ad9144
LIB_DEPS += axi_ad9680 LIB_DEPS += axi_ad9680
LIB_DEPS += axi_dmac LIB_DEPS += axi_dmac
LIB_DEPS += util_adcfifo LIB_DEPS += util_adcfifo
LIB_DEPS += util_cpack
LIB_DEPS += util_dacfifo LIB_DEPS += util_dacfifo
LIB_DEPS += util_upack LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
include ../../scripts/project-altera.mk include ../../scripts/project-altera.mk

4
projects/daq2/a10soc/Makefile
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@ -18,7 +18,7 @@ LIB_DEPS += axi_ad9144
LIB_DEPS += axi_ad9680 LIB_DEPS += axi_ad9680
LIB_DEPS += axi_dmac LIB_DEPS += axi_dmac
LIB_DEPS += util_adcfifo LIB_DEPS += util_adcfifo
LIB_DEPS += util_cpack LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_upack LIB_DEPS += util_pack/util_upack2
include ../../scripts/project-altera.mk include ../../scripts/project-altera.mk

69
projects/daq2/common/daq2_bd.tcl
View File

@ -13,9 +13,11 @@ adi_axi_jesd204_tx_create axi_ad9144_jesd 4
ad_ip_instance axi_ad9144 axi_ad9144_core ad_ip_instance axi_ad9144 axi_ad9144_core
ad_ip_parameter axi_ad9144_core CONFIG.QUAD_OR_DUAL_N 0 ad_ip_parameter axi_ad9144_core CONFIG.QUAD_OR_DUAL_N 0
ad_ip_instance util_upack axi_ad9144_upack ad_ip_instance util_upack2 axi_ad9144_upack { \
ad_ip_parameter axi_ad9144_upack CONFIG.CHANNEL_DATA_WIDTH 64 NUM_OF_CHANNELS 2 \
ad_ip_parameter axi_ad9144_upack CONFIG.NUM_OF_CHANNELS 2 SAMPLES_PER_CHANNEL 4 \
SAMPLE_DATA_WIDTH 16 \
}
ad_ip_instance axi_dmac axi_ad9144_dma ad_ip_instance axi_dmac axi_ad9144_dma
ad_ip_parameter axi_ad9144_dma CONFIG.DMA_TYPE_SRC 0 ad_ip_parameter axi_ad9144_dma CONFIG.DMA_TYPE_SRC 0
@ -40,9 +42,11 @@ adi_axi_jesd204_rx_create axi_ad9680_jesd 4
ad_ip_instance axi_ad9680 axi_ad9680_core ad_ip_instance axi_ad9680 axi_ad9680_core
ad_ip_instance util_cpack axi_ad9680_cpack ad_ip_instance util_cpack2 axi_ad9680_cpack { \
ad_ip_parameter axi_ad9680_cpack CONFIG.CHANNEL_DATA_WIDTH 64 NUM_OF_CHANNELS 2 \
ad_ip_parameter axi_ad9680_cpack CONFIG.NUM_OF_CHANNELS 2 SAMPLES_PER_CHANNEL 4 \
SAMPLE_DATA_WIDTH 16 \
}
ad_ip_instance axi_dmac axi_ad9680_dma ad_ip_instance axi_dmac axi_ad9680_dma
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_SRC 1 ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_SRC 1
@ -88,22 +92,30 @@ ad_xcvrpll axi_ad9680_xcvr/up_pll_rst util_daq2_xcvr/up_cpll_rst_*
ad_xcvrcon util_daq2_xcvr axi_ad9144_xcvr axi_ad9144_jesd {0 2 3 1} ad_xcvrcon util_daq2_xcvr axi_ad9144_xcvr axi_ad9144_jesd {0 2 3 1}
ad_connect util_daq2_xcvr/tx_out_clk_0 axi_ad9144_core/tx_clk ad_connect util_daq2_xcvr/tx_out_clk_0 axi_ad9144_core/tx_clk
ad_connect axi_ad9144_jesd/tx_data_tdata axi_ad9144_core/tx_data ad_connect axi_ad9144_jesd/tx_data_tdata axi_ad9144_core/tx_data
ad_connect util_daq2_xcvr/tx_out_clk_0 axi_ad9144_upack/dac_clk ad_connect util_daq2_xcvr/tx_out_clk_0 axi_ad9144_upack/clk
ad_connect axi_ad9144_core/dac_enable_0 axi_ad9144_upack/dac_enable_0 ad_connect axi_ad9144_jesd_rstgen/peripheral_reset axi_ad9144_upack/reset
ad_connect axi_ad9144_core/dac_ddata_0 axi_ad9144_upack/dac_data_0
ad_connect axi_ad9144_core/dac_valid_0 axi_ad9144_upack/dac_valid_0
ad_connect axi_ad9144_core/dac_enable_1 axi_ad9144_upack/dac_enable_1 ad_connect axi_ad9144_core/dac_valid_0 axi_ad9144_upack/fifo_rd_en
ad_connect axi_ad9144_core/dac_ddata_1 axi_ad9144_upack/dac_data_1 for {set i 0} {$i < 2} {incr i} {
ad_connect axi_ad9144_core/dac_valid_1 axi_ad9144_upack/dac_valid_1 ad_connect axi_ad9144_core/dac_enable_$i axi_ad9144_upack/enable_$i
ad_connect axi_ad9144_core/dac_ddata_$i axi_ad9144_upack/fifo_rd_data_$i
}
ad_connect util_daq2_xcvr/tx_out_clk_0 axi_ad9144_fifo/dac_clk ad_connect util_daq2_xcvr/tx_out_clk_0 axi_ad9144_fifo/dac_clk
ad_connect axi_ad9144_jesd_rstgen/peripheral_reset axi_ad9144_fifo/dac_rst ad_connect axi_ad9144_jesd_rstgen/peripheral_reset axi_ad9144_fifo/dac_rst
ad_connect axi_ad9144_upack/dac_valid axi_ad9144_fifo/dac_valid
ad_connect axi_ad9144_upack/dac_data axi_ad9144_fifo/dac_data # TODO: Add streaming AXI interface for DAC FIFO
ad_connect axi_ad9144_upack/s_axis_valid VCC
ad_connect axi_ad9144_upack/s_axis_ready axi_ad9144_fifo/dac_valid
ad_connect axi_ad9144_upack/s_axis_data axi_ad9144_fifo/dac_data
ad_connect axi_ad9144_core/dac_dunf axi_ad9144_fifo/dac_dunf ad_connect axi_ad9144_core/dac_dunf axi_ad9144_fifo/dac_dunf
ad_connect sys_cpu_clk axi_ad9144_fifo/dma_clk ad_connect sys_cpu_clk axi_ad9144_fifo/dma_clk
ad_connect sys_cpu_reset axi_ad9144_fifo/dma_rst ad_connect sys_cpu_reset axi_ad9144_fifo/dma_rst
ad_connect sys_cpu_clk axi_ad9144_dma/m_axis_aclk ad_connect sys_cpu_clk axi_ad9144_dma/m_axis_aclk
ad_connect sys_cpu_resetn axi_ad9144_dma/m_src_axi_aresetn ad_connect sys_cpu_resetn axi_ad9144_dma/m_src_axi_aresetn
ad_connect axi_ad9144_fifo/dma_xfer_req axi_ad9144_dma/m_axis_xfer_req ad_connect axi_ad9144_fifo/dma_xfer_req axi_ad9144_dma/m_axis_xfer_req
ad_connect axi_ad9144_fifo/dma_ready axi_ad9144_dma/m_axis_ready ad_connect axi_ad9144_fifo/dma_ready axi_ad9144_dma/m_axis_ready
ad_connect axi_ad9144_fifo/dma_data axi_ad9144_dma/m_axis_data ad_connect axi_ad9144_fifo/dma_data axi_ad9144_dma/m_axis_data
@ -116,18 +128,24 @@ ad_xcvrcon util_daq2_xcvr axi_ad9680_xcvr axi_ad9680_jesd
ad_connect util_daq2_xcvr/rx_out_clk_0 axi_ad9680_core/rx_clk ad_connect util_daq2_xcvr/rx_out_clk_0 axi_ad9680_core/rx_clk
ad_connect axi_ad9680_jesd/rx_sof axi_ad9680_core/rx_sof ad_connect axi_ad9680_jesd/rx_sof axi_ad9680_core/rx_sof
ad_connect axi_ad9680_jesd/rx_data_tdata axi_ad9680_core/rx_data ad_connect axi_ad9680_jesd/rx_data_tdata axi_ad9680_core/rx_data
ad_connect util_daq2_xcvr/rx_out_clk_0 axi_ad9680_cpack/adc_clk
ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/adc_rst ad_connect util_daq2_xcvr/rx_out_clk_0 axi_ad9680_cpack/clk
ad_connect axi_ad9680_core/adc_enable_0 axi_ad9680_cpack/adc_enable_0 ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/reset
ad_connect axi_ad9680_core/adc_valid_0 axi_ad9680_cpack/adc_valid_0
ad_connect axi_ad9680_core/adc_data_0 axi_ad9680_cpack/adc_data_0 ad_connect axi_ad9680_core/adc_valid_0 axi_ad9680_cpack/fifo_wr_en
ad_connect axi_ad9680_core/adc_enable_1 axi_ad9680_cpack/adc_enable_1 ad_connect axi_ad9680_core/adc_enable_0 axi_ad9680_cpack/enable_0
ad_connect axi_ad9680_core/adc_valid_1 axi_ad9680_cpack/adc_valid_1 ad_connect axi_ad9680_core/adc_data_0 axi_ad9680_cpack/fifo_wr_data_0
ad_connect axi_ad9680_core/adc_data_1 axi_ad9680_cpack/adc_data_1 ad_connect axi_ad9680_core/adc_enable_1 axi_ad9680_cpack/enable_1
ad_connect axi_ad9680_core/adc_data_1 axi_ad9680_cpack/fifo_wr_data_1
ad_connect axi_ad9680_core/adc_dovf axi_ad9680_cpack/fifo_wr_overflow
ad_connect util_daq2_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk ad_connect util_daq2_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk
ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst
ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr
ad_connect axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata ad_connect axi_ad9680_cpack/packed_fifo_wr_en axi_ad9680_fifo/adc_wr
ad_connect axi_ad9680_cpack/packed_fifo_wr_data axi_ad9680_fifo/adc_wdata
ad_connect axi_ad9680_cpack/packed_fifo_wr_overflow axi_ad9680_fifo/adc_wovf
ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk
ad_connect sys_cpu_clk axi_ad9680_dma/s_axis_aclk ad_connect sys_cpu_clk axi_ad9680_dma/s_axis_aclk
ad_connect sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn ad_connect sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn
@ -135,7 +153,6 @@ ad_connect axi_ad9680_fifo/dma_wr axi_ad9680_dma/s_axis_valid
ad_connect axi_ad9680_fifo/dma_wdata axi_ad9680_dma/s_axis_data ad_connect axi_ad9680_fifo/dma_wdata axi_ad9680_dma/s_axis_data
ad_connect axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready ad_connect axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready
ad_connect axi_ad9680_fifo/dma_xfer_req axi_ad9680_dma/s_axis_xfer_req ad_connect axi_ad9680_fifo/dma_xfer_req axi_ad9680_dma/s_axis_xfer_req
ad_connect axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf
# interconnect (cpu) # interconnect (cpu)

26
projects/daq2/common/daq2_qsys.tcl
View File

@ -32,11 +32,14 @@ add_connection sys_clk.clk axi_ad9144_core.s_axi_clock
# ad9144-unpack # ad9144-unpack
add_instance util_ad9144_upack util_upack add_instance util_ad9144_upack util_upack2
set_instance_parameter_value util_ad9144_upack {CHANNEL_DATA_WIDTH} {64}
set_instance_parameter_value util_ad9144_upack {NUM_OF_CHANNELS} {2} set_instance_parameter_value util_ad9144_upack {NUM_OF_CHANNELS} {2}
set_instance_parameter_value util_ad9144_upack {SAMPLES_PER_CHANNEL} {4}
set_instance_parameter_value util_ad9144_upack {SAMPLE_DATA_WIDTH} {16}
set_instance_parameter_value util_ad9144_upack {INTERFACE_TYPE} {1}
add_connection ad9144_jesd204.link_clk util_ad9144_upack.if_dac_clk add_connection ad9144_jesd204.link_clk util_ad9144_upack.clk
add_connection ad9144_jesd204.link_reset util_ad9144_upack.reset
add_connection axi_ad9144_core.dac_ch_0 util_ad9144_upack.dac_ch_0 add_connection axi_ad9144_core.dac_ch_0 util_ad9144_upack.dac_ch_0
add_connection axi_ad9144_core.dac_ch_1 util_ad9144_upack.dac_ch_1 add_connection axi_ad9144_core.dac_ch_1 util_ad9144_upack.dac_ch_1
@ -47,8 +50,8 @@ set_interface_property tx_fifo_bypass EXPORT_OF avl_ad9144_fifo.if_bypass
add_connection ad9144_jesd204.link_clk avl_ad9144_fifo.if_dac_clk add_connection ad9144_jesd204.link_clk avl_ad9144_fifo.if_dac_clk
add_connection ad9144_jesd204.link_reset avl_ad9144_fifo.if_dac_rst add_connection ad9144_jesd204.link_reset avl_ad9144_fifo.if_dac_rst
add_connection util_ad9144_upack.if_dac_valid avl_ad9144_fifo.if_dac_valid add_connection util_ad9144_upack.if_packed_fifo_rd_en avl_ad9144_fifo.if_dac_valid
add_connection avl_ad9144_fifo.if_dac_data util_ad9144_upack.if_dac_data add_connection avl_ad9144_fifo.if_dac_data util_ad9144_upack.if_packed_fifo_rd_data
add_connection avl_ad9144_fifo.if_dac_dunf axi_ad9144_core.if_dac_dunf add_connection avl_ad9144_fifo.if_dac_dunf axi_ad9144_core.if_dac_dunf
# ad9144-dma # ad9144-dma
@ -113,12 +116,13 @@ add_connection sys_clk.clk axi_ad9680_core.s_axi_clock
# ad9680-pack # ad9680-pack
add_instance util_ad9680_cpack util_cpack add_instance util_ad9680_cpack util_cpack2
set_instance_parameter_value util_ad9680_cpack {CHANNEL_DATA_WIDTH} {64}
set_instance_parameter_value util_ad9680_cpack {NUM_OF_CHANNELS} {2} set_instance_parameter_value util_ad9680_cpack {NUM_OF_CHANNELS} {2}
set_instance_parameter_value util_ad9680_cpack {SAMPLES_PER_CHANNEL} {4}
set_instance_parameter_value util_ad9680_cpack {SAMPLE_DATA_WIDTH} {16}
add_connection sys_clk.clk_reset util_ad9680_cpack.if_adc_rst add_connection ad9680_jesd204.link_reset util_ad9680_cpack.reset
add_connection ad9680_jesd204.link_clk util_ad9680_cpack.if_adc_clk add_connection ad9680_jesd204.link_clk util_ad9680_cpack.clk
add_connection axi_ad9680_core.adc_ch_0 util_ad9680_cpack.adc_ch_0 add_connection axi_ad9680_core.adc_ch_0 util_ad9680_cpack.adc_ch_0
add_connection axi_ad9680_core.adc_ch_1 util_ad9680_cpack.adc_ch_1 add_connection axi_ad9680_core.adc_ch_1 util_ad9680_cpack.adc_ch_1
@ -131,8 +135,8 @@ set_instance_parameter_value ad9680_adcfifo {DMA_ADDRESS_WIDTH} {16}
add_connection sys_clk.clk_reset ad9680_adcfifo.if_adc_rst add_connection sys_clk.clk_reset ad9680_adcfifo.if_adc_rst
add_connection ad9680_jesd204.link_clk ad9680_adcfifo.if_adc_clk add_connection ad9680_jesd204.link_clk ad9680_adcfifo.if_adc_clk
add_connection util_ad9680_cpack.if_adc_valid ad9680_adcfifo.if_adc_wr add_connection util_ad9680_cpack.if_packed_fifo_wr_en ad9680_adcfifo.if_adc_wr
add_connection util_ad9680_cpack.if_adc_data ad9680_adcfifo.if_adc_wdata add_connection util_ad9680_cpack.if_packed_fifo_wr_data ad9680_adcfifo.if_adc_wdata
add_connection sys_dma_clk.clk ad9680_adcfifo.if_dma_clk add_connection sys_dma_clk.clk ad9680_adcfifo.if_dma_clk
add_connection sys_dma_clk.clk_reset ad9680_adcfifo.if_adc_rst add_connection sys_dma_clk.clk_reset ad9680_adcfifo.if_adc_rst

4
projects/daq2/kc705/Makefile
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@ -23,9 +23,9 @@ LIB_DEPS += jesd204/axi_jesd204_tx
LIB_DEPS += jesd204/jesd204_rx LIB_DEPS += jesd204/jesd204_rx
LIB_DEPS += jesd204/jesd204_tx LIB_DEPS += jesd204/jesd204_tx
LIB_DEPS += util_adcfifo LIB_DEPS += util_adcfifo
LIB_DEPS += util_cpack
LIB_DEPS += util_dacfifo LIB_DEPS += util_dacfifo
LIB_DEPS += util_upack LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += xilinx/axi_adxcvr LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr LIB_DEPS += xilinx/util_adxcvr

4
projects/daq2/kcu105/Makefile
View File

@ -22,9 +22,9 @@ LIB_DEPS += jesd204/axi_jesd204_tx
LIB_DEPS += jesd204/jesd204_rx LIB_DEPS += jesd204/jesd204_rx
LIB_DEPS += jesd204/jesd204_tx LIB_DEPS += jesd204/jesd204_tx
LIB_DEPS += util_adcfifo LIB_DEPS += util_adcfifo
LIB_DEPS += util_cpack
LIB_DEPS += util_dacfifo LIB_DEPS += util_dacfifo
LIB_DEPS += util_upack LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += xilinx/axi_adxcvr LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr LIB_DEPS += xilinx/util_adxcvr

4
projects/daq2/vc707/Makefile
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@ -23,9 +23,9 @@ LIB_DEPS += jesd204/axi_jesd204_tx
LIB_DEPS += jesd204/jesd204_rx LIB_DEPS += jesd204/jesd204_rx
LIB_DEPS += jesd204/jesd204_tx LIB_DEPS += jesd204/jesd204_tx
LIB_DEPS += util_adcfifo LIB_DEPS += util_adcfifo
LIB_DEPS += util_cpack
LIB_DEPS += util_dacfifo LIB_DEPS += util_dacfifo
LIB_DEPS += util_upack LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += xilinx/axi_adxcvr LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr LIB_DEPS += xilinx/util_adxcvr

4
projects/daq2/zc706/Makefile
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@ -25,9 +25,9 @@ LIB_DEPS += jesd204/axi_jesd204_rx
LIB_DEPS += jesd204/axi_jesd204_tx LIB_DEPS += jesd204/axi_jesd204_tx
LIB_DEPS += jesd204/jesd204_rx LIB_DEPS += jesd204/jesd204_rx
LIB_DEPS += jesd204/jesd204_tx LIB_DEPS += jesd204/jesd204_tx
LIB_DEPS += util_cpack
LIB_DEPS += util_dacfifo LIB_DEPS += util_dacfifo
LIB_DEPS += util_upack LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += xilinx/axi_adcfifo LIB_DEPS += xilinx/axi_adcfifo
LIB_DEPS += xilinx/axi_adxcvr LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr LIB_DEPS += xilinx/util_adxcvr

4
projects/daq2/zcu102/Makefile
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@ -22,9 +22,9 @@ LIB_DEPS += jesd204/axi_jesd204_tx
LIB_DEPS += jesd204/jesd204_rx LIB_DEPS += jesd204/jesd204_rx
LIB_DEPS += jesd204/jesd204_tx LIB_DEPS += jesd204/jesd204_tx
LIB_DEPS += util_adcfifo LIB_DEPS += util_adcfifo
LIB_DEPS += util_cpack
LIB_DEPS += util_dacfifo LIB_DEPS += util_dacfifo
LIB_DEPS += util_upack LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += xilinx/axi_adxcvr LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr LIB_DEPS += xilinx/util_adxcvr