diff --git a/projects/daq3/common/daq3_bd.tcl b/projects/daq3/common/daq3_bd.tcl index d8d7dc6be..35ded3e5f 100644 --- a/projects/daq3/common/daq3_bd.tcl +++ b/projects/daq3/common/daq3_bd.tcl @@ -1,20 +1,13 @@ -# daq3 - -create_bd_port -dir I rx_ref_clk -create_bd_port -dir O rx_sync -create_bd_port -dir I rx_sysref -create_bd_port -dir I -from 3 -to 0 rx_data_p -create_bd_port -dir I -from 3 -to 0 rx_data_n - -create_bd_port -dir I tx_ref_clk -create_bd_port -dir I tx_sync -create_bd_port -dir I tx_sysref -create_bd_port -dir O -from 3 -to 0 tx_data_p -create_bd_port -dir O -from 3 -to 0 tx_data_n - # dac peripherals +set axi_ad9152_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9152_xcvr] +set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9152_xcvr +set_property -dict [list CONFIG.QPLL_ENABLE {1}] $axi_ad9152_xcvr +set_property -dict [list CONFIG.TX_OR_RX_N {1}] $axi_ad9152_xcvr + +set sys_ad9152_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_ad9152_rstgen] + set axi_ad9152_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9152:1.0 axi_ad9152_core] set axi_ad9152_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9152_jesd] @@ -39,6 +32,13 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9152_upack # adc peripherals +set axi_ad9680_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9680_xcvr] +set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9680_xcvr +set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9680_xcvr +set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9680_xcvr + +set sys_ad9680_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_ad9680_rstgen] + set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core] set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9680_jesd] @@ -62,85 +62,32 @@ set axi_ad9680_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1 set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9680_cpack set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9680_cpack -# dac/adc common gt +# shared transceiver core -set axi_daq3_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq3_gt] -set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_daq3_gt -set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_daq3_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $axi_daq3_gt -set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $axi_daq3_gt -set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_daq3_gt -set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_0 {1}] $axi_daq3_gt -set_property -dict [list CONFIG.TX_DATA_SEL_0 {0}] $axi_daq3_gt -set_property -dict [list CONFIG.TX_DATA_SEL_1 {3}] $axi_daq3_gt -set_property -dict [list CONFIG.TX_DATA_SEL_2 {1}] $axi_daq3_gt -set_property -dict [list CONFIG.TX_DATA_SEL_3 {2}] $axi_daq3_gt +set util_daq3_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_daq3_xcvr] +set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_daq3_xcvr +set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $util_daq3_xcvr -set util_daq3_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_daq3_gt] -set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $util_daq3_gt -set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_daq3_gt -set_property -dict [list CONFIG.NUM_OF_LANES {4}] $util_daq3_gt -set_property -dict [list CONFIG.RX_ENABLE {1}] $util_daq3_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_daq3_gt -set_property -dict [list CONFIG.TX_ENABLE {1}] $util_daq3_gt -set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $util_daq3_gt - -# connections (gt) - -ad_connect util_daq3_gt/qpll_ref_clk rx_ref_clk -ad_connect util_daq3_gt/cpll_ref_clk tx_ref_clk - -ad_connect axi_daq3_gt/gt_qpll_0 util_daq3_gt/gt_qpll_0 -ad_connect axi_daq3_gt/gt_pll_0 util_daq3_gt/gt_pll_0 -ad_connect axi_daq3_gt/gt_pll_1 util_daq3_gt/gt_pll_1 -ad_connect axi_daq3_gt/gt_pll_2 util_daq3_gt/gt_pll_2 -ad_connect axi_daq3_gt/gt_pll_3 util_daq3_gt/gt_pll_3 -ad_connect axi_daq3_gt/gt_rx_0 util_daq3_gt/gt_rx_0 -ad_connect axi_daq3_gt/gt_rx_1 util_daq3_gt/gt_rx_1 -ad_connect axi_daq3_gt/gt_rx_2 util_daq3_gt/gt_rx_2 -ad_connect axi_daq3_gt/gt_rx_3 util_daq3_gt/gt_rx_3 -ad_connect axi_daq3_gt/gt_rx_ip_0 axi_ad9680_jesd/gt0_rx -ad_connect axi_daq3_gt/gt_rx_ip_1 axi_ad9680_jesd/gt1_rx -ad_connect axi_daq3_gt/gt_rx_ip_2 axi_ad9680_jesd/gt2_rx -ad_connect axi_daq3_gt/gt_rx_ip_3 axi_ad9680_jesd/gt3_rx -ad_connect axi_daq3_gt/rx_gt_comma_align_enb_0 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_daq3_gt/rx_gt_comma_align_enb_1 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_daq3_gt/rx_gt_comma_align_enb_2 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_daq3_gt/rx_gt_comma_align_enb_3 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_daq3_gt/gt_tx_0 util_daq3_gt/gt_tx_0 -ad_connect axi_daq3_gt/gt_tx_1 util_daq3_gt/gt_tx_1 -ad_connect axi_daq3_gt/gt_tx_2 util_daq3_gt/gt_tx_2 -ad_connect axi_daq3_gt/gt_tx_3 util_daq3_gt/gt_tx_3 -ad_connect axi_daq3_gt/gt_tx_ip_0 axi_ad9152_jesd/gt0_tx -ad_connect axi_daq3_gt/gt_tx_ip_1 axi_ad9152_jesd/gt1_tx -ad_connect axi_daq3_gt/gt_tx_ip_2 axi_ad9152_jesd/gt2_tx -ad_connect axi_daq3_gt/gt_tx_ip_3 axi_ad9152_jesd/gt3_tx +ad_connect sys_cpu_resetn util_daq3_xcvr/up_rstn +ad_connect sys_cpu_clk util_daq3_xcvr/up_clk # connections (dac) -ad_connect util_daq3_gt/tx_sysref tx_sysref -ad_connect util_daq3_gt/tx_p tx_data_p -ad_connect util_daq3_gt/tx_n tx_data_n -ad_connect util_daq3_gt/tx_sync tx_sync -ad_connect util_daq3_gt/tx_out_clk util_daq3_gt/tx_clk -ad_connect util_daq3_gt/tx_out_clk axi_ad9152_jesd/tx_core_clk -ad_connect util_daq3_gt/tx_ip_rst axi_ad9152_jesd/tx_reset -ad_connect util_daq3_gt/tx_ip_rst_done axi_ad9152_jesd/tx_reset_done -ad_connect util_daq3_gt/tx_ip_sysref axi_ad9152_jesd/tx_sysref -ad_connect util_daq3_gt/tx_ip_sync axi_ad9152_jesd/tx_sync -ad_connect util_daq3_gt/tx_ip_data axi_ad9152_jesd/tx_tdata -ad_connect util_daq3_gt/tx_out_clk axi_ad9152_core/tx_clk -ad_connect util_daq3_gt/tx_data axi_ad9152_core/tx_data -ad_connect util_daq3_gt/tx_out_clk axi_ad9152_upack/dac_clk +ad_xcvrcon util_daq3_xcvr axi_ad9152_xcvr axi_ad9152_jesd +ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_core/tx_clk +ad_connect axi_ad9152_jesd/tx_tdata axi_ad9152_core/tx_data +ad_connect util_daq3_xcvr/tx_out_clk_0 sys_ad9152_rstgen/slowest_sync_clk +ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_fifo/dac_clk +ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_upack/dac_clk ad_connect axi_ad9152_core/dac_enable_0 axi_ad9152_upack/dac_enable_0 ad_connect axi_ad9152_core/dac_ddata_0 axi_ad9152_upack/dac_data_0 ad_connect axi_ad9152_core/dac_valid_0 axi_ad9152_upack/dac_valid_0 ad_connect axi_ad9152_core/dac_enable_1 axi_ad9152_upack/dac_enable_1 ad_connect axi_ad9152_core/dac_ddata_1 axi_ad9152_upack/dac_data_1 ad_connect axi_ad9152_core/dac_valid_1 axi_ad9152_upack/dac_valid_1 -ad_connect util_daq3_gt/tx_out_clk axi_ad9152_fifo/dac_clk ad_connect axi_ad9152_upack/dac_valid axi_ad9152_fifo/dac_valid ad_connect axi_ad9152_upack/dac_data axi_ad9152_fifo/dac_data +ad_connect axi_ad9152_upack/dma_xfer_in axi_ad9152_fifo/dac_xfer_out ad_connect sys_cpu_clk axi_ad9152_fifo/dma_clk ad_connect sys_cpu_reset axi_ad9152_fifo/dma_rst ad_connect sys_cpu_clk axi_ad9152_dma/m_axis_aclk @@ -153,30 +100,21 @@ ad_connect axi_ad9152_fifo/dma_xfer_last axi_ad9152_dma/m_axis_last # connections (adc) -ad_connect util_daq3_gt/rx_sysref rx_sysref -ad_connect util_daq3_gt/rx_p rx_data_p -ad_connect util_daq3_gt/rx_n rx_data_n -ad_connect util_daq3_gt/rx_sync rx_sync -ad_connect util_daq3_gt/rx_out_clk util_daq3_gt/rx_clk -ad_connect util_daq3_gt/rx_out_clk axi_ad9680_jesd/rx_core_clk -ad_connect util_daq3_gt/rx_ip_rst axi_ad9680_jesd/rx_reset -ad_connect util_daq3_gt/rx_ip_rst_done axi_ad9680_jesd/rx_reset_done -ad_connect util_daq3_gt/rx_ip_sysref axi_ad9680_jesd/rx_sysref -ad_connect util_daq3_gt/rx_ip_sync axi_ad9680_jesd/rx_sync -ad_connect util_daq3_gt/rx_ip_sof axi_ad9680_jesd/rx_start_of_frame -ad_connect util_daq3_gt/rx_ip_data axi_ad9680_jesd/rx_tdata -ad_connect util_daq3_gt/rx_out_clk axi_ad9680_core/rx_clk -ad_connect util_daq3_gt/rx_data axi_ad9680_core/rx_data -ad_connect util_daq3_gt/rx_out_clk axi_ad9680_cpack/adc_clk -ad_connect util_daq3_gt/rx_rst axi_ad9680_cpack/adc_rst +ad_xcvrcon util_daq3_xcvr axi_ad9680_xcvr axi_ad9680_jesd +ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_core/rx_clk +ad_connect axi_ad9680_jesd/rx_start_of_frame axi_ad9680_core/rx_sof +ad_connect axi_ad9680_jesd/rx_tdata axi_ad9680_core/rx_data +ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk +ad_connect util_daq3_xcvr/tx_out_clk_0 sys_ad9680_rstgen/slowest_sync_clk +ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst +ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_cpack/adc_clk +ad_connect sys_ad9680_rstgen/peripheral_reset axi_ad9680_cpack/adc_rst ad_connect axi_ad9680_core/adc_enable_0 axi_ad9680_cpack/adc_enable_0 ad_connect axi_ad9680_core/adc_valid_0 axi_ad9680_cpack/adc_valid_0 ad_connect axi_ad9680_core/adc_data_0 axi_ad9680_cpack/adc_data_0 ad_connect axi_ad9680_core/adc_enable_1 axi_ad9680_cpack/adc_enable_1 ad_connect axi_ad9680_core/adc_valid_1 axi_ad9680_cpack/adc_valid_1 ad_connect axi_ad9680_core/adc_data_1 axi_ad9680_cpack/adc_data_1 -ad_connect util_daq3_gt/rx_out_clk axi_ad9680_fifo/adc_clk -ad_connect util_daq3_gt/rx_rst axi_ad9680_fifo/adc_rst ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr ad_connect axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk @@ -190,10 +128,11 @@ ad_connect axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf # interconnect (cpu) -ad_cpu_interconnect 0x44A60000 axi_daq3_gt +ad_cpu_interconnect 0x44A60000 axi_ad9152_xcvr ad_cpu_interconnect 0x44A00000 axi_ad9152_core ad_cpu_interconnect 0x44A90000 axi_ad9152_jesd ad_cpu_interconnect 0x7c420000 axi_ad9152_dma +ad_cpu_interconnect 0x44A50000 axi_ad9680_xcvr ad_cpu_interconnect 0x44A10000 axi_ad9680_core ad_cpu_interconnect 0x44A91000 axi_ad9680_jesd ad_cpu_interconnect 0x7c400000 axi_ad9680_dma @@ -201,7 +140,7 @@ ad_cpu_interconnect 0x7c400000 axi_ad9680_dma # gt uses hp3, and 100MHz clock for both DRP and AXI4 ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3 -ad_mem_hp3_interconnect sys_cpu_clk axi_daq3_gt/m_axi +ad_mem_hp3_interconnect sys_cpu_clk axi_ad9680_xcvr/m_axi # interconnect (mem/dac) @@ -215,3 +154,7 @@ ad_mem_hp2_interconnect sys_cpu_clk axi_ad9680_dma/m_dest_axi ad_cpu_interrupt ps-12 mb-13 axi_ad9152_dma/irq ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq +# unused + +ad_connect axi_ad9152_fifo/dac_fifo_bypass GND + diff --git a/projects/daq3/zc706/system_bd.tcl b/projects/daq3/zc706/system_bd.tcl index 8b2be9f57..1c2f1794c 100644 --- a/projects/daq3/zc706/system_bd.tcl +++ b/projects/daq3/zc706/system_bd.tcl @@ -39,14 +39,14 @@ set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_adc set_property -dict [list CONFIG.C_PROBE2_WIDTH {16}] $ila_adc -ad_connect util_daq3_gt/rx_rst mfifo_adc/din_rst -ad_connect util_daq3_gt/rx_out_clk mfifo_adc/din_clk +ad_connect util_daq3_xcvr/up_tx_rst_done_0 mfifo_adc/din_rst +ad_connect util_daq3_xcvr/rx_out_clk_0 mfifo_adc/din_clk ad_connect axi_ad9680_core/adc_valid_0 mfifo_adc/din_valid ad_connect axi_ad9680_core/adc_data_0 mfifo_adc/din_data_0 ad_connect axi_ad9680_core/adc_data_1 mfifo_adc/din_data_1 -ad_connect util_daq3_gt/rx_rst mfifo_adc/dout_rst -ad_connect util_daq3_gt/rx_out_clk mfifo_adc/dout_clk -ad_connect util_daq3_gt/rx_out_clk ila_adc/clk +ad_connect util_daq3_xcvr/up_tx_rst_done_0 mfifo_adc/dout_rst +ad_connect util_daq3_xcvr/rx_out_clk_0 mfifo_adc/dout_clk +ad_connect util_daq3_xcvr/rx_out_clk_0 ila_adc/clk ad_connect mfifo_adc/dout_valid ila_adc/probe0 ad_connect mfifo_adc/dout_data_0 ila_adc/probe1 ad_connect mfifo_adc/dout_data_1 ila_adc/probe2 diff --git a/projects/daq3/zc706/system_constr.xdc b/projects/daq3/zc706/system_constr.xdc index fd45dcf08..3728fe6f9 100644 --- a/projects/daq3/zc706/system_constr.xdc +++ b/projects/daq3/zc706/system_constr.xdc @@ -1,21 +1,21 @@ -set_property -dict {PACKAGE_PIN AA8 } [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P -set_property -dict {PACKAGE_PIN AA7 } [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N -set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[0]] ; ## A10 FMC_HPC_DP3_M2C_P -set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[0]] ; ## A11 FMC_HPC_DP3_M2C_N -set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[1]] ; ## C06 FMC_HPC_DP0_M2C_P -set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[1]] ; ## C07 FMC_HPC_DP0_M2C_N -set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P -set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N -set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[3]] ; ## A02 FMC_HPC_DP1_M2C_P -set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[3]] ; ## A03 FMC_HPC_DP1_M2C_N -set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P -set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N -set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G09 FMC_HPC_LA03_P -set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G10 FMC_HPC_LA03_N +set_property -dict {PACKAGE_PIN AA8 } [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P +set_property -dict {PACKAGE_PIN AA7 } [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N +set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[0]] ; ## A10 FMC_HPC_DP3_M2C_P +set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[0]] ; ## A11 FMC_HPC_DP3_M2C_N +set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[1]] ; ## C06 FMC_HPC_DP0_M2C_P +set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[1]] ; ## C07 FMC_HPC_DP0_M2C_N +set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P +set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N +set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[3]] ; ## A02 FMC_HPC_DP1_M2C_P +set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[3]] ; ## A03 FMC_HPC_DP1_M2C_N +set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P +set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N +set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G09 FMC_HPC_LA03_P +set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G10 FMC_HPC_LA03_N -set_property -dict {PACKAGE_PIN AD10} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P -set_property -dict {PACKAGE_PIN AD9 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N +set_property -dict {PACKAGE_PIN AD10} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P +set_property -dict {PACKAGE_PIN AD9 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[0]) set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[0]) set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[1]] ; ## C02 FMC_HPC_DP0_C2M_P (tx_data_p[3]) @@ -24,36 +24,36 @@ set_property -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[2]] set_property -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[2]] ; ## A27 FMC_HPC_DP2_C2M_N (tx_data_n[1]) set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[3]] ; ## A22 FMC_HPC_DP1_C2M_P (tx_data_p[2]) set_property -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[3]] ; ## A23 FMC_HPC_DP1_C2M_N (tx_data_n[2]) -set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P -set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N -set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_p] ; ## H10 FMC_HPC_LA04_P -set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_n] ; ## H11 FMC_HPC_LA04_N +set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P +set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N +set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_p] ; ## H10 FMC_HPC_LA04_P +set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_n] ; ## H11 FMC_HPC_LA04_N -set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ; ## D11 FMC_HPC_LA05_P -set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports spi_csn_dac] ; ## C14 FMC_HPC_LA10_P -set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports spi_csn_adc] ; ## D15 FMC_HPC_LA09_N -set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D12 FMC_HPC_LA05_N -set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## D14 FMC_HPC_LA09_P -set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports spi_dir] ; ## C11 FMC_HPC_LA06_N +set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ; ## D11 FMC_HPC_LA05_P +set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports spi_csn_dac] ; ## C14 FMC_HPC_LA10_P +set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports spi_csn_adc] ; ## D15 FMC_HPC_LA09_N +set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D12 FMC_HPC_LA05_N +set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## D14 FMC_HPC_LA09_P +set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports spi_dir] ; ## C11 FMC_HPC_LA06_N -set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVDS_25} [get_ports sysref_p] ; ## D17 FMC_HPC_LA13_P -set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVDS_25} [get_ports sysref_n] ; ## D18 FMC_HPC_LA13_N -set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports dac_txen] ; ## G16 FMC_HPC_LA12_N -set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports adc_pd] ; ## C10 FMC_HPC_LA06_P +set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVDS_25} [get_ports sysref_p] ; ## D17 FMC_HPC_LA13_P +set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVDS_25} [get_ports sysref_n] ; ## D18 FMC_HPC_LA13_N +set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports dac_txen] ; ## G16 FMC_HPC_LA12_N +set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports adc_pd] ; ## C10 FMC_HPC_LA06_P -set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports clkd_status[0]] ; ## G12 FMC_HPC_LA08_P -set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports clkd_status[1]] ; ## G13 FMC_HPC_LA08_N -set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports dac_irq] ; ## G15 FMC_HPC_LA12_P -set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports adc_fda] ; ## H16 FMC_HPC_LA11_P -set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports adc_fdb] ; ## H17 FMC_HPC_LA11_N +set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports clkd_status[0]] ; ## G12 FMC_HPC_LA08_P +set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports clkd_status[1]] ; ## G13 FMC_HPC_LA08_N +set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports dac_irq] ; ## G15 FMC_HPC_LA12_P +set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports adc_fda] ; ## H16 FMC_HPC_LA11_P +set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports adc_fdb] ; ## H17 FMC_HPC_LA11_N -set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_p] ; ## H13 FMC_HPC_LA07_P -set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_n] ; ## H14 FMC_HPC_LA07_N +set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_p] ; ## H13 FMC_HPC_LA07_P +set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_n] ; ## H14 FMC_HPC_LA07_N # clocks create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p] create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] -create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq3_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK] -create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq3_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] +create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK] +create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] diff --git a/projects/daq3/zc706/system_top.v b/projects/daq3/zc706/system_top.v index 1bec5296e..6273a25a0 100644 --- a/projects/daq3/zc706/system_top.v +++ b/projects/daq3/zc706/system_top.v @@ -390,11 +390,17 @@ module system_top ( .ps_intr_09 (1'b0), .ps_intr_10 (1'b0), .ps_intr_11 (1'b0), - .rx_data_n (rx_data_n), - .rx_data_p (rx_data_p), - .rx_ref_clk (rx_ref_clk), - .rx_sync (rx_sync), - .rx_sysref (rx_sysref), + .rx_data_0_n (rx_data_n[0]), + .rx_data_0_p (rx_data_p[0]), + .rx_data_1_n (rx_data_n[1]), + .rx_data_1_p (rx_data_p[1]), + .rx_data_2_n (rx_data_n[2]), + .rx_data_2_p (rx_data_p[2]), + .rx_data_3_n (rx_data_n[3]), + .rx_data_3_p (rx_data_p[3]), + .rx_ref_clk_0 (rx_ref_clk), + .rx_sync_0 (rx_sync), + .rx_sysref_0 (rx_sysref), .spdif (spdif), .spi0_clk_i (spi0_clk), .spi0_clk_o (spi0_clk), @@ -417,11 +423,17 @@ module system_top ( .sys_clk_clk_n (sys_clk_n), .sys_clk_clk_p (sys_clk_p), .sys_rst (sys_rst), - .tx_data_n (tx_data_n), - .tx_data_p (tx_data_p), - .tx_ref_clk (tx_ref_clk), - .tx_sync (tx_sync), - .tx_sysref (tx_sysref)); + .tx_data_0_n (tx_data_n[0]), + .tx_data_0_p (tx_data_p[0]), + .tx_data_1_n (tx_data_n[1]), + .tx_data_1_p (tx_data_p[1]), + .tx_data_2_n (tx_data_n[2]), + .tx_data_2_p (tx_data_p[2]), + .tx_data_3_n (tx_data_n[3]), + .tx_data_3_p (tx_data_p[3]), + .tx_ref_clk_0 (tx_ref_clk), + .tx_sync_0 (tx_sync), + .tx_sysref_0 (tx_sysref)); endmodule