daq3/zc706: Update project with the new transceiver modules
Istvan Csomortani
parent
1b9d2d434c
commit
bab9b2df0b
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@ -1,20 +1,13 @@
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# daq3
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create_bd_port -dir I rx_ref_clk
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create_bd_port -dir O rx_sync
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create_bd_port -dir I rx_sysref
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create_bd_port -dir I -from 3 -to 0 rx_data_p
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create_bd_port -dir I -from 3 -to 0 rx_data_n
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create_bd_port -dir I tx_ref_clk
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create_bd_port -dir I tx_sync
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create_bd_port -dir I tx_sysref
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create_bd_port -dir O -from 3 -to 0 tx_data_p
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create_bd_port -dir O -from 3 -to 0 tx_data_n
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# dac peripherals
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set axi_ad9152_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9152_xcvr]
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set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9152_xcvr
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set_property -dict [list CONFIG.QPLL_ENABLE {1}] $axi_ad9152_xcvr
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set_property -dict [list CONFIG.TX_OR_RX_N {1}] $axi_ad9152_xcvr
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set sys_ad9152_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_ad9152_rstgen]
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set axi_ad9152_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9152:1.0 axi_ad9152_core]
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set axi_ad9152_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9152_jesd]
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@ -39,6 +32,13 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9152_upack
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# adc peripherals
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set axi_ad9680_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9680_xcvr]
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set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9680_xcvr
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set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9680_xcvr
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set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9680_xcvr
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set sys_ad9680_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_ad9680_rstgen]
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set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
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set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9680_jesd]
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@ -62,85 +62,32 @@ set axi_ad9680_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9680_cpack
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9680_cpack
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# dac/adc common gt
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# shared transceiver core
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set axi_daq3_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq3_gt]
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set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_daq3_gt
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set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_daq3_gt
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $axi_daq3_gt
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set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $axi_daq3_gt
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set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_daq3_gt
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set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_0 {1}] $axi_daq3_gt
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set_property -dict [list CONFIG.TX_DATA_SEL_0 {0}] $axi_daq3_gt
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set_property -dict [list CONFIG.TX_DATA_SEL_1 {3}] $axi_daq3_gt
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set_property -dict [list CONFIG.TX_DATA_SEL_2 {1}] $axi_daq3_gt
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set_property -dict [list CONFIG.TX_DATA_SEL_3 {2}] $axi_daq3_gt
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set util_daq3_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_daq3_xcvr]
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_daq3_xcvr
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set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $util_daq3_xcvr
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set util_daq3_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_daq3_gt]
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set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $util_daq3_gt
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set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_daq3_gt
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set_property -dict [list CONFIG.NUM_OF_LANES {4}] $util_daq3_gt
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set_property -dict [list CONFIG.RX_ENABLE {1}] $util_daq3_gt
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_daq3_gt
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set_property -dict [list CONFIG.TX_ENABLE {1}] $util_daq3_gt
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set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $util_daq3_gt
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# connections (gt)
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ad_connect util_daq3_gt/qpll_ref_clk rx_ref_clk
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ad_connect util_daq3_gt/cpll_ref_clk tx_ref_clk
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ad_connect axi_daq3_gt/gt_qpll_0 util_daq3_gt/gt_qpll_0
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ad_connect axi_daq3_gt/gt_pll_0 util_daq3_gt/gt_pll_0
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ad_connect axi_daq3_gt/gt_pll_1 util_daq3_gt/gt_pll_1
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ad_connect axi_daq3_gt/gt_pll_2 util_daq3_gt/gt_pll_2
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ad_connect axi_daq3_gt/gt_pll_3 util_daq3_gt/gt_pll_3
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ad_connect axi_daq3_gt/gt_rx_0 util_daq3_gt/gt_rx_0
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ad_connect axi_daq3_gt/gt_rx_1 util_daq3_gt/gt_rx_1
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ad_connect axi_daq3_gt/gt_rx_2 util_daq3_gt/gt_rx_2
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ad_connect axi_daq3_gt/gt_rx_3 util_daq3_gt/gt_rx_3
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ad_connect axi_daq3_gt/gt_rx_ip_0 axi_ad9680_jesd/gt0_rx
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ad_connect axi_daq3_gt/gt_rx_ip_1 axi_ad9680_jesd/gt1_rx
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ad_connect axi_daq3_gt/gt_rx_ip_2 axi_ad9680_jesd/gt2_rx
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ad_connect axi_daq3_gt/gt_rx_ip_3 axi_ad9680_jesd/gt3_rx
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ad_connect axi_daq3_gt/rx_gt_comma_align_enb_0 axi_ad9680_jesd/rxencommaalign_out
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ad_connect axi_daq3_gt/rx_gt_comma_align_enb_1 axi_ad9680_jesd/rxencommaalign_out
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ad_connect axi_daq3_gt/rx_gt_comma_align_enb_2 axi_ad9680_jesd/rxencommaalign_out
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ad_connect axi_daq3_gt/rx_gt_comma_align_enb_3 axi_ad9680_jesd/rxencommaalign_out
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ad_connect axi_daq3_gt/gt_tx_0 util_daq3_gt/gt_tx_0
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ad_connect axi_daq3_gt/gt_tx_1 util_daq3_gt/gt_tx_1
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ad_connect axi_daq3_gt/gt_tx_2 util_daq3_gt/gt_tx_2
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ad_connect axi_daq3_gt/gt_tx_3 util_daq3_gt/gt_tx_3
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ad_connect axi_daq3_gt/gt_tx_ip_0 axi_ad9152_jesd/gt0_tx
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ad_connect axi_daq3_gt/gt_tx_ip_1 axi_ad9152_jesd/gt1_tx
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ad_connect axi_daq3_gt/gt_tx_ip_2 axi_ad9152_jesd/gt2_tx
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ad_connect axi_daq3_gt/gt_tx_ip_3 axi_ad9152_jesd/gt3_tx
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ad_connect sys_cpu_resetn util_daq3_xcvr/up_rstn
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ad_connect sys_cpu_clk util_daq3_xcvr/up_clk
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# connections (dac)
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ad_connect util_daq3_gt/tx_sysref tx_sysref
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ad_connect util_daq3_gt/tx_p tx_data_p
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ad_connect util_daq3_gt/tx_n tx_data_n
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ad_connect util_daq3_gt/tx_sync tx_sync
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ad_connect util_daq3_gt/tx_out_clk util_daq3_gt/tx_clk
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ad_connect util_daq3_gt/tx_out_clk axi_ad9152_jesd/tx_core_clk
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ad_connect util_daq3_gt/tx_ip_rst axi_ad9152_jesd/tx_reset
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ad_connect util_daq3_gt/tx_ip_rst_done axi_ad9152_jesd/tx_reset_done
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ad_connect util_daq3_gt/tx_ip_sysref axi_ad9152_jesd/tx_sysref
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ad_connect util_daq3_gt/tx_ip_sync axi_ad9152_jesd/tx_sync
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ad_connect util_daq3_gt/tx_ip_data axi_ad9152_jesd/tx_tdata
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ad_connect util_daq3_gt/tx_out_clk axi_ad9152_core/tx_clk
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ad_connect util_daq3_gt/tx_data axi_ad9152_core/tx_data
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ad_connect util_daq3_gt/tx_out_clk axi_ad9152_upack/dac_clk
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ad_xcvrcon util_daq3_xcvr axi_ad9152_xcvr axi_ad9152_jesd
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ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_core/tx_clk
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ad_connect axi_ad9152_jesd/tx_tdata axi_ad9152_core/tx_data
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ad_connect util_daq3_xcvr/tx_out_clk_0 sys_ad9152_rstgen/slowest_sync_clk
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ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_fifo/dac_clk
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ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_upack/dac_clk
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ad_connect axi_ad9152_core/dac_enable_0 axi_ad9152_upack/dac_enable_0
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ad_connect axi_ad9152_core/dac_ddata_0 axi_ad9152_upack/dac_data_0
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ad_connect axi_ad9152_core/dac_valid_0 axi_ad9152_upack/dac_valid_0
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ad_connect axi_ad9152_core/dac_enable_1 axi_ad9152_upack/dac_enable_1
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ad_connect axi_ad9152_core/dac_ddata_1 axi_ad9152_upack/dac_data_1
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ad_connect axi_ad9152_core/dac_valid_1 axi_ad9152_upack/dac_valid_1
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ad_connect util_daq3_gt/tx_out_clk axi_ad9152_fifo/dac_clk
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ad_connect axi_ad9152_upack/dac_valid axi_ad9152_fifo/dac_valid
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ad_connect axi_ad9152_upack/dac_data axi_ad9152_fifo/dac_data
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ad_connect axi_ad9152_upack/dma_xfer_in axi_ad9152_fifo/dac_xfer_out
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ad_connect sys_cpu_clk axi_ad9152_fifo/dma_clk
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ad_connect sys_cpu_reset axi_ad9152_fifo/dma_rst
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ad_connect sys_cpu_clk axi_ad9152_dma/m_axis_aclk
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@ -153,30 +100,21 @@ ad_connect axi_ad9152_fifo/dma_xfer_last axi_ad9152_dma/m_axis_last
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# connections (adc)
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ad_connect util_daq3_gt/rx_sysref rx_sysref
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ad_connect util_daq3_gt/rx_p rx_data_p
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ad_connect util_daq3_gt/rx_n rx_data_n
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ad_connect util_daq3_gt/rx_sync rx_sync
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ad_connect util_daq3_gt/rx_out_clk util_daq3_gt/rx_clk
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ad_connect util_daq3_gt/rx_out_clk axi_ad9680_jesd/rx_core_clk
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ad_connect util_daq3_gt/rx_ip_rst axi_ad9680_jesd/rx_reset
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ad_connect util_daq3_gt/rx_ip_rst_done axi_ad9680_jesd/rx_reset_done
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ad_connect util_daq3_gt/rx_ip_sysref axi_ad9680_jesd/rx_sysref
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ad_connect util_daq3_gt/rx_ip_sync axi_ad9680_jesd/rx_sync
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ad_connect util_daq3_gt/rx_ip_sof axi_ad9680_jesd/rx_start_of_frame
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ad_connect util_daq3_gt/rx_ip_data axi_ad9680_jesd/rx_tdata
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ad_connect util_daq3_gt/rx_out_clk axi_ad9680_core/rx_clk
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ad_connect util_daq3_gt/rx_data axi_ad9680_core/rx_data
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ad_connect util_daq3_gt/rx_out_clk axi_ad9680_cpack/adc_clk
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ad_connect util_daq3_gt/rx_rst axi_ad9680_cpack/adc_rst
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ad_xcvrcon util_daq3_xcvr axi_ad9680_xcvr axi_ad9680_jesd
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ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_core/rx_clk
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ad_connect axi_ad9680_jesd/rx_start_of_frame axi_ad9680_core/rx_sof
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ad_connect axi_ad9680_jesd/rx_tdata axi_ad9680_core/rx_data
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ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk
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ad_connect util_daq3_xcvr/tx_out_clk_0 sys_ad9680_rstgen/slowest_sync_clk
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ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst
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ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_cpack/adc_clk
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ad_connect sys_ad9680_rstgen/peripheral_reset axi_ad9680_cpack/adc_rst
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ad_connect axi_ad9680_core/adc_enable_0 axi_ad9680_cpack/adc_enable_0
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ad_connect axi_ad9680_core/adc_valid_0 axi_ad9680_cpack/adc_valid_0
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ad_connect axi_ad9680_core/adc_data_0 axi_ad9680_cpack/adc_data_0
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ad_connect axi_ad9680_core/adc_enable_1 axi_ad9680_cpack/adc_enable_1
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ad_connect axi_ad9680_core/adc_valid_1 axi_ad9680_cpack/adc_valid_1
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ad_connect axi_ad9680_core/adc_data_1 axi_ad9680_cpack/adc_data_1
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ad_connect util_daq3_gt/rx_out_clk axi_ad9680_fifo/adc_clk
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ad_connect util_daq3_gt/rx_rst axi_ad9680_fifo/adc_rst
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ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr
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ad_connect axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata
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ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk
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@ -190,10 +128,11 @@ ad_connect axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf
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# interconnect (cpu)
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ad_cpu_interconnect 0x44A60000 axi_daq3_gt
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ad_cpu_interconnect 0x44A60000 axi_ad9152_xcvr
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ad_cpu_interconnect 0x44A00000 axi_ad9152_core
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ad_cpu_interconnect 0x44A90000 axi_ad9152_jesd
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ad_cpu_interconnect 0x7c420000 axi_ad9152_dma
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ad_cpu_interconnect 0x44A50000 axi_ad9680_xcvr
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ad_cpu_interconnect 0x44A10000 axi_ad9680_core
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ad_cpu_interconnect 0x44A91000 axi_ad9680_jesd
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ad_cpu_interconnect 0x7c400000 axi_ad9680_dma
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@ -201,7 +140,7 @@ ad_cpu_interconnect 0x7c400000 axi_ad9680_dma
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# gt uses hp3, and 100MHz clock for both DRP and AXI4
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ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
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ad_mem_hp3_interconnect sys_cpu_clk axi_daq3_gt/m_axi
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ad_mem_hp3_interconnect sys_cpu_clk axi_ad9680_xcvr/m_axi
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# interconnect (mem/dac)
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@ -215,3 +154,7 @@ ad_mem_hp2_interconnect sys_cpu_clk axi_ad9680_dma/m_dest_axi
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ad_cpu_interrupt ps-12 mb-13 axi_ad9152_dma/irq
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ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq
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# unused
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ad_connect axi_ad9152_fifo/dac_fifo_bypass GND
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@ -39,14 +39,14 @@ set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE2_WIDTH {16}] $ila_adc
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ad_connect util_daq3_gt/rx_rst mfifo_adc/din_rst
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ad_connect util_daq3_gt/rx_out_clk mfifo_adc/din_clk
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ad_connect util_daq3_xcvr/up_tx_rst_done_0 mfifo_adc/din_rst
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ad_connect util_daq3_xcvr/rx_out_clk_0 mfifo_adc/din_clk
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ad_connect axi_ad9680_core/adc_valid_0 mfifo_adc/din_valid
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ad_connect axi_ad9680_core/adc_data_0 mfifo_adc/din_data_0
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ad_connect axi_ad9680_core/adc_data_1 mfifo_adc/din_data_1
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ad_connect util_daq3_gt/rx_rst mfifo_adc/dout_rst
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ad_connect util_daq3_gt/rx_out_clk mfifo_adc/dout_clk
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ad_connect util_daq3_gt/rx_out_clk ila_adc/clk
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ad_connect util_daq3_xcvr/up_tx_rst_done_0 mfifo_adc/dout_rst
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ad_connect util_daq3_xcvr/rx_out_clk_0 mfifo_adc/dout_clk
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ad_connect util_daq3_xcvr/rx_out_clk_0 ila_adc/clk
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ad_connect mfifo_adc/dout_valid ila_adc/probe0
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ad_connect mfifo_adc/dout_data_0 ila_adc/probe1
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ad_connect mfifo_adc/dout_data_1 ila_adc/probe2
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@ -54,6 +54,6 @@ set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_
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create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p]
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create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p]
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create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq3_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
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create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq3_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
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create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
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create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
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@ -390,11 +390,17 @@ module system_top (
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.ps_intr_09 (1'b0),
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.ps_intr_10 (1'b0),
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.ps_intr_11 (1'b0),
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.rx_data_n (rx_data_n),
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.rx_data_p (rx_data_p),
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.rx_ref_clk (rx_ref_clk),
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.rx_sync (rx_sync),
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.rx_sysref (rx_sysref),
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.rx_data_0_n (rx_data_n[0]),
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.rx_data_0_p (rx_data_p[0]),
|
||||
.rx_data_1_n (rx_data_n[1]),
|
||||
.rx_data_1_p (rx_data_p[1]),
|
||||
.rx_data_2_n (rx_data_n[2]),
|
||||
.rx_data_2_p (rx_data_p[2]),
|
||||
.rx_data_3_n (rx_data_n[3]),
|
||||
.rx_data_3_p (rx_data_p[3]),
|
||||
.rx_ref_clk_0 (rx_ref_clk),
|
||||
.rx_sync_0 (rx_sync),
|
||||
.rx_sysref_0 (rx_sysref),
|
||||
.spdif (spdif),
|
||||
.spi0_clk_i (spi0_clk),
|
||||
.spi0_clk_o (spi0_clk),
|
||||
|
|
@ -417,11 +423,17 @@ module system_top (
|
|||
.sys_clk_clk_n (sys_clk_n),
|
||||
.sys_clk_clk_p (sys_clk_p),
|
||||
.sys_rst (sys_rst),
|
||||
.tx_data_n (tx_data_n),
|
||||
.tx_data_p (tx_data_p),
|
||||
.tx_ref_clk (tx_ref_clk),
|
||||
.tx_sync (tx_sync),
|
||||
.tx_sysref (tx_sysref));
|
||||
.tx_data_0_n (tx_data_n[0]),
|
||||
.tx_data_0_p (tx_data_p[0]),
|
||||
.tx_data_1_n (tx_data_n[1]),
|
||||
.tx_data_1_p (tx_data_p[1]),
|
||||
.tx_data_2_n (tx_data_n[2]),
|
||||
.tx_data_2_p (tx_data_p[2]),
|
||||
.tx_data_3_n (tx_data_n[3]),
|
||||
.tx_data_3_p (tx_data_p[3]),
|
||||
.tx_ref_clk_0 (tx_ref_clk),
|
||||
.tx_sync_0 (tx_sync),
|
||||
.tx_sysref_0 (tx_sysref));
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue