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sys_dmafifo: Update the p_sys_dacfifo process 

Update the ports and parameters at util_dacfifo instantiation.
main
Istvan Csomortani 2015-05-11 12:13:56 +03:00
parent 9934cce5d2
commit bad821ba1c
1 changed files with 17 additions and 18 deletions
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35
projects/common/xilinx/sys_dmafifo.tcl
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@ -48,7 +48,7 @@ proc p_sys_dmafifo {p_name m_name adc_data_width dma_addr_width} {
current_bd_instance $c_instance
}
proc p_sys_dacfifo {p_name m_name dma_data_width dac_data_width dac_addr_width} {
proc p_sys_dacfifo {p_name m_name data_width addr_width} {
global ad_hdl_dir
@ -62,31 +62,30 @@ proc p_sys_dacfifo {p_name m_name dma_data_width dac_data_width dac_addr_width}
create_bd_pin -dir I dma_clk
create_bd_pin -dir I dma_rst
create_bd_pin -dir O dma_en
create_bd_pin -dir O dma_ready
create_bd_pin -dir I dma_valid
create_bd_pin -dir I -from [expr ($dma_data_width-1)] -to 0 dma_data
create_bd_pin -dir I dma_unf
create_bd_pin -dir I -from [expr ($data_width-1)] -to 0 dma_data
create_bd_pin -dir I dma_xfer_req
create_bd_pin -dir I dma_xfer_last
create_bd_pin -dir I dac_clk
create_bd_pin -dir I dac_valid
create_bd_pin -dir O -from [expr ($dac_data_width - 1)] -to 0 dac_data
create_bd_pin -dir O -from [expr ($data_width - 1)] -to 0 dac_data
set util_dacfifo [create_bd_cell -type ip -vlnv analog.com:user:util_dacfifo:1.0 util_dacfifo]
set_property -dict [list CONFIG.FIFO_WDATA_WIDTH $dac_data_width] $util_dacfifo
set_property -dict [list CONFIG.FIFO_WADDR_WIDTH $dac_addr_width] $util_dacfifo
set_property -dict [list CONFIG.FIFO_RDATA_WIDTH $dma_data_width] $util_dacfifo
set_property -dict [list CONFIG.DATA_WIDTH $data_width] $util_dacfifo
set_property -dict [list CONFIG.ADDR_WIDTH $addr_width] $util_dacfifo
ad_connect dma_clk util_dacfifo/rd_clk
ad_connect dac_clk util_dacfifo/wr_clk
ad_connect dma_rst util_dacfifo/rd_rst
ad_connect dma_en util_dacfifo/rd_en
ad_connect dma_valid util_dacfifo/rd_valid
ad_connect dma_data util_dacfifo/rd_data
ad_connect dma_unf util_dacfifo/rd_underflow
ad_connect dma_xfer_req util_dacfifo/rd_xfer_req
ad_connect dac_valid util_dacfifo/wr_valid
ad_connect dac_data util_dacfifo/wr_data
ad_connect dma_clk util_dacfifo/dma_clk
ad_connect dac_clk util_dacfifo/dac_clk
ad_connect dma_rst util_dacfifo/dma_rst
ad_connect dma_ready util_dacfifo/dma_ready
ad_connect dma_valid util_dacfifo/dma_valid
ad_connect dma_data util_dacfifo/dma_data
ad_connect dma_xfer_req util_dacfifo/dma_xfer_req
ad_connect dma_xfer_last util_dacfifo/dma_xfer_last
ad_connect dac_valid util_dacfifo/dac_valid
ad_connect dac_data util_dacfifo/dac_data
current_bd_instance $c_instance
}