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library: dds and dcfilter changes, added fifo wrappers

main
Rejeesh Kutty 2014-03-10 11:11:50 -04:00
parent d6256e9e29
commit bb0431d3e8
3 changed files with 164 additions and 31 deletions
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88
library/common/ad_dcfilter.v
View File

@ -73,6 +73,7 @@ module ad_dcfilter (
// internal registers
reg [15:0] dc_offset = 'd0;
reg [15:0] dc_offset_d = 'd0;
reg valid_d = 'd0;
reg [15:0] data_d = 'd0;
reg valid_out = 'd0;
@ -80,12 +81,14 @@ module ad_dcfilter (
// internal signals
wire [14:0] dc_offset_15_s;
wire [32:0] dc_offset_33_s;
// cancelling the dc offset
always @(posedge clk) begin
dc_offset <= dc_offset_33_s[32:17];
dc_offset_d <= dc_offset;
valid_d <= valid;
if (valid == 1'b1) begin
data_d <= data + dcfilt_offset;
@ -99,13 +102,84 @@ module ad_dcfilter (
end
end
ad_dcfilter_1 i_dcfilter_1 (
.clk (clk),
.d (data_d),
.b (dcfilt_coeff),
.a (dc_offset_33_s[32:17]),
.c (dc_offset_33_s[32:17]),
.p (dc_offset_33_s));
// dsp slice instance ((D-A)*B)+C
DSP48E1 #(
.ACASCREG (1),
.ADREG (1),
.ALUMODEREG (0),
.AREG (1),
.AUTORESET_PATDET ("NO_RESET"),
.A_INPUT ("DIRECT"),
.BCASCREG (1),
.BREG (1),
.B_INPUT ("DIRECT"),
.CARRYINREG (0),
.CARRYINSELREG (0),
.CREG (1),
.DREG (0),
.INMODEREG (0),
.MASK (48'h3fffffffffff),
.MREG (1),
.OPMODEREG (0),
.PATTERN (48'h000000000000),
.PREG (0),
.SEL_MASK ("MASK"),
.SEL_PATTERN ("PATTERN"),
.USE_DPORT ("TRUE"),
.USE_MULT ("MULTIPLY"),
.USE_PATTERN_DETECT ("NO_PATDET"),
.USE_SIMD ("ONE48"))
i_dsp48e1 (
.CLK (clk),
.A ({{14{dc_offset_33_s[32]}}, dc_offset_33_s[32:17]}),
.B ({{2{dcfilt_coeff[15]}}, dcfilt_coeff}),
.C ({{32{dc_offset_d[15]}}, dc_offset_d}),
.D ({{9{data_d[15]}}, data_d}),
.MULTSIGNIN (1'd0),
.CARRYIN (1'd0),
.CARRYCASCIN (1'd0),
.ACIN (30'd0),
.BCIN (18'd0),
.PCIN (48'd0),
.P ({dc_offset_15_s, dc_offset_33_s}),
.MULTSIGNOUT (),
.CARRYOUT (),
.CARRYCASCOUT (),
.ACOUT (),
.BCOUT (),
.PCOUT (),
.ALUMODE (4'd0),
.CARRYINSEL (3'd0),
.INMODE (5'b01100),
.OPMODE (7'b0110101),
.PATTERNBDETECT (),
.PATTERNDETECT (),
.OVERFLOW (),
.UNDERFLOW (),
.CEA1 (1'd0),
.CEA2 (1'd1),
.CEAD (1'd1),
.CEALUMODE (1'd0),
.CEB1 (1'd0),
.CEB2 (1'd1),
.CEC (1'd1),
.CECARRYIN (1'd0),
.CECTRL (1'd0),
.CED (1'd1),
.CEINMODE (1'd0),
.CEM (1'd1),
.CEP (1'd0),
.RSTA (1'd0),
.RSTALLCARRYIN (1'd0),
.RSTALUMODE (1'd0),
.RSTB (1'd0),
.RSTC (1'd0),
.RSTCTRL (1'd0),
.RSTD (1'd0),
.RSTINMODE (1'd0),
.RSTM (1'd0),
.RSTP (1'd0));
endmodule

87
library/common/ad_dds_1.v
View File

@ -44,26 +44,85 @@ module ad_dds_1 (
// interface
clk,
sclr,
phase_in,
sine);
angle,
scale,
dds_data);
// interface
input clk;
input sclr;
input [15:0] phase_in;
output [15:0] sine;
input [15:0] angle;
input [15:0] scale;
output [15:0] dds_data;
// xilinx dds ip
// internal registers
ad_dds_1_xip i_dds_1_xip (
.aclk (clk),
.aresetn (~sclr),
.s_axis_phase_tvalid (1'b1),
.s_axis_phase_tdata (phase_in),
.m_axis_data_tvalid (),
.m_axis_data_tdata (sine));
reg sine_sign = 'd0;
reg [14:0] sine_magn = 'd0;
reg [14:0] sine_scale_p = 'd0;
reg [14:0] sine_scale_n = 'd0;
reg sine_scale_sign = 'd0;
reg [15:0] dds_data = 'd0;
// internal signals
wire [15:0] sine_s;
wire [14:0] sine_p_s;
wire [14:0] sine_n_s;
wire [31:0] sine_scale_s;
wire sine_sign_s;
wire scale_sign_s;
wire [14:0] sine_scale_p_s;
wire [14:0] sine_scale_n_s;
wire sine_scale_sign_s;
// sine generator
ad_dds_sine #(.DELAY_DATA_WIDTH(1)) i_dds_sine (
.clk (clk),
.angle (angle),
.sine (sine_s),
.ddata_in (1'b0),
.ddata_out ());
// sign-magnitude
assign sine_p_s = sine_s[14:0];
assign sine_n_s = ~sine_s[14:0] + 1'b1;
always @(posedge clk) begin
sine_sign <= sine_s[15];
if (sine_s[15] == 1'b1) begin
sine_magn <= sine_n_s;
end else begin
sine_magn <= sine_p_s;
end
end
// scale
ad_mul_u16 #(.DELAY_DATA_WIDTH(2)) i_mul_u16 (
.clk (clk),
.data_a ({1'b0, sine_magn}),
.data_b ({1'b0, scale[14:0]}),
.data_p (sine_scale_s),
.ddata_in ({sine_sign, scale[15]}),
.ddata_out ({sine_sign_s, scale_sign_s}));
assign sine_scale_p_s = sine_scale_s[28:14];
assign sine_scale_n_s = ~sine_scale_s[28:14] + 1'b1;
assign sine_scale_sign_s = sine_sign_s ^ scale_sign_s;
always @(posedge clk) begin
sine_scale_p <= sine_scale_p_s;
sine_scale_n <= sine_scale_n_s;
sine_scale_sign <= sine_scale_sign_s;
if (sine_scale_sign == 1'b1) begin
dds_data <= {1'b1, sine_scale_n};
end else begin
dds_data <= {1'b0, sine_scale_p};
end
end
endmodule

18
library/common/up_dac_channel.v
View File

@ -93,10 +93,10 @@ module up_dac_channel (
input dac_clk;
input dac_rst;
output [ 3:0] dac_dds_scale_1;
output [15:0] dac_dds_scale_1;
output [15:0] dac_dds_init_1;
output [15:0] dac_dds_incr_1;
output [ 3:0] dac_dds_scale_2;
output [15:0] dac_dds_scale_2;
output [15:0] dac_dds_init_2;
output [15:0] dac_dds_incr_2;
output [15:0] dac_dds_patt_1;
@ -135,10 +135,10 @@ module up_dac_channel (
// internal registers
reg [ 3:0] up_dac_dds_scale_1 = 'd0;
reg [15:0] up_dac_dds_scale_1 = 'd0;
reg [15:0] up_dac_dds_init_1 = 'd0;
reg [15:0] up_dac_dds_incr_1 = 'd0;
reg [ 3:0] up_dac_dds_scale_2 = 'd0;
reg [15:0] up_dac_dds_scale_2 = 'd0;
reg [15:0] up_dac_dds_init_2 = 'd0;
reg [15:0] up_dac_dds_incr_2 = 'd0;
reg [15:0] up_dac_dds_patt_2 = 'd0;
@ -190,14 +190,14 @@ module up_dac_channel (
up_usr_interpolation_n <= 'd0;
end else begin
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h0)) begin
up_dac_dds_scale_1 <= up_wdata[3:0];
up_dac_dds_scale_1 <= up_wdata[15:0];
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h1)) begin
up_dac_dds_init_1 <= up_wdata[31:16];
up_dac_dds_incr_1 <= up_wdata[15:0];
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h2)) begin
up_dac_dds_scale_2 <= up_wdata[3:0];
up_dac_dds_scale_2 <= up_wdata[15:0];
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h3)) begin
up_dac_dds_init_2 <= up_wdata[31:16];
@ -238,9 +238,9 @@ module up_dac_channel (
up_ack <= up_sel_s;
if (up_sel_s == 1'b1) begin
case (up_addr[3:0])
4'h0: up_rdata <= {28'd0, up_dac_dds_scale_1};
4'h0: up_rdata <= {16'd0, up_dac_dds_scale_1};
4'h1: up_rdata <= {up_dac_dds_init_1, up_dac_dds_incr_1};
4'h2: up_rdata <= {28'd0, up_dac_dds_scale_2};
4'h2: up_rdata <= {16'd0, up_dac_dds_scale_2};
4'h3: up_rdata <= {up_dac_dds_init_2, up_dac_dds_incr_2};
4'h4: up_rdata <= {up_dac_dds_patt_2, up_dac_dds_patt_1};
4'h5: up_rdata <= {30'd0, up_dac_lb_enb, up_dac_pn_enb};
@ -259,7 +259,7 @@ module up_dac_channel (
// dac control & status
up_xfer_cntrl #(.DATA_WIDTH(110)) i_dac_xfer_cntrl (
up_xfer_cntrl #(.DATA_WIDTH(134)) i_dac_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_dac_dds_scale_1,