diff --git a/projects/adrv9001/zed/system_constr.xdc b/projects/adrv9001/zed/system_constr.xdc
index ab95e58ad..f1b1407d4 100644
--- a/projects/adrv9001/zed/system_constr.xdc
+++ b/projects/adrv9001/zed/system_constr.xdc
@@ -57,3 +57,7 @@ set_property  -dict {PACKAGE_PIN  R15   IOSTANDARD LVCMOS18} [get_ports gpio_bd[
 set_property  -dict {PACKAGE_PIN  K15   IOSTANDARD LVCMOS18} [get_ports gpio_bd[29]]      ; ## XADC-GIO2
 set_property  -dict {PACKAGE_PIN  J15   IOSTANDARD LVCMOS18} [get_ports gpio_bd[30]]      ; ## XADC-GIO3
 set_property  -dict {PACKAGE_PIN  G17   IOSTANDARD LVCMOS18} [get_ports gpio_bd[31]]      ; ## OTG-RESETN
+
+set_property  -dict {PACKAGE_PIN  Y11   IOSTANDARD LVCMOS33} [get_ports  tdd_sync]        ; ## JA1.JA1 
+
+
diff --git a/projects/adrv9001/zed/system_top.v b/projects/adrv9001/zed/system_top.v
index ce119ec21..0026b733f 100644
--- a/projects/adrv9001/zed/system_top.v
+++ b/projects/adrv9001/zed/system_top.v
@@ -155,7 +155,9 @@ module system_top (
 
   inout                   sm_fan_tach,
   input                   vadj_err,
-  output                  platform_status
+  output                  platform_status,
+
+  inout                   tdd_sync
 );
 
   // internal registers
@@ -182,6 +184,9 @@ module system_top (
   wire            rx2_enable_s;
   wire            tx1_enable_s;
   wire            tx2_enable_s;
+  wire            tdd_sync_loc;
+  wire            tdd_sync_i;
+  wire            tdd_sync_cntr;
 
   // instantiations
 
@@ -229,6 +234,13 @@ module system_top (
   assign gpio_i[55] = vadj_err;
   assign gpio_i[63:56] = gpio_o[63:56];
 
+  assign tdd_sync_loc = gpio_o[56];
+
+  // tdd_sync_loc - local sync signal from a GPIO or other source
+  // tdd_sync - external sync 
+  assign tdd_sync_i = tdd_sync_cntr ? tdd_sync_loc : tdd_sync;
+  assign tdd_sync = tdd_sync_cntr ? tdd_sync_loc : 1'bz;
+
    ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_iic_scl (
     .dio_t ({iic_mux_scl_t_s,iic_mux_scl_t_s}),
     .dio_i (iic_mux_scl_o_s),
@@ -342,6 +354,9 @@ module system_top (
     .gpio_tx1_enable_in (gpio_tx1_enable_in),
     .gpio_tx2_enable_in (gpio_tx2_enable_in),
 
+    .tdd_sync (tdd_sync_i),
+    .tdd_sync_cntr (tdd_sync_cntr),
+
     .spi0_clk_i (1'b0),
     .spi0_clk_o (spi_clk_s),
     .spi0_csn_0_o (spi_en_s),