From bb9cb86f346ffdc4f8987c1b399007506f733afe Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 11 Aug 2016 09:58:36 -0400 Subject: [PATCH] adc/dac- fifo constraints --- library/util_adcfifo/util_adcfifo_constr.xdc | 8 +++++--- library/util_dacfifo/util_dacfifo.v | 12 ++++++------ library/util_dacfifo/util_dacfifo_constr.xdc | 9 +++++++-- 3 files changed, 18 insertions(+), 11 deletions(-) diff --git a/library/util_adcfifo/util_adcfifo_constr.xdc b/library/util_adcfifo/util_adcfifo_constr.xdc index d0f3cfbaa..2e7ab2b1c 100644 --- a/library/util_adcfifo/util_adcfifo_constr.xdc +++ b/library/util_adcfifo/util_adcfifo_constr.xdc @@ -1,6 +1,8 @@ -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports adc_clk]] -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports dma_clk]] - +set_property shreg_extract no [get_cells -hier -filter {name =~ *adc_xfer_req_m*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *dma_waddr_rel_t*}] +set_false_path -from [get_cells -hier -filter {name =~ *adc_waddr_rel_t_reg* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dma_waddr_rel_t_m_reg[0]* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *adc_waddr_rel_reg* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dma_waddr_rel_reg* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *adc_xfer_req_m_reg[0]* && IS_SEQUENTIAL}] diff --git a/library/util_dacfifo/util_dacfifo.v b/library/util_dacfifo/util_dacfifo.v index e73eb0091..16e183acb 100644 --- a/library/util_dacfifo/util_dacfifo.v +++ b/library/util_dacfifo/util_dacfifo.v @@ -91,8 +91,8 @@ module util_dacfifo ( reg [(ADDRESS_WIDTH-1):0] dma_waddr = 'b0; reg [(ADDRESS_WIDTH-1):0] dma_lastaddr = 'b0; - reg [(ADDRESS_WIDTH-1):0] dma_lastaddr_d = 'b0; - reg [(ADDRESS_WIDTH-1):0] dma_lastaddr_2d = 'b0; + reg [(ADDRESS_WIDTH-1):0] dac_lastaddr_d = 'b0; + reg [(ADDRESS_WIDTH-1):0] dac_lastaddr_2d = 'b0; reg dma_xfer_req_ff = 1'b0; reg dma_ready_d = 1'b0; @@ -140,8 +140,8 @@ module util_dacfifo ( // sync lastaddr to dac clock domain always @(posedge dac_clk) begin - dma_lastaddr_d <= dma_lastaddr; - dma_lastaddr_2d <= dma_lastaddr_d; + dac_lastaddr_d <= dma_lastaddr; + dac_lastaddr_2d <= dac_lastaddr_d; dac_xfer_out_m <= {dac_xfer_out_m[1:0], dma_xfer_out}; end @@ -151,10 +151,10 @@ module util_dacfifo ( always @(posedge dac_clk) begin if(dac_valid == 1'b1) begin - if (dma_lastaddr_2d == 'h0) begin + if (dac_lastaddr_2d == 'h0) begin dac_raddr <= dac_raddr + 1; end else begin - dac_raddr <= (dac_raddr < dma_lastaddr_2d) ? (dac_raddr + 1) : 'b0; + dac_raddr <= (dac_raddr < dac_lastaddr_2d) ? (dac_raddr + 1) : 'b0; end end end diff --git a/library/util_dacfifo/util_dacfifo_constr.xdc b/library/util_dacfifo/util_dacfifo_constr.xdc index c8c0111d1..670b91327 100644 --- a/library/util_dacfifo/util_dacfifo_constr.xdc +++ b/library/util_dacfifo/util_dacfifo_constr.xdc @@ -1,2 +1,7 @@ -set_false_path -from [get_cells *dma_lastaddr_reg* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \ - -to [get_cells *dma_lastaddr_d_reg* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] + +set_property shreg_extract no [get_cells -hier -filter {name =~ *dac_lastaddr_d*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *dac_xfer_out_m*}] + +set_false_path -from [get_cells -hier -filter {name =~ *dma_lastaddr_reg* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dac_lastaddr_d_reg* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *dac_xfer_out_m_reg[0]* && IS_SEQUENTIAL}] +