From bc6a09c828eef99fb6293aa93261e2b3c7a8df06 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Wed, 1 Mar 2017 15:34:04 -0500 Subject: [PATCH] adrv9371x/a10soc- dacfifo added --- projects/adrv9371x/a10soc/system_constr.sdc | 7 +++ projects/adrv9371x/a10soc/system_project.tcl | 4 +- projects/adrv9371x/a10soc/system_qsys.tcl | 5 +++ projects/adrv9371x/a10soc/system_top.v | 47 +++++++++++++++++++- projects/adrv9371x/common/adrv9371x_qsys.tcl | 19 +++++--- 5 files changed, 75 insertions(+), 7 deletions(-) diff --git a/projects/adrv9371x/a10soc/system_constr.sdc b/projects/adrv9371x/a10soc/system_constr.sdc index 029e779b7..d7ab191fd 100644 --- a/projects/adrv9371x/a10soc/system_constr.sdc +++ b/projects/adrv9371x/a10soc/system_constr.sdc @@ -1,11 +1,18 @@ +# qsys- automatically infers these clocks + create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] create_clock -period "8.139 ns" -name ref_clk0_122mhz [get_ports {ref_clk0}] create_clock -period "8.139 ns" -name ref_clk1_122mhz [get_ports {ref_clk1}] +create_clock -period "7.503 ns" -name hps_ddr_ref_clk_133mhz [get_ports {hps_ddr_ref_clk}] +create_clock -period "7.503 ns" -name sys_ddr_ref_clk_133mhz [get_ports {sys_ddr_ref_clk}] derive_pll_clocks derive_clock_uncertainty +set_false_path -to [get_registers *sys_gpio_in|readdata[12]*] +set_false_path -to [get_registers *sys_gpio_in|readdata[13]*] + set_false_path -from [get_clocks {sys_clk_100mhz}]\ -through [get_nets *altera_jesd204_tx_csr_inst*]\ -to [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}] diff --git a/projects/adrv9371x/a10soc/system_project.tcl b/projects/adrv9371x/a10soc/system_project.tcl index f918f5208..9ef4f5e47 100644 --- a/projects/adrv9371x/a10soc/system_project.tcl +++ b/projects/adrv9371x/a10soc/system_project.tcl @@ -4,7 +4,9 @@ load_package flow source ../../scripts/adi_env.tcl project_new adrv9371x_a10soc -overwrite -source "../../common/a10soc/a10soc_system_assign.tcl" +source $ad_hdl_dir/projects/common/a10soc/a10soc_system_assign.tcl +source $ad_hdl_dir/projects/common/a10soc/a10soc_plddr4_assign.tcl +source $ad_hdl_dir/projects/common/altera/sys_gen.tcl set_global_assignment -name QSYS_FILE system_bd.qsys set_global_assignment -name VERILOG_FILE system_top.v diff --git a/projects/adrv9371x/a10soc/system_qsys.tcl b/projects/adrv9371x/a10soc/system_qsys.tcl index 7581f7875..03c2b439c 100644 --- a/projects/adrv9371x/a10soc/system_qsys.tcl +++ b/projects/adrv9371x/a10soc/system_qsys.tcl @@ -1,6 +1,11 @@ +set dac_fifo_name axi_ad9371_tx_fifo +set dac_fifo_address_width 10 +set dac_data_width 128 +set dac_dma_data_width 128 source $ad_hdl_dir/projects/common/a10soc/a10soc_system_qsys.tcl +source $ad_hdl_dir/projects/common/a10soc/a10soc_plddr4_dacfifo_qsys.tcl source ../common/adrv9371x_qsys.tcl diff --git a/projects/adrv9371x/a10soc/system_top.v b/projects/adrv9371x/a10soc/system_top.v index 9cf0c5fbe..768ddb097 100644 --- a/projects/adrv9371x/a10soc/system_top.v +++ b/projects/adrv9371x/a10soc/system_top.v @@ -65,6 +65,27 @@ module system_top ( inout [ 3:0] hps_ddr_dbi_n, input hps_ddr_rzq, + // pl-ddr4 + + input sys_ddr_ref_clk, + output [ 0:0] sys_ddr_clk_p, + output [ 0:0] sys_ddr_clk_n, + output [ 16:0] sys_ddr_a, + output [ 1:0] sys_ddr_ba, + output [ 0:0] sys_ddr_bg, + output [ 0:0] sys_ddr_cke, + output [ 0:0] sys_ddr_cs_n, + output [ 0:0] sys_ddr_odt, + output [ 0:0] sys_ddr_reset_n, + output [ 0:0] sys_ddr_act_n, + output [ 0:0] sys_ddr_par, + input [ 0:0] sys_ddr_alert_n, + inout [ 7:0] sys_ddr_dqs_p, + inout [ 7:0] sys_ddr_dqs_n, + inout [ 63:0] sys_ddr_dq, + inout [ 7:0] sys_ddr_dbi_n, + input sys_ddr_rzq, + // hps-ethernet input [ 0:0] hps_eth_rxclk, @@ -140,6 +161,8 @@ module system_top ( // internal signals + wire sys_ddr_cal_success; + wire sys_ddr_cal_fail; wire sys_hps_resetn; wire sys_resetn_s; wire [ 7:0] spi_csn; @@ -163,7 +186,9 @@ module system_top ( // gpio (max-v-u21) - assign gpio_i[15:12] = gpio_o[15:12]; + assign gpio_i[15:14] = gpio_o[15:14]; + assign gpio_i[13:13] = sys_ddr_cal_success; + assign gpio_i[12:12] = sys_ddr_cal_fail; assign gpio_i[11: 4] = gpio_bd_i; assign gpio_i[ 3: 0] = gpio_o[3:0]; @@ -190,6 +215,26 @@ module system_top ( .rx_sync_export (rx_sync), .rx_sysref_export (sysref), .sys_clk_clk (sys_clk), + .sys_ddr_mem_mem_ck (sys_ddr_clk_p), + .sys_ddr_mem_mem_ck_n (sys_ddr_clk_n), + .sys_ddr_mem_mem_a (sys_ddr_a), + .sys_ddr_mem_mem_act_n (sys_ddr_act_n), + .sys_ddr_mem_mem_ba (sys_ddr_ba), + .sys_ddr_mem_mem_bg (sys_ddr_bg), + .sys_ddr_mem_mem_cke (sys_ddr_cke), + .sys_ddr_mem_mem_cs_n (sys_ddr_cs_n), + .sys_ddr_mem_mem_odt (sys_ddr_odt), + .sys_ddr_mem_mem_reset_n (sys_ddr_reset_n), + .sys_ddr_mem_mem_par (sys_ddr_par), + .sys_ddr_mem_mem_alert_n (sys_ddr_alert_n), + .sys_ddr_mem_mem_dqs (sys_ddr_dqs_p), + .sys_ddr_mem_mem_dqs_n (sys_ddr_dqs_n), + .sys_ddr_mem_mem_dq (sys_ddr_dq), + .sys_ddr_mem_mem_dbi_n (sys_ddr_dbi_n), + .sys_ddr_oct_oct_rzqin (sys_ddr_rzq), + .sys_ddr_ref_clk_clk (sys_ddr_ref_clk), + .sys_ddr_status_local_cal_success (sys_ddr_cal_success), + .sys_ddr_status_local_cal_fail (sys_ddr_cal_fail), .sys_gpio_in_export (gpio_i), .sys_gpio_out_export (gpio_o), .sys_hps_ddr_mem_ck (hps_ddr_clk_p), diff --git a/projects/adrv9371x/common/adrv9371x_qsys.tcl b/projects/adrv9371x/common/adrv9371x_qsys.tcl index c3e1428ec..661117f0e 100644 --- a/projects/adrv9371x/common/adrv9371x_qsys.tcl +++ b/projects/adrv9371x/common/adrv9371x_qsys.tcl @@ -179,6 +179,12 @@ add_connection axi_ad9371.adc_os_ch_1 axi_ad9371_rx_os_cpack.adc_ch_1 # dac & adc fifos +add_connection axi_ad9371_tx_xcvr.if_up_rst axi_ad9371_tx_fifo.if_dac_rst +add_connection avl_ad9371_tx_xcvr.core_clk axi_ad9371_tx_fifo.if_dac_clk +add_connection axi_ad9371_tx_upack.if_dac_valid axi_ad9371_tx_fifo.if_dac_valid +add_connection axi_ad9371_tx_fifo.if_dac_data axi_ad9371_tx_upack.if_dac_data +add_connection axi_ad9371_tx_fifo.if_dac_dunf axi_ad9371.if_dac_dunf + add_instance axi_ad9371_rx_fifo util_adcfifo 1.0 set_instance_parameter_value axi_ad9371_rx_fifo {ADC_DATA_WIDTH} {64} set_instance_parameter_value axi_ad9371_rx_fifo {DMA_DATA_WIDTH} {64} @@ -217,13 +223,16 @@ set_instance_parameter_value axi_ad9371_tx_dma {AXI_SLICE_DEST} {0} set_instance_parameter_value axi_ad9371_tx_dma {AXI_SLICE_SRC} {0} set_instance_parameter_value axi_ad9371_tx_dma {SYNC_TRANSFER_START} {0} set_instance_parameter_value axi_ad9371_tx_dma {CYCLIC} {1} -set_instance_parameter_value axi_ad9371_tx_dma {DMA_TYPE_DEST} {2} +set_instance_parameter_value axi_ad9371_tx_dma {DMA_TYPE_DEST} {1} set_instance_parameter_value axi_ad9371_tx_dma {DMA_TYPE_SRC} {0} set_instance_parameter_value axi_ad9371_tx_dma {FIFO_SIZE} {16} -add_connection avl_ad9371_tx_xcvr.core_clk axi_ad9371_tx_dma.if_fifo_rd_clk -add_connection axi_ad9371_tx_upack.if_dac_valid axi_ad9371_tx_dma.if_fifo_rd_en -add_connection axi_ad9371_tx_dma.if_fifo_rd_dout axi_ad9371_tx_upack.if_dac_data -add_connection axi_ad9371_tx_dma.if_fifo_rd_underflow axi_ad9371.if_dac_dunf +add_connection sys_dma_clk.clk axi_ad9371_tx_fifo.if_dma_clk +add_connection sys_dma_clk.clk axi_ad9371_tx_dma.if_m_axis_aclk +add_connection axi_ad9371_tx_dma.if_m_axis_valid axi_ad9371_tx_fifo.if_dma_valid +add_connection axi_ad9371_tx_dma.if_m_axis_data axi_ad9371_tx_fifo.if_dma_data +add_connection axi_ad9371_tx_dma.if_m_axis_last axi_ad9371_tx_fifo.if_dma_xfer_last +add_connection axi_ad9371_tx_dma.if_m_axis_xfer_req axi_ad9371_tx_fifo.if_dma_xfer_req +add_connection axi_ad9371_tx_fifo.if_dma_ready axi_ad9371_tx_dma.if_m_axis_ready add_connection sys_clk.clk axi_ad9371_tx_dma.s_axi_clock add_connection sys_clk.clk_reset axi_ad9371_tx_dma.s_axi_reset add_connection sys_dma_clk.clk axi_ad9371_tx_dma.m_src_axi_clock