adrv9371x/a10soc- dacfifo added
Rejeesh Kutty
parent
5b5c0dde99
commit
bc6a09c828
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@ -1,11 +1,18 @@
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# qsys- automatically infers these clocks
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
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create_clock -period "8.139 ns" -name ref_clk0_122mhz [get_ports {ref_clk0}]
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create_clock -period "8.139 ns" -name ref_clk1_122mhz [get_ports {ref_clk1}]
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create_clock -period "7.503 ns" -name hps_ddr_ref_clk_133mhz [get_ports {hps_ddr_ref_clk}]
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create_clock -period "7.503 ns" -name sys_ddr_ref_clk_133mhz [get_ports {sys_ddr_ref_clk}]
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derive_pll_clocks
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derive_clock_uncertainty
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set_false_path -to [get_registers *sys_gpio_in|readdata[12]*]
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set_false_path -to [get_registers *sys_gpio_in|readdata[13]*]
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set_false_path -from [get_clocks {sys_clk_100mhz}]\
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-through [get_nets *altera_jesd204_tx_csr_inst*]\
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-to [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]
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@ -4,7 +4,9 @@ load_package flow
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source ../../scripts/adi_env.tcl
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project_new adrv9371x_a10soc -overwrite
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source "../../common/a10soc/a10soc_system_assign.tcl"
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source $ad_hdl_dir/projects/common/a10soc/a10soc_system_assign.tcl
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source $ad_hdl_dir/projects/common/a10soc/a10soc_plddr4_assign.tcl
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source $ad_hdl_dir/projects/common/altera/sys_gen.tcl
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set_global_assignment -name QSYS_FILE system_bd.qsys
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set_global_assignment -name VERILOG_FILE system_top.v
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@ -1,6 +1,11 @@
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set dac_fifo_name axi_ad9371_tx_fifo
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set dac_fifo_address_width 10
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set dac_data_width 128
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set dac_dma_data_width 128
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source $ad_hdl_dir/projects/common/a10soc/a10soc_system_qsys.tcl
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source $ad_hdl_dir/projects/common/a10soc/a10soc_plddr4_dacfifo_qsys.tcl
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source ../common/adrv9371x_qsys.tcl
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@ -65,6 +65,27 @@ module system_top (
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inout [ 3:0] hps_ddr_dbi_n,
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input hps_ddr_rzq,
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// pl-ddr4
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input sys_ddr_ref_clk,
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output [ 0:0] sys_ddr_clk_p,
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output [ 0:0] sys_ddr_clk_n,
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output [ 16:0] sys_ddr_a,
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output [ 1:0] sys_ddr_ba,
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output [ 0:0] sys_ddr_bg,
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output [ 0:0] sys_ddr_cke,
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output [ 0:0] sys_ddr_cs_n,
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output [ 0:0] sys_ddr_odt,
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output [ 0:0] sys_ddr_reset_n,
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output [ 0:0] sys_ddr_act_n,
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output [ 0:0] sys_ddr_par,
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input [ 0:0] sys_ddr_alert_n,
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inout [ 7:0] sys_ddr_dqs_p,
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inout [ 7:0] sys_ddr_dqs_n,
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inout [ 63:0] sys_ddr_dq,
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inout [ 7:0] sys_ddr_dbi_n,
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input sys_ddr_rzq,
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// hps-ethernet
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input [ 0:0] hps_eth_rxclk,
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@ -140,6 +161,8 @@ module system_top (
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// internal signals
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wire sys_ddr_cal_success;
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wire sys_ddr_cal_fail;
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wire sys_hps_resetn;
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wire sys_resetn_s;
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wire [ 7:0] spi_csn;
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@ -163,7 +186,9 @@ module system_top (
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// gpio (max-v-u21)
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assign gpio_i[15:12] = gpio_o[15:12];
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assign gpio_i[15:14] = gpio_o[15:14];
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assign gpio_i[13:13] = sys_ddr_cal_success;
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assign gpio_i[12:12] = sys_ddr_cal_fail;
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assign gpio_i[11: 4] = gpio_bd_i;
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assign gpio_i[ 3: 0] = gpio_o[3:0];
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@ -190,6 +215,26 @@ module system_top (
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.rx_sync_export (rx_sync),
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.rx_sysref_export (sysref),
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.sys_clk_clk (sys_clk),
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.sys_ddr_mem_mem_ck (sys_ddr_clk_p),
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.sys_ddr_mem_mem_ck_n (sys_ddr_clk_n),
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.sys_ddr_mem_mem_a (sys_ddr_a),
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.sys_ddr_mem_mem_act_n (sys_ddr_act_n),
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.sys_ddr_mem_mem_ba (sys_ddr_ba),
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.sys_ddr_mem_mem_bg (sys_ddr_bg),
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.sys_ddr_mem_mem_cke (sys_ddr_cke),
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.sys_ddr_mem_mem_cs_n (sys_ddr_cs_n),
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.sys_ddr_mem_mem_odt (sys_ddr_odt),
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.sys_ddr_mem_mem_reset_n (sys_ddr_reset_n),
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.sys_ddr_mem_mem_par (sys_ddr_par),
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.sys_ddr_mem_mem_alert_n (sys_ddr_alert_n),
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.sys_ddr_mem_mem_dqs (sys_ddr_dqs_p),
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.sys_ddr_mem_mem_dqs_n (sys_ddr_dqs_n),
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.sys_ddr_mem_mem_dq (sys_ddr_dq),
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.sys_ddr_mem_mem_dbi_n (sys_ddr_dbi_n),
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.sys_ddr_oct_oct_rzqin (sys_ddr_rzq),
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.sys_ddr_ref_clk_clk (sys_ddr_ref_clk),
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.sys_ddr_status_local_cal_success (sys_ddr_cal_success),
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.sys_ddr_status_local_cal_fail (sys_ddr_cal_fail),
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.sys_gpio_in_export (gpio_i),
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.sys_gpio_out_export (gpio_o),
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.sys_hps_ddr_mem_ck (hps_ddr_clk_p),
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@ -179,6 +179,12 @@ add_connection axi_ad9371.adc_os_ch_1 axi_ad9371_rx_os_cpack.adc_ch_1
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# dac & adc fifos
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add_connection axi_ad9371_tx_xcvr.if_up_rst axi_ad9371_tx_fifo.if_dac_rst
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add_connection avl_ad9371_tx_xcvr.core_clk axi_ad9371_tx_fifo.if_dac_clk
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add_connection axi_ad9371_tx_upack.if_dac_valid axi_ad9371_tx_fifo.if_dac_valid
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add_connection axi_ad9371_tx_fifo.if_dac_data axi_ad9371_tx_upack.if_dac_data
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add_connection axi_ad9371_tx_fifo.if_dac_dunf axi_ad9371.if_dac_dunf
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add_instance axi_ad9371_rx_fifo util_adcfifo 1.0
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set_instance_parameter_value axi_ad9371_rx_fifo {ADC_DATA_WIDTH} {64}
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set_instance_parameter_value axi_ad9371_rx_fifo {DMA_DATA_WIDTH} {64}
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@ -217,13 +223,16 @@ set_instance_parameter_value axi_ad9371_tx_dma {AXI_SLICE_DEST} {0}
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set_instance_parameter_value axi_ad9371_tx_dma {AXI_SLICE_SRC} {0}
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set_instance_parameter_value axi_ad9371_tx_dma {SYNC_TRANSFER_START} {0}
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set_instance_parameter_value axi_ad9371_tx_dma {CYCLIC} {1}
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set_instance_parameter_value axi_ad9371_tx_dma {DMA_TYPE_DEST} {2}
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set_instance_parameter_value axi_ad9371_tx_dma {DMA_TYPE_DEST} {1}
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set_instance_parameter_value axi_ad9371_tx_dma {DMA_TYPE_SRC} {0}
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set_instance_parameter_value axi_ad9371_tx_dma {FIFO_SIZE} {16}
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add_connection avl_ad9371_tx_xcvr.core_clk axi_ad9371_tx_dma.if_fifo_rd_clk
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add_connection axi_ad9371_tx_upack.if_dac_valid axi_ad9371_tx_dma.if_fifo_rd_en
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add_connection axi_ad9371_tx_dma.if_fifo_rd_dout axi_ad9371_tx_upack.if_dac_data
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add_connection axi_ad9371_tx_dma.if_fifo_rd_underflow axi_ad9371.if_dac_dunf
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add_connection sys_dma_clk.clk axi_ad9371_tx_fifo.if_dma_clk
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add_connection sys_dma_clk.clk axi_ad9371_tx_dma.if_m_axis_aclk
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add_connection axi_ad9371_tx_dma.if_m_axis_valid axi_ad9371_tx_fifo.if_dma_valid
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add_connection axi_ad9371_tx_dma.if_m_axis_data axi_ad9371_tx_fifo.if_dma_data
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add_connection axi_ad9371_tx_dma.if_m_axis_last axi_ad9371_tx_fifo.if_dma_xfer_last
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add_connection axi_ad9371_tx_dma.if_m_axis_xfer_req axi_ad9371_tx_fifo.if_dma_xfer_req
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add_connection axi_ad9371_tx_fifo.if_dma_ready axi_ad9371_tx_dma.if_m_axis_ready
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add_connection sys_clk.clk axi_ad9371_tx_dma.s_axi_clock
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add_connection sys_clk.clk_reset axi_ad9371_tx_dma.s_axi_reset
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add_connection sys_dma_clk.clk axi_ad9371_tx_dma.m_src_axi_clock
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