From bc93910ee5271de3630249fc51613412a064f3e9 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 10 Dec 2015 16:04:10 -0500 Subject: [PATCH] ad9152: qsys updates --- library/axi_ad9152/axi_ad9152.v | 4 +++ library/axi_ad9152/axi_ad9152_hw.tcl | 49 +++++++--------------------- 2 files changed, 15 insertions(+), 38 deletions(-) diff --git a/library/axi_ad9152/axi_ad9152.v b/library/axi_ad9152/axi_ad9152.v index 2ab69a0ee..cc9c36e45 100644 --- a/library/axi_ad9152/axi_ad9152.v +++ b/library/axi_ad9152/axi_ad9152.v @@ -65,6 +65,7 @@ module axi_ad9152 ( s_axi_aresetn, s_axi_awvalid, s_axi_awaddr, + s_axi_awprot, s_axi_awready, s_axi_wvalid, s_axi_wdata, @@ -75,6 +76,7 @@ module axi_ad9152 ( s_axi_bready, s_axi_arvalid, s_axi_araddr, + s_axi_arprot, s_axi_arready, s_axi_rvalid, s_axi_rdata, @@ -110,6 +112,7 @@ module axi_ad9152 ( input s_axi_aresetn; input s_axi_awvalid; input [ 31:0] s_axi_awaddr; + input [ 2:0] s_axi_awprot; output s_axi_awready; input s_axi_wvalid; input [ 31:0] s_axi_wdata; @@ -120,6 +123,7 @@ module axi_ad9152 ( input s_axi_bready; input s_axi_arvalid; input [ 31:0] s_axi_araddr; + input [ 2:0] s_axi_arprot; output s_axi_arready; output s_axi_rvalid; output [ 31:0] s_axi_rdata; diff --git a/library/axi_ad9152/axi_ad9152_hw.tcl b/library/axi_ad9152/axi_ad9152_hw.tcl index b30788e08..5cb74d354 100755 --- a/library/axi_ad9152/axi_ad9152_hw.tcl +++ b/library/axi_ad9152/axi_ad9152_hw.tcl @@ -4,18 +4,16 @@ package require -exact qsys 13.0 source ../scripts/adi_env.tcl source ../scripts/adi_ip_alt.tcl -set_module_property NAME axi_ad9144 -set_module_property DESCRIPTION "AXI AD9144 Interface" +set_module_property NAME axi_ad9152 +set_module_property DESCRIPTION "AXI AD9152 Interface" set_module_property VERSION 1.0 set_module_property GROUP "Analog Devices" -set_module_property DISPLAY_NAME axi_ad9144 -set_module_property ELABORATION_CALLBACK p_axi_ad9144 +set_module_property DISPLAY_NAME axi_ad9152 # files add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" -set_fileset_property quartus_synth TOP_LEVEL axi_ad9144 -add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v +set_fileset_property quartus_synth TOP_LEVEL axi_ad9152 add_fileset_file MULT_MACRO.v VERILOG PATH $ad_hdl_dir/library/common/altera/MULT_MACRO.v add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/common/ad_mul.v add_fileset_file ad_dds_sine.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v @@ -28,10 +26,10 @@ add_fileset_file up_xfer_status.v VERILOG PATH $ad_hdl_dir/library/common/up add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v add_fileset_file up_dac_common.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_common.v add_fileset_file up_dac_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_channel.v -add_fileset_file axi_ad9144_channel.v VERILOG PATH axi_ad9144_channel.v -add_fileset_file axi_ad9144_core.v VERILOG PATH axi_ad9144_core.v -add_fileset_file axi_ad9144_if.v VERILOG PATH axi_ad9144_if.v -add_fileset_file axi_ad9144.v VERILOG PATH axi_ad9144.v TOP_LEVEL_FILE +add_fileset_file axi_ad9152_channel.v VERILOG PATH axi_ad9152_channel.v +add_fileset_file axi_ad9152_core.v VERILOG PATH axi_ad9152_core.v +add_fileset_file axi_ad9152_if.v VERILOG PATH axi_ad9152_if.v +add_fileset_file axi_ad9152.v VERILOG PATH axi_ad9152.v TOP_LEVEL_FILE add_fileset_file ad_axi_ip_constr.sdc SDC PATH $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc # parameters @@ -43,13 +41,6 @@ set_parameter_property ID TYPE INTEGER set_parameter_property ID UNITS None set_parameter_property ID HDL_PARAMETER true -add_parameter QUAD_OR_DUAL_N INTEGER 0 -set_parameter_property QUAD_OR_DUAL_N DEFAULT_VALUE 0 -set_parameter_property QUAD_OR_DUAL_N DISPLAY_NAME QUAD_OR_DUAL_N -set_parameter_property QUAD_OR_DUAL_N TYPE INTEGER -set_parameter_property QUAD_OR_DUAL_N UNITS None -set_parameter_property QUAD_OR_DUAL_N HDL_PARAMETER true - # axi4 slave add_interface s_axi_clock clock end @@ -85,7 +76,7 @@ add_interface_port s_axi s_axi_rready rready Input 1 # transceiver interface ad_alt_intf clock tx_clk input 1 -ad_alt_intf signal tx_data output 128*(QUAD_OR_DUAL_N+1) data +ad_alt_intf signal tx_data output 128 data # dma interface @@ -101,24 +92,6 @@ add_interface_port fifo_ch_1_out dac_enable_1 enable Output 1 add_interface_port fifo_ch_1_out dac_valid_1 valid Output 1 add_interface_port fifo_ch_1_out dac_data_1 data Input 64 -ad_alt_intf signal dac_dovf input 1 -ad_alt_intf signal dac_dunf input 1 +ad_alt_intf signal dac_dovf input 1 ovf +ad_alt_intf signal dac_dunf input 1 unf -proc p_axi_ad9144 {} { - - set p_pcore_quad_dual_n [get_parameter_value "QUAD_OR_DUAL_N"] - - if {[get_parameter_value QUAD_OR_DUAL_N] == 1} { - - add_interface fifo_ch_2_out conduit end - add_interface_port fifo_ch_2_out dac_enable_2 enable Output 1 - add_interface_port fifo_ch_2_out dac_valid_2 valid Output 1 - add_interface_port fifo_ch_2_out dac_data_2 data Input 64 - - add_interface fifo_ch_3_out conduit end - add_interface_port fifo_ch_3_out dac_enable_3 enable Output 1 - add_interface_port fifo_ch_3_out dac_valid_3 valid Output 1 - add_interface_port fifo_ch_3_out dac_data_3 data Input 64 - - } -}