fmcomms1: Fixed missing sample issue on ZC706. Added modifications for all other platforms

projects/fmcomms1/ac701/system_top.v

@@ -181,8 +181,33 @@ module system_top (
 
   output          spdif;
 
+  // internal registers
+
+  reg     [63:0]  dac_ddata_0 = 'd0;
+  reg     [63:0]  dac_ddata_1 = 'd0;
+  reg             dac_dma_rd = 'd0;
+  reg             adc_data_cnt = 'd0;
+  reg             adc_dma_wr = 'd0;
+  reg     [31:0]  adc_dma_wdata = 'd0;
+
+  // internal signals
+
+  wire            dac_clk;
+  wire            dac_valid_0;
+  wire            dac_enable_0;
+  wire            dac_valid_1;
+  wire            dac_enable_1;
+  wire    [63:0]  dac_dma_rdata;
+  wire            adc_clk;
+  wire            adc_valid_0;
+  wire            adc_enable_0;
+  wire    [15:0]  adc_data_0;
+  wire            adc_valid_1;
+  wire            adc_enable_1;
+  wire    [15:0]  adc_data_1;
   wire            ref_clk;
   wire            oddr_ref_clk;
+
   // assignments
 
   assign mgt_clk_sel = 2'd0;
@@ -207,6 +232,36 @@ module system_top (
     .O (ref_clk_out_p),
     .OB (ref_clk_out_n));
 
+   always @(posedge dac_clk) begin
+    dac_dma_rd <= dac_valid_0 & dac_enable_0;
+    dac_ddata_1[63:48] <= dac_dma_rdata[63:48];
+    dac_ddata_1[47:32] <= dac_dma_rdata[63:48];
+    dac_ddata_1[31:16] <= dac_dma_rdata[31:16];
+    dac_ddata_1[15: 0] <= dac_dma_rdata[31:16];
+    dac_ddata_0[63:48] <= dac_dma_rdata[47:32];
+    dac_ddata_0[47:32] <= dac_dma_rdata[47:32];
+    dac_ddata_0[31:16] <= dac_dma_rdata[15: 0];
+    dac_ddata_0[15: 0] <= dac_dma_rdata[15: 0];
+  end
+
+  always @(posedge adc_clk) begin
+    adc_data_cnt <= ~adc_data_cnt;
+    case ({adc_enable_1, adc_enable_0})
+      2'b10: begin
+        adc_dma_wr <= adc_data_cnt;
+        adc_dma_wdata <= {adc_data_1, adc_dma_wdata[31:16]};
+      end
+      2'b01: begin
+        adc_dma_wr <= adc_data_cnt;
+        adc_dma_wdata <= {adc_data_0, adc_dma_wdata[31:16]};
+      end
+      default: begin
+        adc_dma_wr <= 1'b1;
+        adc_dma_wdata <= {adc_data_1, adc_data_0};
+      end
+    endcase
+  end
+
   system_wrapper i_system_wrapper (
     .ddr3_addr (ddr3_addr),
     .ddr3_ba (ddr3_ba),
@@ -235,20 +290,39 @@ module system_top (
     .iic_main_scl_io (iic_scl),
     .iic_main_sda_io (iic_sda),
     .iic_rstn (iic_rstn),
+    .adc_clk (adc_clk),
     .adc_clk_in_n (adc_clk_in_n),
     .adc_clk_in_p (adc_clk_in_p),
+    .adc_data_0 (adc_data_0),
+    .adc_data_1 (adc_data_1),
     .adc_data_in_n (adc_data_in_n),
     .adc_data_in_p (adc_data_in_p),
+    .adc_dma_sync (1'b1),
+    .adc_dma_wdata (adc_dma_wdata),
+    .adc_dma_wr (adc_dma_wr),
+    .adc_enable_0 (adc_enable_0),
+    .adc_enable_1 (adc_enable_1),
     .adc_or_in_n (adc_or_in_n),
     .adc_or_in_p (adc_or_in_p),
+    .adc_valid_0 (adc_valid_0),
+    .adc_valid_1 (adc_valid_1),
+    .dac_clk (dac_clk),
     .dac_clk_in_n (dac_clk_in_n),
     .dac_clk_in_p (dac_clk_in_p),
     .dac_clk_out_n (dac_clk_out_n),
     .dac_clk_out_p (dac_clk_out_p),
     .dac_data_out_n (dac_data_out_n),
     .dac_data_out_p (dac_data_out_p),
+    .dac_ddata_0 (dac_ddata_0),
+    .dac_ddata_1 (dac_ddata_1),
+    .dac_dma_rd (dac_dma_rd),
+    .dac_dma_rdata (dac_dma_rdata),
+    .dac_enable_0 (dac_enable_0),
+    .dac_enable_1 (dac_enable_1),
     .dac_frame_out_n (dac_frame_out_n),
     .dac_frame_out_p (dac_frame_out_p),
+    .dac_valid_0 (dac_valid_0),
+    .dac_valid_1 (dac_valid_1),
     .ref_clk (ref_clk),
     .mdio_io (phy_mdio),
     .mdio_mdc (phy_mdc),

projects/fmcomms1/common/fmcomms1_bd.tcl

@@ -245,6 +245,7 @@ if {$sys_zynq == 0 } {
   set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_adc
   set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc
   set_property -dict [list CONFIG.C_PROBE1_WIDTH {64}] $ila_adc
+  set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}]  $ila_adc
   set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
 
   connect_bd_net -net sys_200m_clk [get_bd_pins ila_adc/clk]

projects/fmcomms1/kc705/system_top.v

@@ -191,6 +191,30 @@ module system_top (
 
   output          spdif;
 
+  // internal registers
+
+  reg     [63:0]  dac_ddata_0 = 'd0;
+  reg     [63:0]  dac_ddata_1 = 'd0;
+  reg             dac_dma_rd = 'd0;
+  reg             adc_data_cnt = 'd0;
+  reg             adc_dma_wr = 'd0;
+  reg     [31:0]  adc_dma_wdata = 'd0;
+
+  // internal signals
+
+  wire            dac_clk;
+  wire            dac_valid_0;
+  wire            dac_enable_0;
+  wire            dac_valid_1;
+  wire            dac_enable_1;
+  wire    [63:0]  dac_dma_rdata;
+  wire            adc_clk;
+  wire            adc_valid_0;
+  wire            adc_enable_0;
+  wire    [15:0]  adc_data_0;
+  wire            adc_valid_1;
+  wire            adc_enable_1;
+  wire    [15:0]  adc_data_1;
   wire            ref_clk;
   wire            oddr_ref_clk;
 
@@ -214,6 +238,36 @@ module system_top (
     .O (ref_clk_out_p),
     .OB (ref_clk_out_n));
 
+  always @(posedge dac_clk) begin
+    dac_dma_rd <= dac_valid_0 & dac_enable_0;
+    dac_ddata_1[63:48] <= dac_dma_rdata[63:48];
+    dac_ddata_1[47:32] <= dac_dma_rdata[63:48];
+    dac_ddata_1[31:16] <= dac_dma_rdata[31:16];
+    dac_ddata_1[15: 0] <= dac_dma_rdata[31:16];
+    dac_ddata_0[63:48] <= dac_dma_rdata[47:32];
+    dac_ddata_0[47:32] <= dac_dma_rdata[47:32];
+    dac_ddata_0[31:16] <= dac_dma_rdata[15: 0];
+    dac_ddata_0[15: 0] <= dac_dma_rdata[15: 0];
+  end
+
+  always @(posedge adc_clk) begin 
+    adc_data_cnt <= ~adc_data_cnt;
+    case ({adc_enable_1, adc_enable_0})
+      2'b10: begin
+        adc_dma_wr <= adc_data_cnt;
+        adc_dma_wdata <= {adc_data_1, adc_dma_wdata[31:16]};
+      end
+      2'b01: begin
+        adc_dma_wr <= adc_data_cnt;
+        adc_dma_wdata <= {adc_data_0, adc_dma_wdata[31:16]};
+      end
+      default: begin
+        adc_dma_wr <= 1'b1;
+        adc_dma_wdata <= {adc_data_1, adc_data_0};
+      end
+    endcase
+  end
+
   system_wrapper i_system_wrapper (
     .ddr3_1_n (ddr3_1_n),
     .ddr3_1_p (ddr3_1_p),
@@ -236,20 +290,39 @@ module system_top (
     .gpio_lcd_tri_io (gpio_lcd),
     .gpio_led_tri_io (gpio_led),
     .gpio_sw_tri_io (gpio_sw),
+    .adc_clk (adc_clk),
     .adc_clk_in_n (adc_clk_in_n),
     .adc_clk_in_p (adc_clk_in_p),
+    .adc_data_0 (adc_data_0),
+    .adc_data_1 (adc_data_1),
     .adc_data_in_n (adc_data_in_n),
     .adc_data_in_p (adc_data_in_p),
+    .adc_dma_sync (1'b1),
+    .adc_dma_wdata (adc_dma_wdata),
+    .adc_dma_wr (adc_dma_wr),
+    .adc_enable_0 (adc_enable_0),
+    .adc_enable_1 (adc_enable_1),
     .adc_or_in_n (adc_or_in_n),
     .adc_or_in_p (adc_or_in_p),
+    .adc_valid_0 (adc_valid_0),
+    .adc_valid_1 (adc_valid_1),
+    .dac_clk (dac_clk),
     .dac_clk_in_n (dac_clk_in_n),
     .dac_clk_in_p (dac_clk_in_p),
     .dac_clk_out_n (dac_clk_out_n),
     .dac_clk_out_p (dac_clk_out_p),
     .dac_data_out_n (dac_data_out_n),
     .dac_data_out_p (dac_data_out_p),
+    .dac_ddata_0 (dac_ddata_0),
+    .dac_ddata_1 (dac_ddata_1),
+    .dac_dma_rd (dac_dma_rd),
+    .dac_dma_rdata (dac_dma_rdata),
+    .dac_enable_0 (dac_enable_0),
+    .dac_enable_1 (dac_enable_1),
     .dac_frame_out_n (dac_frame_out_n),
     .dac_frame_out_p (dac_frame_out_p),
+    .dac_valid_0 (dac_valid_0),
+    .dac_valid_1 (dac_valid_1),
     .ref_clk (ref_clk),
     .hdmi_data (hdmi_data),
     .hdmi_data_e (hdmi_data_e),

projects/fmcomms1/vc707/system_top.v

@@ -182,6 +182,30 @@ module system_top (
 
   output          spdif;
 
+  // internal registers
+
+  reg     [63:0]  dac_ddata_0 = 'd0;
+  reg     [63:0]  dac_ddata_1 = 'd0;
+  reg             dac_dma_rd = 'd0;
+  reg             adc_data_cnt = 'd0;
+  reg             adc_dma_wr = 'd0;
+  reg     [31:0]  adc_dma_wdata = 'd0;
+
+  // internal signals
+
+  wire            dac_clk;
+  wire            dac_valid_0;
+  wire            dac_enable_0;
+  wire            dac_valid_1;
+  wire            dac_enable_1;
+  wire    [63:0]  dac_dma_rdata;
+  wire            adc_clk;
+  wire            adc_valid_0;
+  wire            adc_enable_0;
+  wire    [15:0]  adc_data_0;
+  wire            adc_valid_1;
+  wire            adc_enable_1;
+  wire    [15:0]  adc_data_1;
   wire            ref_clk;
   wire            oddr_ref_clk;
 
@@ -205,6 +229,36 @@ module system_top (
     .O (ref_clk_out_p),
     .OB (ref_clk_out_n));
 
+  always @(posedge dac_clk) begin
+    dac_dma_rd <= dac_valid_0 & dac_enable_0;
+    dac_ddata_1[63:48] <= dac_dma_rdata[63:48];
+    dac_ddata_1[47:32] <= dac_dma_rdata[63:48];
+    dac_ddata_1[31:16] <= dac_dma_rdata[31:16];
+    dac_ddata_1[15: 0] <= dac_dma_rdata[31:16];
+    dac_ddata_0[63:48] <= dac_dma_rdata[47:32];
+    dac_ddata_0[47:32] <= dac_dma_rdata[47:32];
+    dac_ddata_0[31:16] <= dac_dma_rdata[15: 0];
+    dac_ddata_0[15: 0] <= dac_dma_rdata[15: 0];
+  end
+
+  always @(posedge adc_clk) begin 
+    adc_data_cnt <= ~adc_data_cnt;
+    case ({adc_enable_1, adc_enable_0})
+      2'b10: begin
+        adc_dma_wr <= adc_data_cnt;
+        adc_dma_wdata <= {adc_data_1, adc_dma_wdata[31:16]};
+      end
+      2'b01: begin
+        adc_dma_wr <= adc_data_cnt;
+        adc_dma_wdata <= {adc_data_0, adc_dma_wdata[31:16]};
+      end
+      default: begin
+        adc_dma_wr <= 1'b1;
+        adc_dma_wdata <= {adc_data_1, adc_data_0};
+      end
+    endcase
+  end
+
   system_wrapper i_system_wrapper (
     .ddr3_addr (ddr3_addr),
     .ddr3_ba (ddr3_ba),
@@ -230,20 +284,39 @@ module system_top (
     .hdmi_hsync (hdmi_hsync),
     .hdmi_out_clk (hdmi_out_clk),
     .hdmi_vsync (hdmi_vsync),
+    .adc_clk (adc_clk),
     .adc_clk_in_n (adc_clk_in_n),
     .adc_clk_in_p (adc_clk_in_p),
+    .adc_data_0 (adc_data_0),
+    .adc_data_1 (adc_data_1),
     .adc_data_in_n (adc_data_in_n),
     .adc_data_in_p (adc_data_in_p),
+    .adc_dma_sync (1'b1),
+    .adc_dma_wdata (adc_dma_wdata),
+    .adc_dma_wr (adc_dma_wr),
+    .adc_enable_0 (adc_enable_0),
+    .adc_enable_1 (adc_enable_1),
     .adc_or_in_n (adc_or_in_n),
     .adc_or_in_p (adc_or_in_p),
+    .adc_valid_0 (adc_valid_0),
+    .adc_valid_1 (adc_valid_1),
+    .dac_clk (dac_clk),
     .dac_clk_in_n (dac_clk_in_n),
     .dac_clk_in_p (dac_clk_in_p),
     .dac_clk_out_n (dac_clk_out_n),
     .dac_clk_out_p (dac_clk_out_p),
     .dac_data_out_n (dac_data_out_n),
     .dac_data_out_p (dac_data_out_p),
+    .dac_ddata_0 (dac_ddata_0),
+    .dac_ddata_1 (dac_ddata_1),
+    .dac_dma_rd (dac_dma_rd),
+    .dac_dma_rdata (dac_dma_rdata),
+    .dac_enable_0 (dac_enable_0),
+    .dac_enable_1 (dac_enable_1),
     .dac_frame_out_n (dac_frame_out_n),
     .dac_frame_out_p (dac_frame_out_p),
+    .dac_valid_0 (dac_valid_0),
+    .dac_valid_1 (dac_valid_1),
     .ref_clk (ref_clk),
     .iic_main_scl_io (iic_scl),
     .iic_main_sda_io (iic_sda),

projects/fmcomms1/zc702/system_top.v

@@ -151,11 +151,33 @@ module system_top (
   inout           iic_scl;
   inout           iic_sda;
 
+  // internal registers
+
+  reg     [63:0]  dac_ddata_0 = 'd0;
+  reg     [63:0]  dac_ddata_1 = 'd0;
+  reg             dac_dma_rd = 'd0;
+  reg             adc_data_cnt = 'd0;
+  reg             adc_dma_wr = 'd0;
+  reg     [31:0]  adc_dma_wdata = 'd0;
+
   // internal signals
 
   wire    [31:0]  gpio_i;
   wire    [31:0]  gpio_o;
   wire    [31:0]  gpio_t;
+  wire            dac_clk;
+  wire            dac_valid_0;
+  wire            dac_enable_0;
+  wire            dac_valid_1;
+  wire            dac_enable_1;
+  wire    [63:0]  dac_dma_rdata;
+  wire            adc_clk;
+  wire            adc_valid_0;
+  wire            adc_enable_0;
+  wire    [15:0]  adc_data_0;
+  wire            adc_valid_1;
+  wire            adc_enable_1;
+  wire    [15:0]  adc_data_1;
   wire            ref_clk;
   wire            oddr_ref_clk;
 
@@ -190,6 +212,36 @@ module system_top (
   end
   endgenerate
 
+  always @(posedge dac_clk) begin
+    dac_dma_rd <= dac_valid_0 & dac_enable_0;
+    dac_ddata_1[63:48] <= dac_dma_rdata[63:48];
+    dac_ddata_1[47:32] <= dac_dma_rdata[63:48];
+    dac_ddata_1[31:16] <= dac_dma_rdata[31:16];
+    dac_ddata_1[15: 0] <= dac_dma_rdata[31:16];
+    dac_ddata_0[63:48] <= dac_dma_rdata[47:32];
+    dac_ddata_0[47:32] <= dac_dma_rdata[47:32];
+    dac_ddata_0[31:16] <= dac_dma_rdata[15: 0];
+    dac_ddata_0[15: 0] <= dac_dma_rdata[15: 0];
+  end
+
+  always @(posedge adc_clk) begin
+    adc_data_cnt <= ~adc_data_cnt ;
+    case ({adc_enable_1, adc_enable_0})
+      2'b10: begin
+        adc_dma_wr <= adc_data_cnt;
+        adc_dma_wdata <= {adc_data_1, adc_dma_wdata[31:16]};
+      end
+      2'b01: begin
+        adc_dma_wr <= adc_data_cnt;
+        adc_dma_wdata <= {adc_data_0, adc_dma_wdata[31:16]};
+      end
+      default: begin
+        adc_dma_wr <= 1'b1;
+        adc_dma_wdata <= {adc_data_1, adc_data_0};
+      end
+    endcase
+  end
+
   system_wrapper i_system_wrapper (
     .DDR_addr (DDR_addr),
     .DDR_ba (DDR_ba),
@@ -215,20 +267,39 @@ module system_top (
     .GPIO_I (gpio_i),
     .GPIO_O (gpio_o),
     .GPIO_T (gpio_t),
+    .adc_clk (adc_clk),
     .adc_clk_in_n (adc_clk_in_n),
     .adc_clk_in_p (adc_clk_in_p),
+    .adc_data_0 (adc_data_0),
+    .adc_data_1 (adc_data_1),
     .adc_data_in_n (adc_data_in_n),
     .adc_data_in_p (adc_data_in_p),
+    .adc_dma_sync (1'b1),
+    .adc_dma_wdata (adc_dma_wdata),
+    .adc_dma_wr (adc_dma_wr),
+    .adc_enable_0 (adc_enable_0),
+    .adc_enable_1 (adc_enable_1),
     .adc_or_in_n (adc_or_in_n),
     .adc_or_in_p (adc_or_in_p),
+    .adc_valid_0 (adc_valid_0),
+    .adc_valid_1 (adc_valid_1),
+    .dac_clk (dac_clk),
     .dac_clk_in_n (dac_clk_in_n),
     .dac_clk_in_p (dac_clk_in_p),
     .dac_clk_out_n (dac_clk_out_n),
     .dac_clk_out_p (dac_clk_out_p),
     .dac_data_out_n (dac_data_out_n),
     .dac_data_out_p (dac_data_out_p),
+    .dac_ddata_0 (dac_ddata_0),
+    .dac_ddata_1 (dac_ddata_1),
+    .dac_dma_rd (dac_dma_rd),
+    .dac_dma_rdata (dac_dma_rdata),
+    .dac_enable_0 (dac_enable_0),
+    .dac_enable_1 (dac_enable_1),
     .dac_frame_out_n (dac_frame_out_n),
     .dac_frame_out_p (dac_frame_out_p),
+    .dac_valid_0 (dac_valid_0),
+    .dac_valid_1 (dac_valid_1),
     .hdmi_data (hdmi_data),
     .hdmi_data_e (hdmi_data_e),
     .hdmi_hsync (hdmi_hsync),

projects/fmcomms1/zc706/system_top.v

@@ -156,9 +156,9 @@ module system_top (
   reg     [63:0]  dac_ddata_0 = 'd0;
   reg     [63:0]  dac_ddata_1 = 'd0;
   reg             dac_dma_rd = 'd0;
-  reg     [ 1:0]  adc_data_cnt = 'd0;
+  reg             adc_data_cnt = 'd0;
   reg             adc_dma_wr = 'd0;
-  reg     [63:0]  adc_dma_wdata = 'd0;
+  reg     [31:0]  adc_dma_wdata = 'd0;
 
   // internal signals
 
@@ -224,20 +224,20 @@ module system_top (
     dac_ddata_0[15: 0] <= dac_dma_rdata[15: 0];
   end
 
-  always @(posedge adc_clk) begin 
+  always @(posedge adc_clk) begin
-    adc_data_cnt <= adc_data_cnt + 1'b1;
+    adc_data_cnt <= ~adc_data_cnt ;
     case ({adc_enable_1, adc_enable_0})
       2'b10: begin
-        adc_dma_wr <= adc_data_cnt[0] & adc_data_cnt[1];
+        adc_dma_wr <= adc_data_cnt;
-        adc_dma_wdata <= {adc_data_1, adc_dma_wdata[63:16]};
+        adc_dma_wdata <= {adc_data_1, adc_dma_wdata[31:16]};
       end
       2'b01: begin
-        adc_dma_wr <= adc_data_cnt[0] & adc_data_cnt[1];
+        adc_dma_wr <= adc_data_cnt;
-        adc_dma_wdata <= {adc_data_0, adc_dma_wdata[63:16]};
+        adc_dma_wdata <= {adc_data_0, adc_dma_wdata[31:16]};
       end
       default: begin
-        adc_dma_wr <= adc_data_cnt[0];
+        adc_dma_wr <= 1'b1;
-        adc_dma_wdata <= {adc_data_1, adc_data_0, adc_dma_wdata[63:32]};
+        adc_dma_wdata <= {adc_data_1, adc_data_0};
       end
     endcase
   end

projects/fmcomms1/zed/system_top.v

@@ -171,11 +171,33 @@ module system_top (
 
   input           otg_vbusoc;
 
+  // internal registers
+
+  reg     [63:0]  dac_ddata_0 = 'd0;
+  reg     [63:0]  dac_ddata_1 = 'd0;
+  reg             dac_dma_rd = 'd0;
+  reg             adc_data_cnt = 'd0;
+  reg             adc_dma_wr = 'd0;
+  reg     [31:0]  adc_dma_wdata = 'd0;
+
   // internal signals
 
   wire    [31:0]  gpio_i;
   wire    [31:0]  gpio_o;
   wire    [31:0]  gpio_t;
+  wire            dac_clk;
+  wire            dac_valid_0;
+  wire            dac_enable_0;
+  wire            dac_valid_1;
+  wire            dac_enable_1;
+  wire    [63:0]  dac_dma_rdata;
+  wire            adc_clk;
+  wire            adc_valid_0;
+  wire            adc_enable_0;
+  wire    [15:0]  adc_data_0;
+  wire            adc_valid_1;
+  wire            adc_enable_1;
+  wire    [15:0]  adc_data_1;
   wire            ref_clk;
   wire            oddr_ref_clk;
 
@@ -222,6 +244,36 @@ module system_top (
   IOBUF i_iic_mux_sda_0 (.I(iic_mux_sda_o_s[0]), .O(iic_mux_sda_i_s[0]), .T(iic_mux_sda_t_s), .IO(iic_mux_sda[0]));
   IOBUF i_iic_mux_sda_1 (.I(iic_mux_sda_o_s[1]), .O(iic_mux_sda_i_s[1]), .T(iic_mux_sda_t_s), .IO(iic_mux_sda[1]));
 
+  always @(posedge dac_clk) begin
+    dac_dma_rd <= dac_valid_0 & dac_enable_0;
+    dac_ddata_1[63:48] <= dac_dma_rdata[63:48];
+    dac_ddata_1[47:32] <= dac_dma_rdata[63:48];
+    dac_ddata_1[31:16] <= dac_dma_rdata[31:16];
+    dac_ddata_1[15: 0] <= dac_dma_rdata[31:16];
+    dac_ddata_0[63:48] <= dac_dma_rdata[47:32];
+    dac_ddata_0[47:32] <= dac_dma_rdata[47:32];
+    dac_ddata_0[31:16] <= dac_dma_rdata[15: 0];
+    dac_ddata_0[15: 0] <= dac_dma_rdata[15: 0];
+  end
+
+  always @(posedge adc_clk) begin
+    adc_data_cnt <= ~adc_data_cnt ;
+    case ({adc_enable_1, adc_enable_0})
+      2'b10: begin
+        adc_dma_wr <= adc_data_cnt;
+        adc_dma_wdata <= {adc_data_1, adc_dma_wdata[31:16]};
+      end
+      2'b01: begin
+        adc_dma_wr <= adc_data_cnt;
+        adc_dma_wdata <= {adc_data_0, adc_dma_wdata[31:16]};
+      end
+      default: begin
+        adc_dma_wr <= 1'b1;
+        adc_dma_wdata <= {adc_data_1, adc_data_0};
+      end
+    endcase
+  end
+
   system_wrapper i_system_wrapper (
     .DDR_addr (DDR_addr),
     .DDR_ba (DDR_ba),
@@ -247,20 +299,39 @@ module system_top (
     .GPIO_I (gpio_i),
     .GPIO_O (gpio_o),
     .GPIO_T (gpio_t),
+    .adc_clk (adc_clk),
     .adc_clk_in_n (adc_clk_in_n),
     .adc_clk_in_p (adc_clk_in_p),
+    .adc_data_0 (adc_data_0),
+    .adc_data_1 (adc_data_1),
     .adc_data_in_n (adc_data_in_n),
     .adc_data_in_p (adc_data_in_p),
+    .adc_dma_sync (1'b1),
+    .adc_dma_wdata (adc_dma_wdata),
+    .adc_dma_wr (adc_dma_wr),
+    .adc_enable_0 (adc_enable_0),
+    .adc_enable_1 (adc_enable_1),
     .adc_or_in_n (adc_or_in_n),
     .adc_or_in_p (adc_or_in_p),
+    .adc_valid_0 (adc_valid_0),
+    .adc_valid_1 (adc_valid_1),
+    .dac_clk (dac_clk),
     .dac_clk_in_n (dac_clk_in_n),
     .dac_clk_in_p (dac_clk_in_p),
     .dac_clk_out_n (dac_clk_out_n),
     .dac_clk_out_p (dac_clk_out_p),
     .dac_data_out_n (dac_data_out_n),
     .dac_data_out_p (dac_data_out_p),
+    .dac_ddata_0 (dac_ddata_0),
+    .dac_ddata_1 (dac_ddata_1),
+    .dac_dma_rd (dac_dma_rd),
+    .dac_dma_rdata (dac_dma_rdata),
+    .dac_enable_0 (dac_enable_0),
+    .dac_enable_1 (dac_enable_1),
     .dac_frame_out_n (dac_frame_out_n),
     .dac_frame_out_p (dac_frame_out_p),
+    .dac_valid_0 (dac_valid_0),
+    .dac_valid_1 (dac_valid_1),
     .hdmi_data (hdmi_data),
     .hdmi_data_e (hdmi_data_e),
     .hdmi_hsync (hdmi_hsync),