axi_ltc2387: Make adc_valid to represent the current sample
* Before, adc_valid was for the previous sample. This said that at the second rising edge of clk_gate - the first sample is valid, which is not true * Alongside with the software issue that will be solved, these fixes will make the first 2 samples to be with valid data, otherwise the user has to always keep in mind that the first 2 ones are invalid Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>main
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@ -96,7 +96,8 @@ module axi_ltc2387_if #(
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// assignments
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assign adc_valid = ~clk_gate_d[2] & clk_gate_d[1];
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// adc_valid is 1 for the current sample that is sent
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assign adc_valid = clk_gate_d[1] & ~clk_gate_d[0];
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always @(posedge clk) begin
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clk_gate_d <= {clk_gate_d[1:0], clk_gate};
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