fmcomms2_tdd: Update tdd_enabaled path
This line controls the mux, which switch between hdl and software (GPIO) control of the ENABLE/TXNRX pins. Fix the broken path and change the name from "tdd_enable" to "tdd_enabled".main
parent
8e536ad8d1
commit
bcee3e04d4
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@ -108,7 +108,7 @@ module axi_ad9361 (
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dac_dunf,
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dac_r1_mode,
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tdd_enable,
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tdd_enabled,
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enable,
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txnrx,
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@ -227,7 +227,7 @@ module axi_ad9361 (
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input dac_dunf;
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output dac_r1_mode;
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output tdd_enable;
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output tdd_enabled;
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output enable;
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output txnrx;
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@ -407,7 +407,7 @@ module axi_ad9361 (
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.tdd_tx_vco_en(tdd_tx_vco_en_s),
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.tdd_rx_rf_en(tdd_rx_rf_en_s),
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.tdd_tx_rf_en(tdd_tx_rf_en_s),
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.tdd_enable (tdd_enable),
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.tdd_enabled (tdd_enabled),
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.tdd_status(tdd_status_s),
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.tdd_sync_req(tdd_sync_req),
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.tdd_sync_ack(tdd_sync_ack),
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@ -55,7 +55,7 @@ module axi_ad9361_tdd (
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// status signal
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tdd_enable,
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tdd_enabled,
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tdd_status,
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// sync signals
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@ -111,7 +111,7 @@ module axi_ad9361_tdd (
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output tdd_rx_rf_en;
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output tdd_tx_rf_en;
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output tdd_enable;
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output tdd_enabled;
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input [ 7:0] tdd_status;
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inout tdd_sync_req;
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@ -156,7 +156,6 @@ module axi_ad9361_tdd (
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output [41:0] tdd_dbg;
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reg tdd_enable = 1'b0;
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reg tdd_slave_synced = 1'b0;
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reg tdd_sync_o = 1'b0;
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@ -223,6 +222,8 @@ module axi_ad9361_tdd (
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assign tdd_rx_valid_q1 = ((tdd_enable_synced_s & tdd_gated_rx_dmapath_s) == 1'b1) ?
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(rx_valid_q1 & tdd_rx_rf_en) : rx_valid_q1;
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assign tdd_enabled = tdd_enable_synced_s;
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// instantiations
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up_tdd_cntrl i_up_tdd_cntrl(
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@ -17,7 +17,7 @@ create_bd_port -dir O -from 5 -to 0 tx_data_out_n
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create_bd_port -dir O enable
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create_bd_port -dir O txnrx
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create_bd_port -dir O tdd_enable
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create_bd_port -dir O tdd_enabled
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create_bd_port -dir IO tdd_sync_req
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create_bd_port -dir IO tdd_sync_ack
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@ -142,7 +142,7 @@ ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf
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ad_connect tdd_sync_req axi_ad9361/tdd_sync_req
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ad_connect tdd_sync_ack axi_ad9361/tdd_sync_ack
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ad_connect tdd_enable axi_ad9361/tdd_enable
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ad_connect tdd_enabled axi_ad9361/tdd_enabled
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# interconnects
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@ -195,6 +195,6 @@ set_property -dict [list CONFIG.C_PROBE3_WIDTH {35}] $ila_adc
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ad_connect axi_ad9361_clk ila_tdd/clk
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ad_connect axi_ad9361/enable ila_tdd/probe0
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ad_connect axi_ad9361/txnrx ila_tdd/probe1
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ad_connect axi_ad9361/tdd_enable ila_tdd/probe2
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ad_connect axi_ad9361/tdd_enabled ila_tdd/probe2
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ad_connect axi_ad9361/tdd_dbg ila_tdd/probe3
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@ -225,7 +225,7 @@ module system_top (
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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wire tdd_enable_s;
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wire tdd_enabled_s;
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wire gpio_enable;
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wire gpio_txnrx;
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wire enable_s;
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@ -234,8 +234,8 @@ module system_top (
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// assignments
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assign hdmi_pd = 1'b0;
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assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
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assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
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assign enable = (tdd_enabled_s == 1'b1) ? enable_s : gpio_enable;
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assign txnrx = (tdd_enabled_s == 1'b1) ? txnrx_s : gpio_txnrx;
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// instantiations
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@ -363,7 +363,7 @@ module system_top (
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.tx_frame_out_n (tx_frame_out_n),
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.tx_frame_out_p (tx_frame_out_p),
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.txnrx (txnrx_s),
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.tdd_enable (tdd_enable_s),
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.tdd_enabled (tdd_enabled_s),
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.tdd_sync_req (tdd_sync_req),
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.tdd_sync_ack (tdd_sync_ack));
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@ -212,14 +212,14 @@ module system_top (
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wire [31:0] dac_gpio_input;
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wire [31:0] dac_gpio_output;
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wire tdd_enable_s;
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wire tdd_enabled_s;
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wire gpio_enable;
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wire gpio_txnrx;
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wire enable_s;
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wire txnrx_s;
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assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
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assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
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assign enable = (tdd_enabled_s == 1'b1) ? enable_s : gpio_enable;
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assign txnrx = (tdd_enabled_s == 1'b1) ? txnrx_s : gpio_txnrx;
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// instantiations
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@ -320,7 +320,7 @@ module system_top (
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.tx_frame_out_n (tx_frame_out_n),
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.tx_frame_out_p (tx_frame_out_p),
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.txnrx (txnrx_s),
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.tdd_enable (tdd_enable_s),
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.tdd_enabled (tdd_enabled_s),
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.tdd_sync_req(tdd_sync_req),
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.tdd_sync_ack(tdd_sync_ack));
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