library: Use ad_ip_intf_s_axi were applicable

Use the ad_ip_intf_s_axi helper function to create the axi4lite slave
interface for memory mapped peripherals. This slightly reduces the amount
of boilerplate code in the peripheral's *hw.tcl

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

library/altera/axi_adxcvr/axi_adxcvr_hw.tcl

@@ -41,35 +41,7 @@ set_parameter_property NUM_OF_LANES HDL_PARAMETER true
 
 # axi4 slave interface
 
-add_interface s_axi_clock clock end
-add_interface_port s_axi_clock s_axi_aclk clk Input 1
-
-add_interface s_axi_reset reset end
-set_interface_property s_axi_reset associatedClock s_axi_clock
-add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
-
-add_interface s_axi axi4lite end
-set_interface_property s_axi associatedClock s_axi_clock
-set_interface_property s_axi associatedReset s_axi_reset
-add_interface_port s_axi s_axi_awvalid awvalid Input 1
-add_interface_port s_axi s_axi_awaddr awaddr Input 12
-add_interface_port s_axi s_axi_awprot awprot Input 3
-add_interface_port s_axi s_axi_awready awready Output 1
-add_interface_port s_axi s_axi_wvalid wvalid Input 1
-add_interface_port s_axi s_axi_wdata wdata Input 32
-add_interface_port s_axi s_axi_wstrb wstrb Input 4
-add_interface_port s_axi s_axi_wready wready Output 1
-add_interface_port s_axi s_axi_bvalid bvalid Output 1
-add_interface_port s_axi s_axi_bresp bresp Output 2
-add_interface_port s_axi s_axi_bready bready Input 1
-add_interface_port s_axi s_axi_arvalid arvalid Input 1
-add_interface_port s_axi s_axi_araddr araddr Input 12
-add_interface_port s_axi s_axi_arprot arprot Input 3
-add_interface_port s_axi s_axi_arready arready Output 1
-add_interface_port s_axi s_axi_rvalid rvalid Output 1
-add_interface_port s_axi s_axi_rresp rresp Output 2
-add_interface_port s_axi s_axi_rdata rdata Output 32
-add_interface_port s_axi s_axi_rready rready Input 1
+ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12
 
 # xcvr interface
 

library/axi_ad9144/axi_ad9144_hw.tcl

@@ -60,35 +60,7 @@ set_parameter_property DEVICE_TYPE HDL_PARAMETER true
 
 # axi4 slave
 
-add_interface s_axi_clock clock end
-add_interface_port s_axi_clock s_axi_aclk clk Input 1
-
-add_interface s_axi_reset reset end
-set_interface_property s_axi_reset associatedClock s_axi_clock
-add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
-
-add_interface s_axi axi4lite end
-set_interface_property s_axi associatedClock s_axi_clock
-set_interface_property s_axi associatedReset s_axi_reset
-add_interface_port s_axi s_axi_awvalid awvalid Input 1
-add_interface_port s_axi s_axi_awaddr awaddr Input 16
-add_interface_port s_axi s_axi_awprot awprot Input 3
-add_interface_port s_axi s_axi_awready awready Output 1
-add_interface_port s_axi s_axi_wvalid wvalid Input 1
-add_interface_port s_axi s_axi_wdata wdata Input 32
-add_interface_port s_axi s_axi_wstrb wstrb Input 4
-add_interface_port s_axi s_axi_wready wready Output 1
-add_interface_port s_axi s_axi_bvalid bvalid Output 1
-add_interface_port s_axi s_axi_bresp bresp Output 2
-add_interface_port s_axi s_axi_bready bready Input 1
-add_interface_port s_axi s_axi_arvalid arvalid Input 1
-add_interface_port s_axi s_axi_araddr araddr Input 16
-add_interface_port s_axi s_axi_arprot arprot Input 3
-add_interface_port s_axi s_axi_arready arready Output 1
-add_interface_port s_axi s_axi_rvalid rvalid Output 1
-add_interface_port s_axi s_axi_rresp rresp Output 2
-add_interface_port s_axi s_axi_rdata rdata Output 32
-add_interface_port s_axi s_axi_rready rready Input 1
+ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
 
 # transceiver interface
 

library/axi_ad9152/axi_ad9152_hw.tcl

@@ -52,35 +52,7 @@ set_parameter_property DEVICE_TYPE HDL_PARAMETER true
 
 # axi4 slave
 
-add_interface s_axi_clock clock end
-add_interface_port s_axi_clock s_axi_aclk clk Input 1
-
-add_interface s_axi_reset reset end
-set_interface_property s_axi_reset associatedClock s_axi_clock
-add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
-
-add_interface s_axi axi4lite end
-set_interface_property s_axi associatedClock s_axi_clock
-set_interface_property s_axi associatedReset s_axi_reset
-add_interface_port s_axi s_axi_awvalid awvalid Input 1
-add_interface_port s_axi s_axi_awaddr awaddr Input 16
-add_interface_port s_axi s_axi_awprot awprot Input 3
-add_interface_port s_axi s_axi_awready awready Output 1
-add_interface_port s_axi s_axi_wvalid wvalid Input 1
-add_interface_port s_axi s_axi_wdata wdata Input 32
-add_interface_port s_axi s_axi_wstrb wstrb Input 4
-add_interface_port s_axi s_axi_wready wready Output 1
-add_interface_port s_axi s_axi_bvalid bvalid Output 1
-add_interface_port s_axi s_axi_bresp bresp Output 2
-add_interface_port s_axi s_axi_bready bready Input 1
-add_interface_port s_axi s_axi_arvalid arvalid Input 1
-add_interface_port s_axi s_axi_araddr araddr Input 16
-add_interface_port s_axi s_axi_arprot arprot Input 3
-add_interface_port s_axi s_axi_arready arready Output 1
-add_interface_port s_axi s_axi_rvalid rvalid Output 1
-add_interface_port s_axi s_axi_rresp rresp Output 2
-add_interface_port s_axi s_axi_rdata rdata Output 32
-add_interface_port s_axi s_axi_rready rready Input 1
+ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
 
 # transceiver interface
 

library/axi_ad9250/axi_ad9250_hw.tcl

@@ -52,35 +52,7 @@ set_parameter_property DEVICE_TYPE HDL_PARAMETER true
 
 # axi4 slave
 
-add_interface s_axi_clock clock end
-add_interface_port s_axi_clock s_axi_aclk clk Input 1
-
-add_interface s_axi_reset reset end
-set_interface_property s_axi_reset associatedClock s_axi_clock
-add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
-
-add_interface s_axi axi4lite end
-set_interface_property s_axi associatedClock s_axi_clock
-set_interface_property s_axi associatedReset s_axi_reset
-add_interface_port s_axi s_axi_awvalid awvalid Input 1
-add_interface_port s_axi s_axi_awaddr awaddr Input 16
-add_interface_port s_axi s_axi_awprot awprot Input 3
-add_interface_port s_axi s_axi_awready awready Output 1
-add_interface_port s_axi s_axi_wvalid wvalid Input 1
-add_interface_port s_axi s_axi_wdata wdata Input 32
-add_interface_port s_axi s_axi_wstrb wstrb Input 4
-add_interface_port s_axi s_axi_wready wready Output 1
-add_interface_port s_axi s_axi_bvalid bvalid Output 1
-add_interface_port s_axi s_axi_bresp bresp Output 2
-add_interface_port s_axi s_axi_bready bready Input 1
-add_interface_port s_axi s_axi_arvalid arvalid Input 1
-add_interface_port s_axi s_axi_araddr araddr Input 16
-add_interface_port s_axi s_axi_arprot arprot Input 3
-add_interface_port s_axi s_axi_arready arready Output 1
-add_interface_port s_axi s_axi_rvalid rvalid Output 1
-add_interface_port s_axi s_axi_rresp rresp Output 2
-add_interface_port s_axi s_axi_rdata rdata Output 32
-add_interface_port s_axi s_axi_rready rready Input 1
+ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
 
 # transceiver interface
 

library/axi_ad9371/axi_ad9371_hw.tcl

@@ -75,35 +75,7 @@ set_parameter_property ADC_DATAPATH_DISABLE HDL_PARAMETER true
 
 # axi4 slave
 
-add_interface s_axi_clock clock end
-add_interface_port s_axi_clock s_axi_aclk clk Input 1
-
-add_interface s_axi_reset reset end
-set_interface_property s_axi_reset associatedClock s_axi_clock
-add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
-
-add_interface s_axi axi4lite end
-set_interface_property s_axi associatedClock s_axi_clock
-set_interface_property s_axi associatedReset s_axi_reset
-add_interface_port s_axi s_axi_awvalid awvalid Input 1
-add_interface_port s_axi s_axi_awaddr awaddr Input 16
-add_interface_port s_axi s_axi_awprot awprot Input 3
-add_interface_port s_axi s_axi_awready awready Output 1
-add_interface_port s_axi s_axi_wvalid wvalid Input 1
-add_interface_port s_axi s_axi_wdata wdata Input 32
-add_interface_port s_axi s_axi_wstrb wstrb Input 4
-add_interface_port s_axi s_axi_wready wready Output 1
-add_interface_port s_axi s_axi_bvalid bvalid Output 1
-add_interface_port s_axi s_axi_bresp bresp Output 2
-add_interface_port s_axi s_axi_bready bready Input 1
-add_interface_port s_axi s_axi_arvalid arvalid Input 1
-add_interface_port s_axi s_axi_araddr araddr Input 16
-add_interface_port s_axi s_axi_arprot arprot Input 3
-add_interface_port s_axi s_axi_arready arready Output 1
-add_interface_port s_axi s_axi_rvalid rvalid Output 1
-add_interface_port s_axi s_axi_rresp rresp Output 2
-add_interface_port s_axi s_axi_rdata rdata Output 32
-add_interface_port s_axi s_axi_rready rready Input 1
+ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
 
 # transceiver interface
 

library/axi_ad9671/axi_ad9671_hw.tcl

@@ -60,35 +60,7 @@ set_parameter_property QUAD_OR_DUAL_N HDL_PARAMETER true
 
 # axi4 slave
 
-add_interface s_axi_clock clock end
-add_interface_port s_axi_clock s_axi_aclk clk Input 1
-
-add_interface s_axi_reset reset end
-set_interface_property s_axi_reset associatedClock s_axi_clock
-add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
-
-add_interface s_axi axi4lite end
-set_interface_property s_axi associatedClock s_axi_clock
-set_interface_property s_axi associatedReset s_axi_reset
-add_interface_port s_axi s_axi_awvalid awvalid Input 1
-add_interface_port s_axi s_axi_awaddr awaddr Input 16
-add_interface_port s_axi s_axi_awprot awprot Input 3
-add_interface_port s_axi s_axi_awready awready Output 1
-add_interface_port s_axi s_axi_wvalid wvalid Input 1
-add_interface_port s_axi s_axi_wdata wdata Input 32
-add_interface_port s_axi s_axi_wstrb wstrb Input 4
-add_interface_port s_axi s_axi_wready wready Output 1
-add_interface_port s_axi s_axi_bvalid bvalid Output 1
-add_interface_port s_axi s_axi_bresp bresp Output 2
-add_interface_port s_axi s_axi_bready bready Input 1
-add_interface_port s_axi s_axi_arvalid arvalid Input 1
-add_interface_port s_axi s_axi_araddr araddr Input 16
-add_interface_port s_axi s_axi_arprot arprot Input 3
-add_interface_port s_axi s_axi_arready arready Output 1
-add_interface_port s_axi s_axi_rvalid rvalid Output 1
-add_interface_port s_axi s_axi_rresp rresp Output 2
-add_interface_port s_axi s_axi_rdata rdata Output 32
-add_interface_port s_axi s_axi_rready rready Input 1
+ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
 
 # transceiver interface
 

library/axi_ad9680/axi_ad9680_hw.tcl

@@ -52,35 +52,7 @@ set_parameter_property DEVICE_TYPE HDL_PARAMETER true
 
 # axi4 slave
 
-add_interface s_axi_clock clock end
-add_interface_port s_axi_clock s_axi_aclk clk Input 1
-
-add_interface s_axi_reset reset end
-set_interface_property s_axi_reset associatedClock s_axi_clock
-add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
-
-add_interface s_axi axi4lite end
-set_interface_property s_axi associatedClock s_axi_clock
-set_interface_property s_axi associatedReset s_axi_reset
-add_interface_port s_axi s_axi_awvalid awvalid Input 1
-add_interface_port s_axi s_axi_awaddr awaddr Input 16
-add_interface_port s_axi s_axi_awprot awprot Input 3
-add_interface_port s_axi s_axi_awready awready Output 1
-add_interface_port s_axi s_axi_wvalid wvalid Input 1
-add_interface_port s_axi s_axi_wdata wdata Input 32
-add_interface_port s_axi s_axi_wstrb wstrb Input 4
-add_interface_port s_axi s_axi_wready wready Output 1
-add_interface_port s_axi s_axi_bvalid bvalid Output 1
-add_interface_port s_axi s_axi_bresp bresp Output 2
-add_interface_port s_axi s_axi_bready bready Input 1
-add_interface_port s_axi s_axi_arvalid arvalid Input 1
-add_interface_port s_axi s_axi_araddr araddr Input 16
-add_interface_port s_axi s_axi_arprot arprot Input 3
-add_interface_port s_axi s_axi_arready arready Output 1
-add_interface_port s_axi s_axi_rvalid rvalid Output 1
-add_interface_port s_axi s_axi_rresp rresp Output 2
-add_interface_port s_axi s_axi_rdata rdata Output 32
-add_interface_port s_axi s_axi_rready rready Input 1
+ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
 
 # transceiver interface
 

library/axi_dmac/axi_dmac_hw.tcl

@@ -152,35 +152,7 @@ set_parameter_property FIFO_SIZE HDL_PARAMETER true
 
 # axi4 slave
 
-add_interface s_axi_clock clock end
-add_interface_port s_axi_clock s_axi_aclk clk Input 1
-
-add_interface s_axi_reset reset end
-set_interface_property s_axi_reset associatedClock s_axi_clock
-add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
-
-add_interface s_axi axi4lite end
-set_interface_property s_axi associatedClock s_axi_clock
-set_interface_property s_axi associatedReset s_axi_reset
-add_interface_port s_axi s_axi_awvalid awvalid Input 1
-add_interface_port s_axi s_axi_awaddr awaddr Input 14
-add_interface_port s_axi s_axi_awready awready Output 1
-add_interface_port s_axi s_axi_wvalid wvalid Input 1
-add_interface_port s_axi s_axi_wdata wdata Input 32
-add_interface_port s_axi s_axi_wstrb wstrb Input 4
-add_interface_port s_axi s_axi_wready wready Output 1
-add_interface_port s_axi s_axi_bvalid bvalid Output 1
-add_interface_port s_axi s_axi_bresp bresp Output 2
-add_interface_port s_axi s_axi_bready bready Input 1
-add_interface_port s_axi s_axi_arvalid arvalid Input 1
-add_interface_port s_axi s_axi_araddr araddr Input 14
-add_interface_port s_axi s_axi_arready arready Output 1
-add_interface_port s_axi s_axi_rvalid rvalid Output 1
-add_interface_port s_axi s_axi_rresp rresp Output 2
-add_interface_port s_axi s_axi_rdata rdata Output 32
-add_interface_port s_axi s_axi_rready rready Input 1
-add_interface_port s_axi s_axi_awprot awprot Input 3
-add_interface_port s_axi s_axi_arprot arprot Input 3
+ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12
 
 add_interface interrupt_sender interrupt end
 set_interface_property interrupt_sender associatedAddressablePoint ""

library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl

@@ -68,35 +68,7 @@ set_parameter_property EMBEDDED_SYNC HDL_PARAMETER true
 
 # axi4 slave
 
-add_interface s_axi_clock clock end
-add_interface_port s_axi_clock s_axi_aclk clk Input 1
-
-add_interface s_axi_reset reset end
-set_interface_property s_axi_reset associatedClock s_axi_clock
-add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
-
-add_interface s_axi axi4lite end
-set_interface_property s_axi associatedClock s_axi_clock
-set_interface_property s_axi associatedReset s_axi_reset
-add_interface_port s_axi s_axi_awvalid awvalid Input 1
-add_interface_port s_axi s_axi_awaddr awaddr Input 16
-add_interface_port s_axi s_axi_awprot awprot Input 3
-add_interface_port s_axi s_axi_awready awready Output 1
-add_interface_port s_axi s_axi_wvalid wvalid Input 1
-add_interface_port s_axi s_axi_wdata wdata Input 32
-add_interface_port s_axi s_axi_wstrb wstrb Input 4
-add_interface_port s_axi s_axi_wready wready Output 1
-add_interface_port s_axi s_axi_bvalid bvalid Output 1
-add_interface_port s_axi s_axi_bresp bresp Output 2
-add_interface_port s_axi s_axi_bready bready Input 1
-add_interface_port s_axi s_axi_arvalid arvalid Input 1
-add_interface_port s_axi s_axi_araddr araddr Input 16
-add_interface_port s_axi s_axi_arprot arprot Input 3
-add_interface_port s_axi s_axi_arready arready Output 1
-add_interface_port s_axi s_axi_rvalid rvalid Output 1
-add_interface_port s_axi s_axi_rresp rresp Output 2
-add_interface_port s_axi s_axi_rdata rdata Output 32
-add_interface_port s_axi s_axi_rready rready Input 1
+ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
 
 # hdmi interface