axi_dmac: Remove up_write signal
up_write is just an alias for up_wreq these days. Just always use the later and remove the former.main
parent
afea42f444
commit
bdaad46704
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@ -232,7 +232,6 @@ wire up_rreq;
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wire [31:0] up_wdata;
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wire [11:0] up_waddr;
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wire [11:0] up_raddr;
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wire up_write;
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// Scratch register
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reg [31:0] up_scratch = 'h00;
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@ -331,7 +330,7 @@ up_axi #(
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// IRQ handling
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assign up_irq_pending = ~up_irq_mask & up_irq_source;
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assign up_irq_trigger = {up_eot, up_sot};
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assign up_irq_source_clear = (up_write == 1'b1 && up_waddr == 12'h021) ? up_wdata[1:0] : 0;
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assign up_irq_source_clear = (up_wreq == 1'b1 && up_waddr == 12'h021) ? up_wdata[1:0] : 0;
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always @(posedge s_axi_aclk)
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begin
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@ -351,7 +350,6 @@ begin
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end
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// Register Interface
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assign up_write = up_wreq;
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always @(posedge s_axi_aclk)
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begin
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@ -371,7 +369,7 @@ begin
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end else begin
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up_wack <= up_wreq;
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if (up_enable == 1'b1) begin
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if (up_write && up_waddr == 12'h102) begin
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if (up_wreq && up_waddr == 12'h102) begin
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up_dma_req_valid <= up_dma_req_valid | up_wdata[0];
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end else if (up_sot) begin
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up_dma_req_valid <= 1'b0;
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@ -380,7 +378,7 @@ begin
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up_dma_req_valid <= 1'b0;
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end
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if (up_write) begin
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if (up_wreq) begin
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case (up_waddr)
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12'h002: up_scratch <= up_wdata;
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12'h020: up_irq_mask <= up_wdata;
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