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axi_dmac: Remove up_write signal 

up_write is just an alias for up_wreq these days. Just always use the later
and remove the former.
main
Lars-Peter Clausen 2015-01-15 10:58:12 +01:00
parent afea42f444
commit bdaad46704
1 changed files with 3 additions and 5 deletions
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8
library/axi_dmac/axi_dmac.v
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@ -232,7 +232,6 @@ wire up_rreq;
wire [31:0] up_wdata; wire [31:0] up_wdata;
wire [11:0] up_waddr; wire [11:0] up_waddr;
wire [11:0] up_raddr; wire [11:0] up_raddr;
wire up_write;
// Scratch register // Scratch register
reg [31:0] up_scratch = 'h00; reg [31:0] up_scratch = 'h00;
@ -331,7 +330,7 @@ up_axi #(
// IRQ handling // IRQ handling
assign up_irq_pending = ~up_irq_mask & up_irq_source; assign up_irq_pending = ~up_irq_mask & up_irq_source;
assign up_irq_trigger = {up_eot, up_sot}; assign up_irq_trigger = {up_eot, up_sot};
assign up_irq_source_clear = (up_write == 1'b1 && up_waddr == 12'h021) ? up_wdata[1:0] : 0; assign up_irq_source_clear = (up_wreq == 1'b1 && up_waddr == 12'h021) ? up_wdata[1:0] : 0;
always @(posedge s_axi_aclk) always @(posedge s_axi_aclk)
begin begin
@ -351,7 +350,6 @@ begin
end end
// Register Interface // Register Interface
assign up_write = up_wreq;
always @(posedge s_axi_aclk) always @(posedge s_axi_aclk)
begin begin
@ -371,7 +369,7 @@ begin
end else begin end else begin
up_wack <= up_wreq; up_wack <= up_wreq;
if (up_enable == 1'b1) begin if (up_enable == 1'b1) begin
if (up_write && up_waddr == 12'h102) begin if (up_wreq && up_waddr == 12'h102) begin
up_dma_req_valid <= up_dma_req_valid | up_wdata[0]; up_dma_req_valid <= up_dma_req_valid | up_wdata[0];
end else if (up_sot) begin end else if (up_sot) begin
up_dma_req_valid <= 1'b0; up_dma_req_valid <= 1'b0;
@ -380,7 +378,7 @@ begin
up_dma_req_valid <= 1'b0; up_dma_req_valid <= 1'b0;
end end
if (up_write) begin if (up_wreq) begin
case (up_waddr) case (up_waddr)
12'h002: up_scratch <= up_wdata; 12'h002: up_scratch <= up_wdata;
12'h020: up_irq_mask <= up_wdata; 12'h020: up_irq_mask <= up_wdata;