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axi_dac_interpolate: Make dac_reset external

main
Adrian Costina 2017-03-29 11:17:46 +03:00 committed by Lars-Peter Clausen
parent 7227e74444
commit be6fa287fa
3 changed files with 1 additions and 5 deletions
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3
library/axi_dac_interpolate/axi_dac_interpolate.v
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@ -40,6 +40,7 @@
module axi_dac_interpolate(
input dac_clk,
input dac_rst,
input [15:0] dac_data_a,
input [15:0] dac_data_b,
@ -121,8 +122,6 @@ module axi_dac_interpolate(
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
ad_rst i_core_rst_reg (.preset(~up_rstn), .clk(dac_clk), .rst(dac_rst));
fir_interp fir_interpolation_a (
.clk (dac_clk),
.clk_enable (dac_cic_valid_a),

2
library/axi_dac_interpolate/axi_dac_interpolate_constr.xdc
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@ -2,10 +2,8 @@
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_state*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_toggle*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *ad_rst_sync*}]
set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_data* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}]

1
library/axi_dac_interpolate/axi_dac_interpolate_ip.tcl
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@ -6,7 +6,6 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_dac_interpolate
adi_ip_files axi_dac_interpolate [list \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"axi_dac_interpolate_constr.xdc" \
"cic_interp.v" \