From be6fa287fae339a8b1aa60ebd79fff37c1a8d85f Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 29 Mar 2017 11:17:46 +0300 Subject: [PATCH] axi_dac_interpolate: Make dac_reset external --- library/axi_dac_interpolate/axi_dac_interpolate.v | 3 +-- library/axi_dac_interpolate/axi_dac_interpolate_constr.xdc | 2 -- library/axi_dac_interpolate/axi_dac_interpolate_ip.tcl | 1 - 3 files changed, 1 insertion(+), 5 deletions(-) diff --git a/library/axi_dac_interpolate/axi_dac_interpolate.v b/library/axi_dac_interpolate/axi_dac_interpolate.v index f6541ac4d..8cbe1b59f 100644 --- a/library/axi_dac_interpolate/axi_dac_interpolate.v +++ b/library/axi_dac_interpolate/axi_dac_interpolate.v @@ -40,6 +40,7 @@ module axi_dac_interpolate( input dac_clk, + input dac_rst, input [15:0] dac_data_a, input [15:0] dac_data_b, @@ -121,8 +122,6 @@ module axi_dac_interpolate( assign up_clk = s_axi_aclk; assign up_rstn = s_axi_aresetn; - ad_rst i_core_rst_reg (.preset(~up_rstn), .clk(dac_clk), .rst(dac_rst)); - fir_interp fir_interpolation_a ( .clk (dac_clk), .clk_enable (dac_cic_valid_a), diff --git a/library/axi_dac_interpolate/axi_dac_interpolate_constr.xdc b/library/axi_dac_interpolate/axi_dac_interpolate_constr.xdc index dad7bf305..9ee64a1e4 100644 --- a/library/axi_dac_interpolate/axi_dac_interpolate_constr.xdc +++ b/library/axi_dac_interpolate/axi_dac_interpolate_constr.xdc @@ -2,10 +2,8 @@ set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_state*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_toggle*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_toggle*}] -set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *ad_rst_sync*}] set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg && IS_SEQUENTIAL}] set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg && IS_SEQUENTIAL}] set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_data* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}] -set_false_path -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}] diff --git a/library/axi_dac_interpolate/axi_dac_interpolate_ip.tcl b/library/axi_dac_interpolate/axi_dac_interpolate_ip.tcl index b488e0201..e8a98339b 100644 --- a/library/axi_dac_interpolate/axi_dac_interpolate_ip.tcl +++ b/library/axi_dac_interpolate/axi_dac_interpolate_ip.tcl @@ -6,7 +6,6 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create axi_dac_interpolate adi_ip_files axi_dac_interpolate [list \ "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ - "$ad_hdl_dir/library/common/ad_rst.v" \ "$ad_hdl_dir/library/common/up_axi.v" \ "axi_dac_interpolate_constr.xdc" \ "cic_interp.v" \